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Periodic Aperiodic
Symmetrical
Asymmetrical
B
C
D
4321
R1 R2
V1
V2
V2 =
R2
R1
V1
A1
B
C
D
4321
DC
AC
V1
DC
AC
V2
DC
AC
Vn
DC
AC
INV1
INV2
INVn
DC
AC
DC
AC
V1
INV1
INV2
INVn
LOAD LOAD
TRF1
TRF2
TRFn
Design objectives: Low ripple / fast response
Low ripple:
1. Use between 5 and 8 inverter/transformer stages
2. Transformer secondary windings with binary progression, 2V, 4V, 8V…..256V
=> generate any voltage between -512V to +512V with 2V resolution
=> low resolution achieved
Fast response:
1. IGBT switching time and delay
2. Full voltage swing from -512V to 512V
3. 80µs
4321
D
C
B
DC
AC
V1
DC
AC
V2
DC
AC
Vn
DC
AC
INV1
INV2
INVn
DC
AC
DC
AC
V1
INV1
INV2
INVn
LOAD LOAD
TRF1
TRF2
TRFn
2v
4v
256v
1 2 3 4
A
B
C
D
4321
D
C
B
A
S iz eA 4
N umbe r:
D ate:
File:
S hee t of
D ES IGN E D B Y
D RA W N BY
C HE C KE D B Y
D ATE
D ATE
D ATE
C LIEN T
D ES C RIP TION
R ev is ion:
Issue:
R EV ISION H IS TOR Y
FIGURE - 00
1
A
1
20 12-03 -1 6
20 12-03 -1 6
20 12-03 -1 6
D r A ndri es P utte r
D r A ndri es P utte r
D r A ndri es P utte r
INT E RN A L - D ES IGN & D EV
B in ary Inve rter
20 12-03 -1 6 / ISS U E 1 - R E V A
BBMLI
ADC DEC
32bits8bits
±4V ±310V
±4V ±310V
DECODER DELAY ±310V±4V ADC
8bits
32bits
POWER SECTION
BATTERY
BATTERY
BATTERY
1 2 3 4
A
B
C
DD
C
B
A
S iz eA 4
N umbe r:
D ate:
File:
S hee t of
D ES IGN E D B Y
D RA W N BY
C HE C KE D B Y
D ATE
D ATE
D ATE
C LIEN T
D ES C RIP TION
R ev is ion:
Issue:
R EV ISION H IS TOR Y
FIGURE - 06
1
A
1
20 12-03 -1 6
20 12-03 -1 6
20 12-03 -1 6
D r A ndri es P utte r
D r A ndri es P utte r
D r A ndri es P utte r
INT E RN A L - D ES IGN & D EV
N on-i nvertin g Op -A m p ci rcui t w i th B B ML I
20 12-03 -1 6 / ISS U E 1 - R E V A
R1 R2
V1
V2
V2 =
R2
R1
V1
ADC
ISOLATED
STEP DOWN
VOLTAGE SENSOR
A1
A2
V3
±4V ±310V
DEC
32bits8bits
BATTERY
1 2 3 4
A
B
C
DD
C
B
A
S iz eA 4
N umbe r:
D ate:
File:
S hee t of
D ES IGN E D B Y
D RA W N BY
C HE C KE D B Y
D ATE
D ATE
D ATE
C LIEN T
D ES C RIP TION
R ev is ion:
Issue:
R EV ISION H IS TOR Y
FIGURE - 06
1
A
1
20 12-03 -1 6
20 12-03 -1 6
20 12-03 -1 6
D r A ndri es P utte r
D r A ndri es P utte r
D r A ndri es P utte r
INT E RN A L - D ES IGN & D EV
N on-i nvertin g Op -A m p ci rcui t w i th B B ML I
20 12-03 -1 6 / ISS U E 1 - R E V A
R1 R2
V1
V2
V2 =
R2
R1
V1
ADC
ISOLATED
STEP DOWN
VOLTAGE SENSOR
A1
A2
V3
±4V ±310V
DEC
32bits8bits
BATTERY
1000kHz 100kHz 50kHz 33kHz 25kHz 5kHz
1μs 10μs 20μs 30μs 40μs 200μs
2 8138Hz 8138Hz 8113Hz 4975Hz 2438Hz 563Hz
4 4050Hz 4050Hz 4050Hz 4050Hz 4050Hz 650Hz
8 2000Hz 2000Hz 2000Hz 2000Hz 2000Hz 575Hz
16 1000Hz 1000Hz 1000Hz 1000Hz 1000Hz 825Hz
32 500Hz 500Hz 500Hz 500Hz 500Hz 500Hz
64 250Hz 250Hz 250Hz 250Hz 250Hz 250Hz
128 100Hz 100Hz 100Hz 100Hz 100Hz 100Hz
256 50Hz 50Hz 50Hz 50Hz 50Hz 50Hz
21
D
C
B
DC
AC
V1
DC
AC
V2
DC
AC
Vn
INV1
INV2
INVn
LOAD
6V
12v
192v
+
AC
DC
DC
AC
DUAL CONVERSION ONLINE UPS TOPOLOGY
LOADUTILITYCONNECTION
RECTIFIER INVERTER
BATTERY
GRID
DIESEL
ENGINE
CLUTCH SYNCHRONOUS
MACHINE
FLYWHEEL
BY-PASS
CHOKE CHOKE
LOAD
UTILITYCONNECTION
D C
A C
+ LOAD
INVERTERDURATHON
S1
S2
S3
BBMLI
BBMLI = Bi-directional Binary Multi Level Inverter
LINE CHOKE
High power digital amplifier

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High power digital amplifier

  • 3.
  • 4.
  • 6. Design objectives: Low ripple / fast response Low ripple: 1. Use between 5 and 8 inverter/transformer stages 2. Transformer secondary windings with binary progression, 2V, 4V, 8V…..256V => generate any voltage between -512V to +512V with 2V resolution => low resolution achieved Fast response: 1. IGBT switching time and delay 2. Full voltage swing from -512V to 512V 3. 80µs 4321 D C B DC AC V1 DC AC V2 DC AC Vn DC AC INV1 INV2 INVn DC AC DC AC V1 INV1 INV2 INVn LOAD LOAD TRF1 TRF2 TRFn 2v 4v 256v
  • 7. 1 2 3 4 A B C D 4321 D C B A S iz eA 4 N umbe r: D ate: File: S hee t of D ES IGN E D B Y D RA W N BY C HE C KE D B Y D ATE D ATE D ATE C LIEN T D ES C RIP TION R ev is ion: Issue: R EV ISION H IS TOR Y FIGURE - 00 1 A 1 20 12-03 -1 6 20 12-03 -1 6 20 12-03 -1 6 D r A ndri es P utte r D r A ndri es P utte r D r A ndri es P utte r INT E RN A L - D ES IGN & D EV B in ary Inve rter 20 12-03 -1 6 / ISS U E 1 - R E V A BBMLI ADC DEC 32bits8bits ±4V ±310V ±4V ±310V DECODER DELAY ±310V±4V ADC 8bits 32bits POWER SECTION BATTERY BATTERY BATTERY
  • 8. 1 2 3 4 A B C DD C B A S iz eA 4 N umbe r: D ate: File: S hee t of D ES IGN E D B Y D RA W N BY C HE C KE D B Y D ATE D ATE D ATE C LIEN T D ES C RIP TION R ev is ion: Issue: R EV ISION H IS TOR Y FIGURE - 06 1 A 1 20 12-03 -1 6 20 12-03 -1 6 20 12-03 -1 6 D r A ndri es P utte r D r A ndri es P utte r D r A ndri es P utte r INT E RN A L - D ES IGN & D EV N on-i nvertin g Op -A m p ci rcui t w i th B B ML I 20 12-03 -1 6 / ISS U E 1 - R E V A R1 R2 V1 V2 V2 = R2 R1 V1 ADC ISOLATED STEP DOWN VOLTAGE SENSOR A1 A2 V3 ±4V ±310V DEC 32bits8bits BATTERY
  • 9. 1 2 3 4 A B C DD C B A S iz eA 4 N umbe r: D ate: File: S hee t of D ES IGN E D B Y D RA W N BY C HE C KE D B Y D ATE D ATE D ATE C LIEN T D ES C RIP TION R ev is ion: Issue: R EV ISION H IS TOR Y FIGURE - 06 1 A 1 20 12-03 -1 6 20 12-03 -1 6 20 12-03 -1 6 D r A ndri es P utte r D r A ndri es P utte r D r A ndri es P utte r INT E RN A L - D ES IGN & D EV N on-i nvertin g Op -A m p ci rcui t w i th B B ML I 20 12-03 -1 6 / ISS U E 1 - R E V A R1 R2 V1 V2 V2 = R2 R1 V1 ADC ISOLATED STEP DOWN VOLTAGE SENSOR A1 A2 V3 ±4V ±310V DEC 32bits8bits BATTERY
  • 10. 1000kHz 100kHz 50kHz 33kHz 25kHz 5kHz 1μs 10μs 20μs 30μs 40μs 200μs 2 8138Hz 8138Hz 8113Hz 4975Hz 2438Hz 563Hz 4 4050Hz 4050Hz 4050Hz 4050Hz 4050Hz 650Hz 8 2000Hz 2000Hz 2000Hz 2000Hz 2000Hz 575Hz 16 1000Hz 1000Hz 1000Hz 1000Hz 1000Hz 825Hz 32 500Hz 500Hz 500Hz 500Hz 500Hz 500Hz 64 250Hz 250Hz 250Hz 250Hz 250Hz 250Hz 128 100Hz 100Hz 100Hz 100Hz 100Hz 100Hz 256 50Hz 50Hz 50Hz 50Hz 50Hz 50Hz
  • 12.
  • 13.
  • 14. + AC DC DC AC DUAL CONVERSION ONLINE UPS TOPOLOGY LOADUTILITYCONNECTION RECTIFIER INVERTER BATTERY
  • 16. UTILITYCONNECTION D C A C + LOAD INVERTERDURATHON S1 S2 S3 BBMLI BBMLI = Bi-directional Binary Multi Level Inverter LINE CHOKE