- The document describes the design of a power-efficient full adder circuit using Cadence Virtuoso 180nm CMOS technology. - Three different designs for the full adder are presented: using gates, using multiplexers, and using half adders. - The design using gates has the lowest power dissipation of 232.38pW but uses 53 transistors, while the design using half adders uses only 18 transistors with a power dissipation of 109.3uW. - Simulation results for power dissipation, delay, and number of transistors are provided for each design and compared to previous work. The full adder circuit was shown to operate as intended based on the simulations.