FPGAs on The Cloud document discusses Amazon Web Services (AWS) F1 FPGA instances that allow users to run FPGA designs on the cloud without needing to purchase hardware. Key points:
- AWS F1 offers FPGA instances with Xilinx UltraScale+ FPGAs and provides an integrated development environment for working with FPGA designs.
- Users can develop FPGA accelerated applications using SDAccel with OpenCL or by creating custom kernels packaged as SDAccel kernels.
- Compiled FPGA bitstreams are packaged in secure Amazon FPGA Images (AFIs) that can be loaded onto instances for execution.
- The document provides examples of running the Smith-Waterman
What are the different opportunities for a VLSI Front end Verification engineer? What career path exists and how to build a career path in Verification of VLSI chip designs?
Sharing my experiences and Career journey as Verification Engineer
During the CXL Forum at OCP Global Summit, memory system architect Jungmin Choi of SK hynix talks about the need for memory bandwidth and capacity, and the SK hynix Niagara solution.
Reliability, Availability, and Serviceability (RAS) on ARM64 status - SFO17-203Linaro
Session ID: SFO17-203
Session Name: Reliability, Availability, and Serviceability (RAS) on ARM64 status - SFO17-203
Speaker: Fu Wei
Track: LEG
★ Session Summary ★
This presentation gives an updated RAS architecture on ARM64 base on RAS extension (in ARMv8.2), SDEI (Software Delegated Exception Interface), APEI, UEFI PI-SMM. Will talk about all the components of the new RAS architecture on ARM64, gives audience the current status and the next step of development.
---------------------------------------------------
★ Resources ★
Event Page: http://connect.linaro.org/resource/sfo17/sfo17-203/
Presentation:
Video: https://www.youtube.com/watch?v=NReFBzbeWi0
---------------------------------------------------
★ Event Details ★
Linaro Connect San Francisco 2017 (SFO17)
25-29 September 2017
Hyatt Regency San Francisco Airport
---------------------------------------------------
Keyword:
'http://www.linaro.org'
'http://connect.linaro.org'
---------------------------------------------------
Follow us on Social Media
https://www.facebook.com/LinaroOrg
https://twitter.com/linaroorg
https://www.youtube.com/user/linaroorg?sub_confirmation=1
https://www.linkedin.com/company/1026961
For the full video of this presentation, please visit:
http://www.embedded-vision.com/platinum-members/altera/embedded-vision-training/videos/pages/may-2016-embedded-vision-summit
For more information about embedded vision, please visit:
http://www.embedded-vision.com
Bill Jenkins, Senior Product Specialist for High Level Design Tools at Intel, presents the "Accelerating Deep Learning Using Altera FPGAs" tutorial at the May 2016 Embedded Vision Summit.
While large strides have recently been made in the development of high-performance systems for neural networks based on multi-core technology, significant challenges in power, cost and, performance scaling remain. Field-programmable gate arrays (FPGAs) are a natural choice for implementing neural networks because they can combine computing, logic, and memory resources in a single device. Intel's Programmable Solutions Group has developed a scalable convolutional neural network reference design for deep learning systems using the OpenCL programming language built with our SDK for OpenCL. The design performance is being benchmarked using several popular CNN benchmarks: CIFAR-10, ImageNet and KITTI.
Building the CNN with OpenCL kernels allows true scaling of the design from smaller to larger devices and from one device generation to the next. New designs can be sized using different numbers of kernels at each layer. Performance scaling from one generation to the next also benefits from architectural advancements, such as floating-point engines and frequency scaling. Thus, you achieve greater than linear performance and performance per watt scaling with each new series of devices.
What are the different opportunities for a VLSI Front end Verification engineer? What career path exists and how to build a career path in Verification of VLSI chip designs?
Sharing my experiences and Career journey as Verification Engineer
During the CXL Forum at OCP Global Summit, memory system architect Jungmin Choi of SK hynix talks about the need for memory bandwidth and capacity, and the SK hynix Niagara solution.
Reliability, Availability, and Serviceability (RAS) on ARM64 status - SFO17-203Linaro
Session ID: SFO17-203
Session Name: Reliability, Availability, and Serviceability (RAS) on ARM64 status - SFO17-203
Speaker: Fu Wei
Track: LEG
★ Session Summary ★
This presentation gives an updated RAS architecture on ARM64 base on RAS extension (in ARMv8.2), SDEI (Software Delegated Exception Interface), APEI, UEFI PI-SMM. Will talk about all the components of the new RAS architecture on ARM64, gives audience the current status and the next step of development.
---------------------------------------------------
★ Resources ★
Event Page: http://connect.linaro.org/resource/sfo17/sfo17-203/
Presentation:
Video: https://www.youtube.com/watch?v=NReFBzbeWi0
---------------------------------------------------
★ Event Details ★
Linaro Connect San Francisco 2017 (SFO17)
25-29 September 2017
Hyatt Regency San Francisco Airport
---------------------------------------------------
Keyword:
'http://www.linaro.org'
'http://connect.linaro.org'
---------------------------------------------------
Follow us on Social Media
https://www.facebook.com/LinaroOrg
https://twitter.com/linaroorg
https://www.youtube.com/user/linaroorg?sub_confirmation=1
https://www.linkedin.com/company/1026961
For the full video of this presentation, please visit:
http://www.embedded-vision.com/platinum-members/altera/embedded-vision-training/videos/pages/may-2016-embedded-vision-summit
For more information about embedded vision, please visit:
http://www.embedded-vision.com
Bill Jenkins, Senior Product Specialist for High Level Design Tools at Intel, presents the "Accelerating Deep Learning Using Altera FPGAs" tutorial at the May 2016 Embedded Vision Summit.
While large strides have recently been made in the development of high-performance systems for neural networks based on multi-core technology, significant challenges in power, cost and, performance scaling remain. Field-programmable gate arrays (FPGAs) are a natural choice for implementing neural networks because they can combine computing, logic, and memory resources in a single device. Intel's Programmable Solutions Group has developed a scalable convolutional neural network reference design for deep learning systems using the OpenCL programming language built with our SDK for OpenCL. The design performance is being benchmarked using several popular CNN benchmarks: CIFAR-10, ImageNet and KITTI.
Building the CNN with OpenCL kernels allows true scaling of the design from smaller to larger devices and from one device generation to the next. New designs can be sized using different numbers of kernels at each layer. Performance scaling from one generation to the next also benefits from architectural advancements, such as floating-point engines and frequency scaling. Thus, you achieve greater than linear performance and performance per watt scaling with each new series of devices.
RoCEv2 is an extension of the original RoCE specification announced in 2010 that brought the benefits of Remote Direct Memory Access (RDMA) I/O architecture to Ethernet-based networks. RoCEv2 addresses the needs of today’s evolving enterprise data centers by enabling routing across Layer 3 networks. Extending RoCE to allow Layer 3 routing provides better traffic isolation and enables hyperscale data center deployments.
Watch the video presentation: http://insidehpc.com/2014/09/slidecast-ibta-releases-updated-specification-rocev2/
introduction to Embedded System & Design.
Embedded systems overview
What are they?
Design challenge – optimizing design metrics
Technologies
Processor technologies
IC technologies
Design technologies
Simultaneously Leveraging Linux and Android in a GENIVI compliant IVI System mentoresd
Simultaneously Leveraging Linux and Android in a GENIVI compliant IVI System – Andrew Patterson
It is widely accepted that Linux is the operating system of choice when building a complex, in-vehicle infotainment (IVI) system. The ability to support and quickly integrate device drivers for features such as CAN, MOST, graphics accelerators, networking interfaces, and Bluetooth can result in key differentiators for any GENIVI compliant IVI-based system. But what if Android was introduced as a second operating system? This session multiple implementations integrating both Android and Linux on multicore SoCs sharing audio and video resources across both domains while maintaining GENIVI compliance. Implementations with and without hypervisor technology will also be presented.
LCU13: Deep Dive into ARM Trusted Firmware
Resource: LCU13
Name: Deep Dive into ARM Trusted Firmware
Date: 31-10-2013
Speaker: Dan Handley / Charles Garcia-Tobin
XPDDS19: [ARM] OP-TEE Mediator in Xen - Volodymyr Babchuk, EPAM SystemsThe Linux Foundation
Volodymyr will speak about TEE mediators. This is a new feature in Xen which allows multiple virtual machines to interact with Trusted Execution Environment available on platform. He developed mediator for one of TEEs, namely OP-TEE.
He will give background information on why TEE is needed at all and share some implementation details.
LCU13: An Introduction to ARM Trusted FirmwareLinaro
Resource: LCU13
Name: An Introduction to ARM Trusted Firmware
Date: 28-10-2013
Speaker: Andrew Thoelke
Video: http://www.youtube.com/watch?v=q32BEMMxmfw
Introduction to binary translation in QEMU(TCG). Describe how it works. In addition, there is a section which demonstrate qemu-monitor, a debug tool for AArch64/QEMU.
There are lots of animations in the slides so download and open it with Microsoft PowerPoint for the best experience. Below is the download link.
Google Driver Link: http://goo.gl/XXMC9X
BUD17-209: Reliability, Availability, and Serviceability (RAS) on ARM64 Linaro
BUD17-209: Reliability, Availability, and Serviceability (RAS) on ARM64
Speaker: Wei Fu
Track: LEG
★ Session Summary ★
The RAS architecture base on RAS extension, SDEI, APEI.
1. the definition, Function and importance of RAS
2. Hardware requirement: CPU, GIC and RAS Extension
3. Firmware support : SDEI dispatcher and APEI support, and how to take advantage of RAS Extension.
4. OS support: APEI driver and SDEI client, error report mechanism(trace event)
5. Userspace recorder: rasdaemon
---------------------------------------------------
★ Resources ★
Event Page: http://connect.linaro.org/resource/bud17/bud17-209/
Presentation:
Video:
---------------------------------------------------
★ Event Details ★
Linaro Connect Budapest 2017 (BUD17)
6-10 March 2017
Corinthia Hotel, Budapest,
Erzsébet krt. 43-49,
1073 Hungary
---------------------------------------------------
ARM64, LEG, RAS
http://www.linaro.org
http://connect.linaro.org
---------------------------------------------------
Follow us on Social Media
https://www.facebook.com/LinaroOrg
https://twitter.com/linaroorg
https://www.youtube.com/user/linaroorg?sub_confirmation=1
https://www.linkedin.com/company/1026961
"
CFD acceleration with FPGA (byteLAKE's presentation from PPAM 2019)byteLAKE
byteLAKE's presentation from the PPAM 2019 conference.
Abstract:
The goal of this work is to adapt 4 CFD kernels to the Xilinx ALVEO U250 FPGA, including first-order step of the non-linear iterative upwind advection MPDATA schemes (non-oscillatory forward in time), the divergence part of the matrix-free linear operator formulation in the iterative Krylov scheme, tridiagonal Thomas algorithm for vertical matrix inversion inside preconditioner for the iterative solver, and computation of the psuedovelocity for the second pass of upwind algorithm in MPDATA. All the kernels use 3-dimensional compute domain consisted from 7 to 11 arrays. Since all kernels belong to the group of memory bound algorithms, our main challenge is to provide the highest utilization of global memory bandwidth. Our adaptation allows us to reduce the execution time upto 4x.
Find out more at: www.byteLAKE.com/en/CFD
Foot note:
This is the presentation about the non-AI version of byteLAKE's CFD kernels, highly optimized for Alveo FPGA. Based on this research project and many others in the CFD space, we decided to shift the course of the CFD Suite product development and leverage AI to accelerate computations and enable new possibilities. Instead of adapting CFD solvers to accelerators, we use AI and work on a cross-platform solution. More on the latest: www.byteLAKE.com/en/CFDSuite.
-
Update for 2020: byteLAKE is currently developing CFD Suite as AI for CFD Suite, a collection of AI/ Artificial Intelligence Models to accelerate and enable new features for CFD simulations. It is a cross-platform solution (not only for FPGAs). More: www.byteLAKE.com/en/CFDSuite.
POLYTEDA LLC a provider of semiconductor design software and PV-services, announced the general availability of PowerDRC/LVS version 2.0.1. This release is dedicated to delivering further significant improvements for multi-CPU mode and some new LVS functionality. From now XOR operation supports multi-CPU mode to dramatically increase performance
RoCEv2 is an extension of the original RoCE specification announced in 2010 that brought the benefits of Remote Direct Memory Access (RDMA) I/O architecture to Ethernet-based networks. RoCEv2 addresses the needs of today’s evolving enterprise data centers by enabling routing across Layer 3 networks. Extending RoCE to allow Layer 3 routing provides better traffic isolation and enables hyperscale data center deployments.
Watch the video presentation: http://insidehpc.com/2014/09/slidecast-ibta-releases-updated-specification-rocev2/
introduction to Embedded System & Design.
Embedded systems overview
What are they?
Design challenge – optimizing design metrics
Technologies
Processor technologies
IC technologies
Design technologies
Simultaneously Leveraging Linux and Android in a GENIVI compliant IVI System mentoresd
Simultaneously Leveraging Linux and Android in a GENIVI compliant IVI System – Andrew Patterson
It is widely accepted that Linux is the operating system of choice when building a complex, in-vehicle infotainment (IVI) system. The ability to support and quickly integrate device drivers for features such as CAN, MOST, graphics accelerators, networking interfaces, and Bluetooth can result in key differentiators for any GENIVI compliant IVI-based system. But what if Android was introduced as a second operating system? This session multiple implementations integrating both Android and Linux on multicore SoCs sharing audio and video resources across both domains while maintaining GENIVI compliance. Implementations with and without hypervisor technology will also be presented.
LCU13: Deep Dive into ARM Trusted Firmware
Resource: LCU13
Name: Deep Dive into ARM Trusted Firmware
Date: 31-10-2013
Speaker: Dan Handley / Charles Garcia-Tobin
XPDDS19: [ARM] OP-TEE Mediator in Xen - Volodymyr Babchuk, EPAM SystemsThe Linux Foundation
Volodymyr will speak about TEE mediators. This is a new feature in Xen which allows multiple virtual machines to interact with Trusted Execution Environment available on platform. He developed mediator for one of TEEs, namely OP-TEE.
He will give background information on why TEE is needed at all and share some implementation details.
LCU13: An Introduction to ARM Trusted FirmwareLinaro
Resource: LCU13
Name: An Introduction to ARM Trusted Firmware
Date: 28-10-2013
Speaker: Andrew Thoelke
Video: http://www.youtube.com/watch?v=q32BEMMxmfw
Introduction to binary translation in QEMU(TCG). Describe how it works. In addition, there is a section which demonstrate qemu-monitor, a debug tool for AArch64/QEMU.
There are lots of animations in the slides so download and open it with Microsoft PowerPoint for the best experience. Below is the download link.
Google Driver Link: http://goo.gl/XXMC9X
BUD17-209: Reliability, Availability, and Serviceability (RAS) on ARM64 Linaro
BUD17-209: Reliability, Availability, and Serviceability (RAS) on ARM64
Speaker: Wei Fu
Track: LEG
★ Session Summary ★
The RAS architecture base on RAS extension, SDEI, APEI.
1. the definition, Function and importance of RAS
2. Hardware requirement: CPU, GIC and RAS Extension
3. Firmware support : SDEI dispatcher and APEI support, and how to take advantage of RAS Extension.
4. OS support: APEI driver and SDEI client, error report mechanism(trace event)
5. Userspace recorder: rasdaemon
---------------------------------------------------
★ Resources ★
Event Page: http://connect.linaro.org/resource/bud17/bud17-209/
Presentation:
Video:
---------------------------------------------------
★ Event Details ★
Linaro Connect Budapest 2017 (BUD17)
6-10 March 2017
Corinthia Hotel, Budapest,
Erzsébet krt. 43-49,
1073 Hungary
---------------------------------------------------
ARM64, LEG, RAS
http://www.linaro.org
http://connect.linaro.org
---------------------------------------------------
Follow us on Social Media
https://www.facebook.com/LinaroOrg
https://twitter.com/linaroorg
https://www.youtube.com/user/linaroorg?sub_confirmation=1
https://www.linkedin.com/company/1026961
"
CFD acceleration with FPGA (byteLAKE's presentation from PPAM 2019)byteLAKE
byteLAKE's presentation from the PPAM 2019 conference.
Abstract:
The goal of this work is to adapt 4 CFD kernels to the Xilinx ALVEO U250 FPGA, including first-order step of the non-linear iterative upwind advection MPDATA schemes (non-oscillatory forward in time), the divergence part of the matrix-free linear operator formulation in the iterative Krylov scheme, tridiagonal Thomas algorithm for vertical matrix inversion inside preconditioner for the iterative solver, and computation of the psuedovelocity for the second pass of upwind algorithm in MPDATA. All the kernels use 3-dimensional compute domain consisted from 7 to 11 arrays. Since all kernels belong to the group of memory bound algorithms, our main challenge is to provide the highest utilization of global memory bandwidth. Our adaptation allows us to reduce the execution time upto 4x.
Find out more at: www.byteLAKE.com/en/CFD
Foot note:
This is the presentation about the non-AI version of byteLAKE's CFD kernels, highly optimized for Alveo FPGA. Based on this research project and many others in the CFD space, we decided to shift the course of the CFD Suite product development and leverage AI to accelerate computations and enable new possibilities. Instead of adapting CFD solvers to accelerators, we use AI and work on a cross-platform solution. More on the latest: www.byteLAKE.com/en/CFDSuite.
-
Update for 2020: byteLAKE is currently developing CFD Suite as AI for CFD Suite, a collection of AI/ Artificial Intelligence Models to accelerate and enable new features for CFD simulations. It is a cross-platform solution (not only for FPGAs). More: www.byteLAKE.com/en/CFDSuite.
POLYTEDA LLC a provider of semiconductor design software and PV-services, announced the general availability of PowerDRC/LVS version 2.0.1. This release is dedicated to delivering further significant improvements for multi-CPU mode and some new LVS functionality. From now XOR operation supports multi-CPU mode to dramatically increase performance
Watch the replay: http://cs.co/9000DCie4
In today’s digital economy, getting ahead means crunching a lot of data. That’s why businesses of all sizes and industries are investing in high-performance computing. However, the last thing IT needs is another tech silo to manage.
Fortunately, the new Cisco UCS C4200 Series chassis and C125 M5 server node help you scale out compute-intensive workloads with ease—with the network fabric you already have. This TechWiseTV Workshop will get you up to speed fast.
Resources:
Watch the related TechWiseTV episode: http://cs.co/9006DAVPC
TechWiseTV: http://cs.co/9009DzrjN
Many companies build new-age KVM clouds, only to find out that their applications & workloads do not perform well. In this talk we’ll show you how to get the most out of your KVM cloud and how to optimize it for performance: You’ll understand why performance matters and how to measure it properly. We’ll teach you how to optimize CPU and memory for ultimate performance and how to tune the storage layer for performance. You’ll find out what are the main components of an efficient new-age cloud and which network components work best. In addition, you’ll learn how to select the right hardware to achieve unmatched performance for your new-age cloud and applications.
Venko Moyankov is an experienced system administrator and solutions architect at StorPool storage. He has experience with managing large virtualizations, working in telcos, designing and supporting the infrastructure of large enterprises. In the last year, his focus has been in helping companies globally to build the best storage solution according to their needs and projects.
Amazon EC2 F1 is a new compute instance with programmable hardware for application acceleration. With F1, you can directly access custom FPGA hardware on the instance in a few clicks.
Learning Objectives:
• Learn about the capabilities, features, and benefits of the new F1 instances
• Develop your FPGA using the F1 Hardware Developer Kit and FPGA Developer AMI
• Deploy your FPGA acceleration code using F1 instances
• Use F1 instances for hardware acceleration in your applications
• Learn how to offer pre-packaged Amazon FPGA Machine Images (AFIs) to your customers through the AWS Marketplace
Achieving the Ultimate Performance with KVMDevOps.com
Building and managing a cloud is not an easy task. It needs solid knowledge, proper planning and extensive experience in selecting the proper components and putting them together.
Many companies build new-age KVM clouds, only to find out that their applications & workloads do not perform well. Join this webinar to learn how to get the most out of your KVM cloud and how to optimize it for performance.
Join this webinar and learn:
Why performance matters and how to measure it properly?
What are the main components of an efficient new-age cloud?
How to select the right hardware?
How to optimize CPU and memory for ultimate performance?
Which network components work best?
How to tune the storage layer for performance?
This presentation is about creating software for for hardware which does not exist yet. In particular, it explains how to add support of new hardware to QEMU (I2C Accelerometer), how to simulate new hardware, write a simple application to work with accelerometer, and demonstrate that it works on the real platform as well as under QEMU.
Presentation by Igor Kaplinsky (Senior Embedded Software Developer, GlobalLogic, Kyiv), Taras Protsiv (Embedded Software Developer GlobalLogic, Kyiv), and Volodymyr Shymanskyy (Embedded Software Developer, GlobalLogic, Kyiv), Embedded TechTalk, Lviv, 2014.
More details -
http://www.globallogic.com.ua/press-releases/embedded-lviv-techtalk-2-coverage
POLYTEDA LLC, a provider of semiconductor design software and PV-services announced the general availability of PowerDRC/LVS version 2.2.
This release is dedicated to delivering fill layer generation for multi-CPU mode, new KLayout integration functionality and other significant improvements for multi-CPU mode
The TMS320C6472 DSP is a six-core, fixed-point DSP from Texas instrument and two of these are integrated onto the Sundance EVP6472. Each DSP Core is a 700MHz DSP and can used for a many applications, requiring Embedded DSP Processing
Slides at OpenStack Summit 2017 Sydney
Session Info and Video: https://www.openstack.org/videos/sydney-2017/100gbps-openstack-for-providing-high-performance-nfv
Dev Dives: Train smarter, not harder – active learning and UiPath LLMs for do...UiPathCommunity
💥 Speed, accuracy, and scaling – discover the superpowers of GenAI in action with UiPath Document Understanding and Communications Mining™:
See how to accelerate model training and optimize model performance with active learning
Learn about the latest enhancements to out-of-the-box document processing – with little to no training required
Get an exclusive demo of the new family of UiPath LLMs – GenAI models specialized for processing different types of documents and messages
This is a hands-on session specifically designed for automation developers and AI enthusiasts seeking to enhance their knowledge in leveraging the latest intelligent document processing capabilities offered by UiPath.
Speakers:
👨🏫 Andras Palfi, Senior Product Manager, UiPath
👩🏫 Lenka Dulovicova, Product Program Manager, UiPath
UiPath Test Automation using UiPath Test Suite series, part 3DianaGray10
Welcome to UiPath Test Automation using UiPath Test Suite series part 3. In this session, we will cover desktop automation along with UI automation.
Topics covered:
UI automation Introduction,
UI automation Sample
Desktop automation flow
Pradeep Chinnala, Senior Consultant Automation Developer @WonderBotz and UiPath MVP
Deepak Rai, Automation Practice Lead, Boundaryless Group and UiPath MVP
Key Trends Shaping the Future of Infrastructure.pdfCheryl Hung
Keynote at DIGIT West Expo, Glasgow on 29 May 2024.
Cheryl Hung, ochery.com
Sr Director, Infrastructure Ecosystem, Arm.
The key trends across hardware, cloud and open-source; exploring how these areas are likely to mature and develop over the short and long-term, and then considering how organisations can position themselves to adapt and thrive.
Software Delivery At the Speed of AI: Inflectra Invests In AI-Powered QualityInflectra
In this insightful webinar, Inflectra explores how artificial intelligence (AI) is transforming software development and testing. Discover how AI-powered tools are revolutionizing every stage of the software development lifecycle (SDLC), from design and prototyping to testing, deployment, and monitoring.
Learn about:
• The Future of Testing: How AI is shifting testing towards verification, analysis, and higher-level skills, while reducing repetitive tasks.
• Test Automation: How AI-powered test case generation, optimization, and self-healing tests are making testing more efficient and effective.
• Visual Testing: Explore the emerging capabilities of AI in visual testing and how it's set to revolutionize UI verification.
• Inflectra's AI Solutions: See demonstrations of Inflectra's cutting-edge AI tools like the ChatGPT plugin and Azure Open AI platform, designed to streamline your testing process.
Whether you're a developer, tester, or QA professional, this webinar will give you valuable insights into how AI is shaping the future of software delivery.
Encryption in Microsoft 365 - ExpertsLive Netherlands 2024Albert Hoitingh
In this session I delve into the encryption technology used in Microsoft 365 and Microsoft Purview. Including the concepts of Customer Key and Double Key Encryption.
Connector Corner: Automate dynamic content and events by pushing a buttonDianaGray10
Here is something new! In our next Connector Corner webinar, we will demonstrate how you can use a single workflow to:
Create a campaign using Mailchimp with merge tags/fields
Send an interactive Slack channel message (using buttons)
Have the message received by managers and peers along with a test email for review
But there’s more:
In a second workflow supporting the same use case, you’ll see:
Your campaign sent to target colleagues for approval
If the “Approve” button is clicked, a Jira/Zendesk ticket is created for the marketing design team
But—if the “Reject” button is pushed, colleagues will be alerted via Slack message
Join us to learn more about this new, human-in-the-loop capability, brought to you by Integration Service connectors.
And...
Speakers:
Akshay Agnihotri, Product Manager
Charlie Greenberg, Host
Essentials of Automations: Optimizing FME Workflows with ParametersSafe Software
Are you looking to streamline your workflows and boost your projects’ efficiency? Do you find yourself searching for ways to add flexibility and control over your FME workflows? If so, you’re in the right place.
Join us for an insightful dive into the world of FME parameters, a critical element in optimizing workflow efficiency. This webinar marks the beginning of our three-part “Essentials of Automation” series. This first webinar is designed to equip you with the knowledge and skills to utilize parameters effectively: enhancing the flexibility, maintainability, and user control of your FME projects.
Here’s what you’ll gain:
- Essentials of FME Parameters: Understand the pivotal role of parameters, including Reader/Writer, Transformer, User, and FME Flow categories. Discover how they are the key to unlocking automation and optimization within your workflows.
- Practical Applications in FME Form: Delve into key user parameter types including choice, connections, and file URLs. Allow users to control how a workflow runs, making your workflows more reusable. Learn to import values and deliver the best user experience for your workflows while enhancing accuracy.
- Optimization Strategies in FME Flow: Explore the creation and strategic deployment of parameters in FME Flow, including the use of deployment and geometry parameters, to maximize workflow efficiency.
- Pro Tips for Success: Gain insights on parameterizing connections and leveraging new features like Conditional Visibility for clarity and simplicity.
We’ll wrap up with a glimpse into future webinars, followed by a Q&A session to address your specific questions surrounding this topic.
Don’t miss this opportunity to elevate your FME expertise and drive your projects to new heights of efficiency.
GraphRAG is All You need? LLM & Knowledge GraphGuy Korland
Guy Korland, CEO and Co-founder of FalkorDB, will review two articles on the integration of language models with knowledge graphs.
1. Unifying Large Language Models and Knowledge Graphs: A Roadmap.
https://arxiv.org/abs/2306.08302
2. Microsoft Research's GraphRAG paper and a review paper on various uses of knowledge graphs:
https://www.microsoft.com/en-us/research/blog/graphrag-unlocking-llm-discovery-on-narrative-private-data/
Generating a custom Ruby SDK for your web service or Rails API using Smithyg2nightmarescribd
Have you ever wanted a Ruby client API to communicate with your web service? Smithy is a protocol-agnostic language for defining services and SDKs. Smithy Ruby is an implementation of Smithy that generates a Ruby SDK using a Smithy model. In this talk, we will explore Smithy and Smithy Ruby to learn how to generate custom feature-rich SDKs that can communicate with any web service, such as a Rails JSON API.
Securing your Kubernetes cluster_ a step-by-step guide to success !KatiaHIMEUR1
Today, after several years of existence, an extremely active community and an ultra-dynamic ecosystem, Kubernetes has established itself as the de facto standard in container orchestration. Thanks to a wide range of managed services, it has never been so easy to set up a ready-to-use Kubernetes cluster.
However, this ease of use means that the subject of security in Kubernetes is often left for later, or even neglected. This exposes companies to significant risks.
In this talk, I'll show you step-by-step how to secure your Kubernetes cluster for greater peace of mind and reliability.
DevOps and Testing slides at DASA ConnectKari Kakkonen
My and Rik Marselis slides at 30.5.2024 DASA Connect conference. We discuss about what is testing, then what is agile testing and finally what is Testing in DevOps. Finally we had lovely workshop with the participants trying to find out different ways to think about quality and testing in different parts of the DevOps infinity loop.
AI for Every Business: Unlocking Your Product's Universal Potential by VP of ...
FPGA on the Cloud
1. FPGAs on The Cloud
Ioannis Tsagatakis
Ioannis Stefanis
Msc in Informatics & Multimedia
Department of Informatics Engineering TEI of Crete
Embedded Systems
3. 3
Massive Parallelism
● GPU
– SIMD
– Instruction Set
– Fixed Word Sizes
– Simple control logic
● FPGA
– MIMD
– No instruction set
– Any data width
– Complex control logic (FSMs)
4. 4
AWS F1 FPGA Instances
● Cloud based FPGA
– No need to buy hardware
● Cloud based IDE
– Ready to used AMI
– HDL: Verilog, VHDL
– SDAccel: C/C++, OpenCL
– AFI tools
● Marketplace
– A new market for Ips
– Secure encrypted AFIs
● f1.2xlarge
– 1 VU9P UltraScale+
● 2.5M logic elements
● 6,800 DSP
– 8 vCPU Cores
– 122GB RAM
– PCIe X16
– 1.6$ per hour
● f1.16xlarge
– 8 FPGA/64 CPUs
● Run simulation design on C4
to save money
12. 12
Creating the Amazon FPGA Image
● Created by an amazon
service
● Secured stored and
encrypted
● Developers have no
access to RTL IP
● The distributable
awsxclbin contains
only the AFI id
15. 15
OpenCL vs Cuda
● Cuda
– SIMD
– Easier programming
model
– Restricted memory
access patterns
– Faster development
– Vendor lock
– Easy deployment
● F1 FPGA
– MIMD
– More complexity
– Harder programming
– Deep pipelining
– Slow development
– Vendor lock
– Cloud deployment
16. 16
Smith–Waterman algorithm (sw_emu)
------FPGA Accelerator Summary --------
Number of SmithWaterman instances on FPGA:16
Total processing elements:512
Length of reference string:256
Length of read(query) string:128
Read-Ref pair block size(HOST to FPGA):1024
Verify Mode is:0
---------------------------------------
Generating read-ref samples
Processing 16384 Samples
HW Block Size: 16384
Total Number of blocks: 1
INFO: [smithwaterman.cpp:654] TIME: [Wed Feb 21 22:37:07 2018] nruns = 1
INFO: [smithwaterman.cpp:655] TIME: [Wed Feb 21 22:37:07 2018] total [ms] = 43326.373
INFO: [smithwaterman.cpp:656] TIME: [Wed Feb 21 22:37:07 2018] Host write [ms] = 0.768
INFO: [smithwaterman.cpp:657] TIME: [Wed Feb 21 22:37:07 2018] Krnl exec [ms] = 43317.977
INFO: [smithwaterman.cpp:658] TIME: [Wed Feb 21 22:37:07 2018] Host read [ms] = 1.029
GCups(based on kernel execution time):0.0115426
GCups(based on total execution time):0.0115403
INFO: [smithwaterman.cpp:679] TIME: [Wed Feb 21 22:37:07 2018] Host2Device rate [mbps] = 15616.602
INFO: [smithwaterman.cpp:691] TIME: [Wed Feb 21 22:37:07 2018] Device2Host rate [mbps] = 1457.154
INFO: [main.cpp:172] TIME: [Wed Feb 21 22:37:07 2018] finished
~/aws-fpga/SDAccel/examples/xilinx/acceleration/smithwaterman
17. 17
Smith–Waterman algorithm (wh_emu)
~/aws-fpga/SDAccel/examples/xilinx/acceleration/smithwaterman
xsimk
Generating read-ref samples
Processing 16384 Samples
HW Block Size: 16384
Total Number of blocks: 1
INFO: [SDx-EM 22] [Wall clock time: 23:05, Emulation time: 0.275298 ms] Data transfer between kernel(s) and
global memory(s)
BANK0 RD = 64.316 KB WR = 7.875 KB
BANK1 RD = 0.000 KB WR = 0.000 KB
BANK2 RD = 0.000 KB WR = 0.000 KB
BANK3 RD = 0.000 KB WR = 0.000 KB
…. after many hours …
INFO: [SDx-EM 22] [Wall clock time: 00:27, Emulation time: 4.77014 ms] Data transfer between kernel(s) and
global memory(s)
BANK0 RD = 1110.004 KB WR = 138.562 KB
BANK1 RD = 0.000 KB WR = 0.000 KB
BANK2 RD = 0.000 KB WR = 0.000 KB
BANK3 RD = 0.000 KB WR = 0.000 KB
….
18. 18
Building Times
For the helloworld example
INFO: [XOCC 60-629] Linking for hardware target
INFO: [XOCC 60-895] Target platform: /home/centos/src/project_data/aws-
fpga/SDAccel/aws_platform/xilinx_aws-vu9p-f1_4ddr-xpr-2pr_4_0/xilinx_aws-vu9p-f1_4ddr-xpr-2pr_4_0.xpfm
INFO: [XOCC 60-423] Target device: xilinx:aws-vu9p-f1:4ddr-xpr-2pr:4.0
INFO: [XOCC 60-251] Hardware accelerator integration...
Creating Vivado project and starting FPGA synthesis.
................................................................................................................................
Finished 1st of 5 tasks (FPGA synthesis). Elapsed time: 00h 34m 54s.
.....
Finished 2nd of 5 tasks (FPGA logic optimization). Elapsed time: 00h 05m 37s.
...............................
Finished 3rd of 5 tasks (FPGA logic placement). Elapsed time: 00h 43m 50s.
................................
Finished 4th of 5 tasks (FPGA routing). Elapsed time: 00h 56m 33s.
INFO: [XOCC 60-586] Created xclbin/vector_addition.hw.xilinx_aws-vu9p-f1_4ddr-xpr-2pr_4_0.xclbin
INFO: [XOCC 60-791] Total elapsed time: 2h 31m 50s
And then you have to build the AFI ...
Give up building the
19. 19
Building Times
For the helloworld example
INFO: [XOCC 60-629] Linking for hardware target
INFO: [XOCC 60-895] Target platform: /home/centos/src/project_data/aws-
fpga/SDAccel/aws_platform/xilinx_aws-vu9p-f1_4ddr-xpr-2pr_4_0/xilinx_aws-vu9p-f1_4ddr-xpr-2pr_4_0.xpfm
INFO: [XOCC 60-423] Target device: xilinx:aws-vu9p-f1:4ddr-xpr-2pr:4.0
INFO: [XOCC 60-251] Hardware accelerator integration...
Creating Vivado project and starting FPGA synthesis.
................................................................................................................................
Finished 1st of 5 tasks (FPGA synthesis). Elapsed time: 00h 34m 54s.
.....
Finished 2nd of 5 tasks (FPGA logic optimization). Elapsed time: 00h 05m 37s.
...............................
Finished 3rd of 5 tasks (FPGA logic placement). Elapsed time: 00h 43m 50s.
................................
Finished 4th of 5 tasks (FPGA routing). Elapsed time: 00h 56m 33s.
INFO: [XOCC 60-586] Created xclbin/vector_addition.hw.xilinx_aws-vu9p-f1_4ddr-xpr-2pr_4_0.xclbin
INFO: [XOCC 60-791] Total elapsed time: 2h 31m 50s
And then you have to build the AFI ...
Good luck
building the Smith-Waterman
Example
20. 20
Conclusions
● Moderate* costs
● Easy setup with minor issues
● Cloud based IDE (rdp), or ssh
● Slow development
● Harder to learn than CUDA
● Good documentation and examples
● Market place is still small but
promising
●
No 3rd
party examples
Moderate cost ;
$3,500 Xilinx Virtex-7 FPGA VC707 Evaluation
Kit
$13,000 Xilinx Virtex-7 FPGA VC7222 Char. Kit
$1.500 Intel Xeon Phi 7120P Coprocessor
$1.400 Nvidia GeForce Titan X Pascal
22. 22
FPGA vs GPU Accelerating Compute-Intensive Applications with GPUs and
FPGAs
S. Che, J. Li, J. W. Sheaffer, K. Skadron and J. Lach,
2008 Symposium on Application Specific Processors
CUDA and the GeForce 8800 GTX GPU
VHDL and the Xilinx Virtex-II Pro FPGA