This document summarizes common issues encountered when developing FPGA projects. It introduces FPGAs, the development process, and applications. Key issues discussed include timing violations from negative slack, hardware configuration errors affecting ADCs, DDR3 interface problems from hardware design faults like improper impedance matching, and excessive resource usage from unnecessary registers. Solutions involve optimizing code and hardware design, as well as adjusting compiler options.

1. FPGA 개발하면서 겪은 삽질에 대한 총 정리
NOV. 4, 2017
Hanwook Kim

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Contents
I. Introduction
1) What is FPGA?
2) Development process
3) Difference between FPGA and MCU/DSP
4) Application of FPGA
II. Troubles of developing FPGA
1) Case I : Timing violation due to negative slack
2) Case II : H/W configuration and A/D converter debugging
3) Case III : DDR3 I/F problem due to h/w design fault
4) Case IV : FPGA resource problem

3. Part I. Introduction

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I. Introduction
 1) What is FPGA?
 Definition : Field Programmable Gate Array
→ Contain logical-gate (AND, OR, XOR, NOT… etc.), Flip-flop, and internal wire
→ “Programmable” during operating time and “Reconfigurable”
→ Cost-efficient, and flexible device
[Configuration of FPGA] [CMOS gate array of FPGA]

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I. Introduction
 1) What is FPGA?
[ALTERA FPGA : Stratix IV] [Xilinx FPGA : KINTEX]

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I. Introduction
 1) What is FPGA?
 Main vendor : ALTERA, Xilinx, ACTEL, Mircrosemi, Lettice semiconductor …
 IDE(Integrated Development Environment) : ATLERA Quartus, Xilinx ISE, Vivado,
ACTEL Libero …
 HDL (Hardware Description Language) : VHDL, Verilog, System Verlilog … etc
→ Compatible each other
[ALTERA Quartus II] [Xilinx Vivado]

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I. Introduction
 2) Development process
[FPGA Development Process]

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I. Introduction
 2) Development process
[HDL Synthesis]

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I. Introduction
 3) Difference between FPGA and DSP/MCU
[Difference between parallel process and sequential process]

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I. Introduction
 4) Application of FPGA
 Space, Defense/Military, Automobile, Communication, Cloud, Test and measurement,
Industrial, Medical… etc.
https://www.xilinx.com/applications/megatrends.html

11. Part II. Trouble of developing FPGA

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II. Trouble of developing FPGA
 1) Timing violation due to negative slack
 Slack : (Required clock period) – (Actual clock period)
 Positive slack : The timing requirements are met
 Negative slack : The timing requirements are not met
[Timing slack]

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II. Trouble of developing FPGA
 1) Timing violation due to negative slack
 As the master clock (60MHz) has the negative slack, the reset of 12bit free-
running counter causes some trouble
→ Negative slack is because of heavy encryption logic supported by supervisor corp
always @(posedge i_clk, negedge i_rstn) begin
if (!i_rstn) begin
cnt <= 12’d0;
end
else begin
cnt <= cnt + 1’d1;
end
end
[Free running counter logic]

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II. Trouble of developing FPGA
 2) H/W configuration and A/D converter debugging
 H/W configuration error causes a malfunction A/D converter

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II. Trouble of developing FPGA
 3) DDR3 I/F problem due to h/w design fault
[DDR3 SDRAM architecture and memory topology]

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II. Trouble of developing FPGA
 3) DDR3 I/F problem due to h/w design fault
[DDR3 SDRAM controller block diagram]

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II. Trouble of developing FPGA
 3) DDR3 I/F problem due to h/w design fault
[DDR3 SDRAM Write/Read process] [DDR3 SDRAM controller main FSM]

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II. Trouble of developing FPGA
 3) DDR3 I/F problem due to h/w design fault
 The clock frequency of DDR3 SDRAM is very high (1066 MHz)
→ Deliberate h/w design is required for DDR3 SDRAM control
: Impedance matching, PCB pattern routing, PCB pattern length and width… etc
→ Some H/W design fault causes DDR3 SRRAM control fault
[DDR3 SDRAM impedance matching]

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II. Trouble of developing FPGA
 4) FPGA logic resource
 Unnecessary using of register (flip-flop) causes an excessive resource of FPGA
→ Commonly, FPGA vendors recommend that logic is used up to 70%
→ Our logic occupied 85% of FPGA resource
→ The operating of logic varied frequently when the logic is ported on FPGA
→ Solution : Code optimization, and compiler option