CTU: EE 395 – Electronics 2: Lab 1: BJT Circuits 1 Colorado Technical University EE 395 – Electronics 2 Lab 1: BJT Circuits May 2010 Loren Schwappach, Taylor DeIaco, Victor Arosemena ABSTRACT: This lab report was completed as a course requirement to obtain full course credit in EE395, Electronics 2 atColorado Technical University. This lab report examines two BJT circuits (NPN common emitter, and NPN common emitter with anemitter resister and voltage divider bias) and how they operate. The objective of this lab is to analyze, simulate, experiment, anddocument the characteristics of the NPN transistor. Hand calculations are developed using the properties of the BJT (with B testedprior to circuit construction and then verified using P-Spice schematic calculations to determine the viability of design prior to thephysical build of the design. P-Spice simulation results and hand calculations are then verified by physically modeling the design on abread board and taking measurements for observation. If you have any questions or concerns in regards to this laboratory assignment, this laboratory report, the process used indesigning the indicated circuitry, or the final conclusions and recommendations derived, please send an email toLSchwappach@yahoo.com. All computer drawn figures and pictures used in this report are of original and authentic content. Theauthors authorize the use of any and all content included in this report for academic use. of charges injected from a high-concentration emitter into the base where they are minority carriers that diffuse toward the I. INTRODUCTION collector, and so BJTs are classified as minority-carrier devices. T HE NPN Bipolar Junction Transistor is an active circuit device with several uses such as signal The proportion of electrons able to cross the base and reach the collector is a measure of the BJT efficiency. Theamplification. The DC biasing (B value of the transistor) isused to find the linear operating region of the device and its heavy doping of the emitter region and light doping of theperformance distinctiveness. The BJT transistor structure base region cause many more electrons to be injected from thecontains three regions. The collector, base, and emitter. The emitter into the base than holes to be injected from the baseobjective of this lab is to gain an understanding of how a BJT into the emitter. The common-emitter current gain istransistor operates, and construct a circuit which correctly represented by β; it is approximately the ratio of the DCimplements its operations (within +-10%). collector current to the DC base current in forward-active region. It is typically greater than 100 for small-signal transistors but can be smaller in transistors designed for high- II. OBJECTIVES power applications. Another important parameter is the common-base current gain, α. The common-base current gain The objective of this lab is to gain an understanding is approximately the gain of current from emitter to collectorof the physical structure, operation, and characteristics of the in the forward-active region. This ratio usually has a valuebipolar junction transistors (BJT). In particular what the close to unity; between 0.98 and 0.998. Alpha and beta aredifferences are between the analysis, simulation and actual more precisely related by the following identities (NPNexperiment results. And to recognize the three modes of transistor):operation: saturation, active and cutoff. The goal of this lab is to become familiar and understand how a BJT operates. = III. DIODE THEORY “A bipolar (junction) transistor (BJT) is a three- β= terminal electronic device constructed of doped semiconductormaterial and may be used in amplifying or switching β=applications. Bipolar transistors are so named because their + 1operation involves both electrons and holes. Charge flow in aBJT is due to bidirectional diffusion of charge carriers across a Bipolar transistors have five distinct regions ofjunction between two regions of different charge operation, defined mostly by applied bias; four of theseconcentrations. This mode of operation is contrasted with operations are described below.unipolar transistors, such as field-effect transistors, in whichonly one carrier type is involved in charge flow due to drift. Forward-active (or simply, active): The base–emitterBy design, most of the BJT collector current is due to the flow junction is forward biased and the base–collector junction is
CTU: EE 395 – Electronics 2: Lab 1: BJT Circuits 2reverse biased. Most bipolar transistors are designed to afford initial failures on the first day of testing (error margins the greatest common-emitter current gain, β, in forward-active 10%) due to bias instability. So the transistor was checkedmode. If this is the case, the collector–emitter current is and found to be approx 150 at intended Ic. This B of 150approximately proportional to the base current, but many was then used to redesign hand calculations, PSpicetimes larger, for small base current variations. models and provided accurate circuit measurements. Reverse-active (or inverse-active or inverted): Byreversing the biasing conditions of the forward-active region, abipolar transistor goes into reverse-active mode. In this mode,the emitter and collector regions switch roles. Because mostBJTs are designed to maximize current gain in forward-activemode, the β in inverted mode is several (2–3 for the ordinarygermanium transistor) times smaller. This transistor mode isseldom used, usually being considered only for failsafeconditions and some types of bipolar logic. The reverse biasbreakdown voltage to the base may be an order of magnitudelower in this region. Saturation: With both junctions forward-biased, aBJT is in saturation mode and facilitates high currentconduction from the emitter to the collector. This modecorresponds to a logical on, or a closed switch. Cutoff: In cutoff, biasing conditions opposite ofsaturation (both junctions reverse biased) are present. There isvery little current flow, which corresponds to a logical off,or an open switch.” Figure 2: Circuit 2: Common-emitter circuit with an NPN transistor, emitter resister and voltage divider bias. B was In this lab our group designed and analyzed two initially assumed to be 120 but after initial failures duringspecific circuits using the 2N3904 NPN BJT. Our first circuit the first day of testing (error margins closer but still was a simple Common-emitter circuit with an NPN transistor 10%). So the transistor was checked and found to be(figure 1), our second circuit used a Common-emitter circuit approx 150 at the intended Ic. This B of 150 was then usedusing an NPN transistor with an emitter resister and voltage to redesign hand calculations, PSpice models and provideddivider bias, which should allow for greater bias stability accurate circuit measurements.(figure 2). IV. DESIGN APPROACHES/TRADE-OFFS The performance of this lab will depend on how well the circuit is developed. If the circuit is developed correctly the results showed be similar to hand calculation results. PSpice will also be used to provide a rough estimate of what should be expected in circuit measurements however the PSpice model transistor B was found to be approx 134 which is not the actual B of 150, so the PSpice simulations should have a much larger error margin than the expected hand calculations. The performance of the lab also depends on how well the equipment is calibrated and accurate the components tolerance is. This is not a very cost effective lab except for the development and time it took to construct the lab components. But to save money for a lab project, whether it’s the testing or developing phase of a new design, depending on what the schematic is, a circuit can be reduced, if done correctly. Figure 1: Circuit 1: Common-emitter circuit with NPN transistor. B was initially assumed to be 100 but after
CTU: EE 395 – Electronics 2: Lab 1: BJT Circuits 3 V. HAND CALCULATIONS The scanned hand calculations used for this lab canbe found below. After the initial failure on our first day ofcircuit testing our group decided to try using a 2N3903 NPNBJT in place of the 2N3904 transistor. The 2N3903 producedgood results with 10% error, and B was determined to beapprox 82. With this new data and confidence our groupdecided to recheck the 2N3904 transistor and find a betterapprox for B at our intended Ic. This B was measured to beapprox 149. Thus hand calculations were again performedusing the correct B values. These correct hand calculationsare below and were able to produce results with an errormargin of less than 10%. Figure 4: Circuit 1, using 2N3904, B approx 150, Vbe = .69. Vcc = 5V, Rc = 2.5k, Ic designed at 1mA, Vceq designed at 2.5V, Vbb = 1.7V, and Rb required to be 149k to provide the correct bias and Ib of 6.7uA. Measured values were within 10% of hand calculations.Figure 3: Circuit 1, using 2N3903, B approx 82, Vbe = .69.Vcc = 5V, Rc = 2.5k, Ic designed at 1mA, Vceq designed at 2.5V, Vbb = 1.7V, and Rb required to be 82k to providethe correct bias and Ib of 12.2uA. Measured values were within 10% of hand calculations. Figure 5: Circuit 2, using 2N3903, B approx 82, Vbe = .69. Vcc = 5V, Rc = 1k, Re = 510, Vceq designed at 3V, Ic determined to be 1.3mA, R1 determined to be 10K and R2 required to be 4k to provide the bias stability and Ib of 16uA. Measured values were within 10% of hand calculations.
CTU: EE 395 – Electronics 2: Lab 1: BJT Circuits 4 Figure 7: Circuit 1: PSpice Voltage Results of 3904 NPN. Notice B = 134 not 150 (actual) which accounts for a larger error margin 10% than expected. Figure 6: Circuit 2, using 2N3904, B approx 149, Vbe =.69. Vcc = 5V, Rc = 1k, Re = 510, Vceq designed at 3V, Icdetermined to be 1.3mA, R1 determined to be 20K and R2 required to be 8k to provide the bias stability and Ib of 8.7uA. Measured values were within 10% of hand calculations. VI. CIRCUIT SCHEMATICS The final circuit schematics below were built inPSpice and allowed our team to analyze the circuit digitallybefore performing the physical build. However, since the Bvalue of the transistor used was approx 150 instead of thePSpice B of 134 the actual values were much closer to thehand calculations than PSpice calculations. If the PSpicemodel B was adjusted accordingly the resulting PSpicecalculations would have been much more accurate. Figure 8: Circuit 1: PSpice Current Results of 3904 NPN. Notice B = 134 not 150 (actual) which accounts for a larger error margin 10% than expected.
CTU: EE 395 – Electronics 2: Lab 1: BJT Circuits 5 Figure 9: Circuit 1: PSpice Power Results of 3904 NPN.Notice B = 134 not 150 (actual) which accounts for a larger error margin 10% than expected. Figure 11: Circuit 2: PSpice Circuit Results of 3904 NPN. Notice B = 134 not 150 (actual) which accounts for a larger error margin 10% than expected. Figure 10: Circuit 2: PSpice Power Results of 3904 NPN.Notice B = 134 not 150 (actual) which accounts for a larger error margin 10% than expected.
CTU: EE 395 – Electronics 2: Lab 1: BJT Circuits 6 VIII. EXPERIMENTAL DATA The following table illustrates the measurements taken at each stage of the lab. Circuit 1: Common Emitter NPN (2N3904) B = 150 % Error (rounded up) Hand Calc Pspice Calc Measured Component Min assumed 1% (B=150) (B=134) (B=150) (Hand vs Measured) Rc 2.5k 2.5k 2.45k 2% Rb 149k 149k 149k 1% Vcc 5V 5V 4.99V 1% Vbb 1.7V 1.7V 1.69V 1% Vrb 1V 1.04V 1.02V 2% Vrc 2.5V 2.35 2.51V 1% Vbe 0.69 .66V .69V 1% Vc 2.5V 2.65 2.49V 1% Ve 0V 0V 0V 1% Vceq 2.5V 2.65V 2.49V 1% Vceq(cut) 5V 5V 4.99V 1% Ib 6.7uA 6.957uA 6.9uA 3% Ic 1mA 937.9uA 1.03mA 3% Ic (sat) 2mA 2mA 2mA 1% B 150 134 149.3 1% Table 1: Circuit 1: Comparison of Hand Calculated, PSpice, and Measured Values and Percentage of Error (Hand Calculated vs Actual). Circuit 2: Common Emitter NPN (2N3904) B = 150Figure 11: Circuit 2: PSpice Circuit Results of 3904 NPN. w/ Re and Voltage Divider Bias (Much more stable)Notice B = 134 not 150 (actual) which accounts for a larger % Error (rounded up) Hand Calc Pspice Calc Measured error margin 10% than expected. Component (B=150) (B=134) (B=150) Min assumed 1% (Hand vs Measured) VII. COMPONENT LIST Rc 1k 1k 1k 1% Re 510 510 510 1% The following is a list of components that were used in R1 20k 20k 20k 1%constructing the BJT switch / inverter. Component values R2 8k 8k 8K 1%were selected by the professor. Vcc 5V 5V 4.99V 1% Vb 1.36V 1.37V 1.35V 1% A digital multimeter for measuring circuit Vr1 3.65V 3.63V 3.63V 1% voltages, resistor resistances, and capacitor Vr2 1.35V 1.37V 1.35V 1% Vbe .69V .67V .69V 1% capacitance. Vc 3.7V 3.64V 3.7V 1% A power supply capable of delivering a constant Ve .67V .7V .66V 3% Vcc = 5V. Vrc 1.3V 1.36V 1.3V 1% A power supply capable of delivering a constant Vceq 3V 2.94V 3.04V 1% Vcc = 1.7V (for circuit 1). Vceq(cut) 5V 5V 4.99V 1% A 2N3904 Transistor, V(BE) = .69V, Beta (B) = Ic 1.3mA 1.36mA 1.28mA 3% 150 at Ic = approx 1mA. Ie 1.31mA 1.37mA 1.28mA 3% Resisters for 2N3904 designs of values approx Ib 8.7uA 9uA 8.5uA 3% 2.5k, 149k, 1k, 510, 20k, 8k. Ir1 183uA 181uA 179uA 3% Ir2 169uA 172uA 170uA 1% Bread board with wires. B 151 134 151 1% NOTE: Resistors can normally provide around +/- Ic(Sat) 3.28mA 3.28mA 3.28mA 1% 5%-25% difference between actual and designed Table 2: Circuit 2: Comparison of Hand Calculated, values while Capacitors generally provide around PSpice, and Measured Values and Percentage of Error 20%-50% difference between actual and designed (Hand Calculated vs Actual). Notice that although PSpice values. You can add resisters in series as (R1+R2) B = 134, values are much closer to actual than before, this to closer approximate required resistance values is due to the increased stability offered by adding Re and and you can add Capacitors in parallel as (C1+C2) voltage divider bias. to closely approximate required capacitance.
CTU: EE 395 – Electronics 2: Lab 1: BJT Circuits 7 IX. ANALYSIS/DATA COMPARISON The analysis/PSpice/Experimental data results wereall accurate, but the results differed between the three. Thereasons that the results were different is because theexperimental results have equipment calibrations, componenttolerances, and actual measures values from the components.The PSpice were less accurate than hand calculation becausethe PSpice NPN was modeled at B = 134. All three resultswere not in total agreement however, the results were close toeach other, and became increasingly closer using circuit 2’sincreased bias stability. X. CONCLUSIONS The discrepancies between the actual results, handcalculated and simulated result is that they were all extremelyclose (10%) from the P-Spice results, however these resultscould differ depending upon the error provided by the passiveand active components, factors such as component tolerances,equipment calibrations and measurements fluctuations by theobserver can contribute to results being slightly off from theP-Spice calculations. It is always good to start with P-Spice tounderstand what is happening prior to build, and even moreimportant to know the characteristics (B value) of thetransistor. In conclusion, this lab was a great demonstration onthe powerful features of BJTs and their use in electronics andthe importance of choosing a stable biased circuit (circuit 2) vsa less stable circuit (circuit 1). XI. ATTACHMENTS All figures above follow. REFERENCES D. A. Neamen, “Microelectronics: circuit analysis and design - 3rd ed.” McGraw-Hill, New York, NY, 2007. pp. 1-107.