ECG compression in vlsi

TECHNICAL SEMINAR
Under the guidance of:
THEJASWINI B M
Assistant Professor
Dept. of ECE
BIT, Bangalore
Presented by:
MOHAN G
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VLSI Desgin & Embedded Systems
BIT, Bangalore
VLSI Implementation of Lossless ECG
Compression Algorithm for Low Power Devices
BANGALORE INSTITUTE OF TECHNOLOGY
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
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VLSI Design & Embedded Systems

CONTENT:
Abstract
Introduction
Literature Survey
Methodology
Results
Conclusion
 Future work
References
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Abstract
This paper presents a VLSI implementation of an efficient lossless compression scheme for
electrocardiogram (ECG) data encoding to save storage space and reduce transmission time.As
compression algorithm is able to save storage space and reduce transmission time, this opportunity
has been seized by implementing memory-less design while working at a high clock speed in
VLSI.
 ECG compression algorithm comprises two parts:
 An Adaptive linear prediction technique and
 content-adaptive Golomb Rice code`
To improve the performance, the proposed VLSI design uses bit shifting operations as a
replacement for the different arithmetic operations.
VLSI implementation has been applied to the MITBIH arrhythmia database which is able to
achieve a lossless bit compression rate of 2.77.
Moreover, VLSI architecture contains 3.1 K gate count and core of the chip consumes 27.2 nW of
power while working at 1 KHz frequency. The core area is 0.05 mm2 in 90 nm CMOS process.
VLSI Deign & Embedded Systems

Introduction
In recent years, Cardiovascular disease (CVD) has been the major cause of death worldwide and is
reported as roughly 31% of all global deaths. To diagnose this disease and many others, the
electrocardiogram (ECG) signal is used.
In a 24-hour ECG signal monitoring system, the monitoring system will be producing a huge
amount of data. To understand the amount of data generated during ECG monitoring process,
following two different frequencies can be taken as examples.
 So, to store this huge data, a solution is required to reduce the data of ECG signal, hence ECG
compression is performed in such case to save storage space.
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Recently, there has been an increase in the usage of wearable devices in health monitoring. These
devices can perform many tasks, such as:
 heart rate monitoring,
 walking or running steps counting etc.
Battery life is one of the important factors while designing different sensors or chip modules which
leads to the need for developing low power hardware modules to be used in such devices.
Chen-et-al has presented a mixed signal VLSI design of ECG compression which includes a smart
analog-to-digital converter (ADC) and lossless ECG compression is performed on the basis of
trend forecasting and entropy coding. Although this design is intended for low power applications
yet its power consumption is quite high which makes such design unsuitable for current low power
devices.
Another VLSI implementation of ECG compression has been proposed by Zou-et-al, which uses
wavelet transform and Run-Length Encoding (RLE) but the working frequency of the design is
quite high which makes it unsuitable to be used in real-time ECG data compression.
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Sl.No Title Author Year of Publication Technology
1 A Power-Efficient Mixed-Signal Smart
ADC Design With Adaptive Resolution and
Variable Sampling Rate for Low-Power
Applications
Shih-Lun Chen 2017 0.18-μm CMOS process
with a total power
consumption of 78.8 μW
when operating at 1 kHz and
a total chip area of 850 × 850
μm 2 .
2
An Energy-Efficient Design for ECG
Recording and R-Peak Detection Based on
Wavelet Transform
Y. Zou 2015 design has been fabricated
under TSMC 65-nm CMOS
technology with area cost of
0.41 mm2.
3 A 30 μ W Analog Signal Processor ASIC for
Portable Biopotential Signal Monitoring
R. F. Yazicioglu 2010 ECG signal extraction with
high resolution, ECG
signal feature extraction,
adaptive sampling ADC for
the compression of ECG
signals
4 An Efficient ECG Lossless Compression
System for Embedded Platforms With
Telemedicine Applications
T.-H. Tsai and W.-T. Kuo 2018 The technique is the use of a
suitable packing format; this
enables the real-time
decoding process
Literature Survey
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Methodology

Generally, ECG data compression has two main processing parts :
 error prediction and
 data coding
The prediction error value, e(n), can be calculated as (1)
e(n) = x(n) – x
̂ (n) …… (1)
 where x
̂ (n) is the prediction value, and
 x(n) is the value of current sample data in ECG data at time n.
This prediction error value is utilized in Golomb code.
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ECG signal contains numerous regions with sharp amplitude variations, such as Q,R,S,P,
and T wave regions, as shown in Fig. 1, which may result in a higher prediction error during
prediction error estimation phase. An adaptive linear predictor technique is proposed to improve the
prediction error by keeping its value minimum.
Fig 1:
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Adaptive Linear Prediction:

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Previous four samples are used to estimate the prediction value, which has been shown in fig. 3. The value of
the four parameters i.e. ‘D1_2’, ‘D1_3’, ‘D2_3’, and ‘D3_4’ is calculated through the following equations:
D1_2 (n) = x (n-1) – x (n-2) (2)
D1_3 (n) = x (n-1) – x (n-3) (3)
D2_3 (n) = x (n-2) – x (n-3) (4)
D3_4 (n) = x (n-3) – x (n-4) (5)

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Taking the characteristics of the ECG signal into consideration, the simple differential predictors
with coefficients are used.
 Due to low complexity computation and good performance in estimating prediction value, the
following three differential predictors have been selected in algorithm development as shown in the
below equations
P1: x
̂ (n) = x (n-1) (6)
P2: x
̂ (n) = 2x (n-1) - x (n-2) (7)
P3: x
̂ (n) = 3x (n-1) - 3x (n-2) + x (n-3) (8).

Lossless Data Compression Technique:
 Entropy coding is the part of coding technique in data compression, in which frequently occurring patterns or
values are presented with few binary bits and rarely occurring ones are presented with many binary bits.
Content-Adaptive Golomb-Rice code:
 Golomb coding is a data compression scheme based upon entropy encoding and is optimal for alphabets with
a geometric distribution. The Golomb-Rice code comprises two parts:
 Quotient and
 Remainder,
 which are represented by :
 where k represents the number of bits for the remainder, and M[n] is a positive integer. M[n] is achieved
by transformation of a prediction error, which may be a negative value, into a positive number. This
function can be described by:
 where e is the prediction error value.
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In algorithm development, a window is used to calculate the distribution of prediction errors .
The distribution of prediction error of each window is applied to determinate the k parameter. The
size of the window is determined using the QRS segment in the ECG signal.
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HARDWARE ARCHITECTURE & DATA FORMAT :
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 In the decoding process, to reconstruct the original signal, theencoded output stream contains
the first sample of ECG data of11-bits and the k parameter with 3-bits for each window and
prediction error which is encoded by Golomb-Rice code. The output bit stream is illustrated
in Fig. 5.

• HARDWARE IMPLEMENTATION:
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For the hardware implementation, Fig. 6 shows a block level diagram. Input data’s source can be
RAM, BRAM or text file and the input data has 11 bits per sample which are processed in
Adaptive Linear Prediction (ALP) module in the first phase.
 After performing the error prediction, Golomb Rice coding (GRC) is performed on the processed
data.
In the last stage, the packing is performed and data is sent as output where data becomes valid in
the form of a group.

Adaptive Linear Prediction & Error Prediction

 For ALP module, 11-bit input is being processed at every clock cycle. For the first four inputs,
linear prediction is performed differently as compared to other inputs as discussedin the
proposed original algorithm.
 A control unit is controlling the input data by generating control signals for the selection of
linear prediction unit as well as sending data from linear prediction units to error predictor.
 For error predictor, simple arithmetic is present to check whether the number is positive or
negative.

Architecture for Golomb Rice Coding:
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Input data is post-processed data of the error predictor module. Data is processed for one complete
window so there is a 40x13-bits register to save one window’s values.
When new window’s values are arriving then previous window’s values are processed to find the
value of U and V, where U and V represent quotient and remainder.
this module’s architecture can be divided into two parts; data controlling part and computation.
 In the computation part, operations have been divided into different clock cycles to reduce the
processing delay. Instead of using the built-in operators of division or power, bit shifting has been
used to perform the multiplication, power, mod and division operations.
A single counter is being used to control data reading and saving to reduce resources usage.
Moreover, sharing of the single counter for both controllers leads to less activity as compared to
using two counters which results in saving switching power.

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ARCHITECTURE FOR PACKGING MODULE:
 Packaging module includes two controllers which are responsible for data saving in a
temporary 26-bits register as well as sending 16-bits of output data when 16 or more than 16
bits have been stored in the temporary register.

VLSI design has been implemented using TSMC 90nm technology, Synopsys Design Compiler
and IC Compiler has been used for synthesis and layout respectively.
Power analysis for the proposed design has been performed using Switching Activity File (SAIF),
which was generated by simulating the data of one channel of MIT-BIH dataset for 297947
values, in Prime Time.
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RESULTS
The layout of the ECG compression chip

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 Table I shows the hardware implementation results summary for the low and high-speed design. As
the chip is intended to work for real-time processing, only the low-speed design has been processed
for layout purposes
For VLSI implementation, few state of the art methods have been compared with proposed
implementation technique. Table II shows a comparison of different parameters for different
implementation techniques.

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Conclusion & Future Work
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 This paper presents a low power VLSI implementation of thelossless ECG compression
algorithm.
 The proposed implementation has been tested for MIT-BIH arrhythmia database which
achieves the compression ratio of 2.77
 The design runs at 1 KHz for real-time data processing and core power consumption is only
27.2 nW which makes this design suitable for modern day low power applications.
 The design has a core area of 0.05 mm2 in 90 nm CMOS technology.
For future work, power consumption can be reduced for this design as 99.98% power
consumption is from leakage power.
The leakage power can be reduced by using clock gating and multi- threshold voltage cells

REFERENCES
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 “WHO | World Health Statistics 2013,” WHO, 2013.
 M. S. Alam and N. M. S. Rahim, “Compression of ECG signal based on its deviation from a
reference signal using discrete cosine transform,” 2008 Int. Conf. Electr. Comput. Eng., vol.
00, no. December 2008, pp. 20–22, 2008.
 S.-L. Chen et al., “A Power-Efficient Mixed-Signal Smart ADC Design With Adaptive
Resolution and Variable Sampling Rate for Low-Power Applications,” IEEE Sens. J., vol.
17, no. 11, pp. 3461– 3469, Jun. 2017.
 Y. Zou et al., “An energy-efficient design for ECG recording and R-peak detection based on
wavelet transform,” IEEE Trans. Circuits Syst. II Express Briefs, vol. 62, no. 2, pp. 119–
123, 2015.
 R. J. Ellis, B. Zhu, J. Koenig, J. F. Thayer, and Y. Wang, “A careful look at ECG sampling
frequency and R-peak interpolation on short- term measures of heart rate variability,”
Physiol. Meas., vol. 36, no. 9, pp. 1827–1852, 2015.

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 L. Hejjel and E. Roth, “What is the adequate sampling interval of the ECG signal for heart rate
variability analysis in the time domain?,” Physiol. Meas., vol. 25, no. 6, pp. 1405–1411, 2004.
 R. F. Yazicioglu, S. Kim, T. Torfs, H. Kim, and C. Van Hoof, “A 30 μw analog signal
processor ASIC for portable biopotential signal monitoring,” IEEE J. Solid-State Circuits, vol.
46, no. 1, pp. 209–223, 2011.
 T.-H. Tsai and W.-T. Kuo, “An Efficient ECG Lossless Compression System for Embedded
Platforms With Telemedicine Applications,” IEEE Access, vol. 6, pp. 42207–42215, 2018.
 W. D. Leon-Salas, “Encoding compressive sensing measurements with Golomb-Rice codes,”
Proc. - IEEE Int. Symp. Circuits Syst., vol.2015-July, pp. 2177–2180, 2015.
 C. J. Deepu, C.-H. Heng, and Y. Lian, “A Hybrid Data Compression Scheme for Power
Reduction in Wireless Sensors for IoT,” IEEE Trans. Biomed. Circuits Syst., vol. 11, no. 2, pp.
245–254, 2017.
 C. J. Deepu, X. Zhang, W. S. Liew, D. L. T. Wong, and Y. Lian, “An ECG-on-Chip with 535
nW/channel integrated lossless data compressor for wireless sensors,” IEEE J. Solid-State
Circuits, vol. 49, no. 11, pp. 2435–2448, 2014.

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 C.-I. Ieong, M. Li, M.-K. Law, P.-I. Mak, M. I. Vai, and R. P. Martins, “A 0.45 V 147–375 nW
ECG Compression Processor With Wavelet Shrinkage and Adaptive Temporal Decimation
Architectures,” IEEE TVLSI Syst., vol. 25, no. 4, Apr. 2017.
 S.-L. Chen and J.-G. Wang, “VLSI implementation of low-power cost-efficient lossless ECG
encoder design for wireless healthcare monitoring application,” Electron. Lett., vol. 49, no. 2, pp.
91–93, 2013.
 “ECG/ EKG.” [Online]. Available: https://glneurotech.com/FAQ/ecg
_ekg.html. [Accessed: 03-Jun-2019].
 C.-I. Ieong, M. Li, M.-K. Law, P.-I. Mak, M. I. Vai, and R. P. Martins, “A 0.45 V 147–375 nW
ECG Compression Processor With Wavelet Shrinkage and Adaptive Temporal Decimation
Architectures,” IEEE Trans. Very Large Scale Integr. Syst., vol. 25, no. 4, pp. 1307–1319, Apr.
2017.
 C. J. Deepu, X. Zhang, C. H. Heng, and Y. Lian, “A 3-Lead ECG-on-chip with QRS detection and
lossless compression for wireless sensors,” IEEE Trans. Circuits Syst. II Express Briefs, vol. 63,
no. 12, pp. 1151–1155, Dec. 2016.

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ECG compression in vlsi

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