This document summarizes the results of an ECE260B mini-project completed by Fanyu Yang and Nian Jiang. They designed an ALU that achieved a maximum frequency of 50MHz using a non-linear carry select adder and Baugh-Wooley multiplier. Through logic synthesis and physical implementation, they optimized the design to operate at 30MHz with a total power of 4.583mW and slack time of 0.548ns. The document describes the components and optimization steps taken at the RTL, logic synthesis, and physical implementation stages to achieve these results.

1. ECE260B Mini-Project1 Fanyu Yang (A53102865) & Nian Jiang (A53070866)
ECE260B Mini-Project1 Report
Submitted by: Fanyu Yang (A53102865, fay012@eng.ucsd.edu)
Nian Jiang (A53070866, nijiang@eng.ucsd.edu)
All files used for data collection is available at:/home/linux/ieng6/ee260b/nijiang/mp_1/mp_1_release
1. Maximum frequency reported by Encounter without negative slack:
50MHz (Period =20ns). But as the matric5 value of this frequency is not maximum among the
several frequency tried, this has not been chosen as the operating frequency as the final design.
The final operating frequency is chosen as 30MHz.
2.
Total Area of Standard Cells
(um^2)
Total Power (mw) Slack Time (ns)
Post-Placement 71823.960 4.682 0.099
Post-CTS 71435.520 4.682 0.050
Post-Routing 71435.520 4.583 0.548
result_pnr.rpt of period=30ns is listed as below:
Metric 5 CLKP(ns) WNS INT_PWR
(mw)
SWIT_PWR (mw) LEAK(mw) TOT_PWR(mw)
0.00741 30 0.548 1.801 2.01 0.772 4.583
3. Type of adder and multiplier implemented:
Adder: Non-linear carry select adder. The adder module includes 9 sub-adder modules. The first
module is a 4bit carry ripple adder, and the other sub-modules adopted the CSA structure, with
block size increasing from 4bit to 11bit uniformly.
4bit(carry ripple adder)-4bit(CSA)-5bit(CSA)-6bit(CSA)-7bit(CSA)-8bit(CSA)-9bit(CSA)-10bit(CSA)-
11bit(CSA)
Multiplier: Baugh Wooley multiplier is applied in order to handle the 2's complement calculation.
4. What has been tried to optimize our design:
1) RTL design stage:
Initially, the adder has been chosen to be implemented as carry look ahead (CLA adder. But as
this adder is relatively slow (although faster than carry ripple adder) and the design could not
meet the 30ns operating period requirement, linear carry select adder (CSA) has then been
applied to our design. To further improve the ALU's performance, we have then applied non-
linear CSA adder in order to achieve higher operating frequency and lower power consumption.
As the multiplier is using the same type of adder as defined in ADD module, the multiplier's
performance has been enhanced at same time through the whole optimization process.
2) Logic synthesis:
As the max transition requirement and clock uncertainty requirement have been fixed, the main
strategy that we could try is to simulate our design's performance at different frequencies.
Performance at following time period has been verified: 60ns, 50ns, 40ns, 30ns, 25ns, 23ns,
20ns, 15ns, 10ns. The highest frequency with WNS >0 is achieved at 15ns (66.7MHz) with
WNS=3.71933e-05.

2. ECE260B Mini-Project1 Fanyu Yang (A53102865) & Nian Jiang (A53070866)
3) Physical implementation:
In order to achieve best matric 5 result within 30ns period bound, we have tried to use the
netlist and timing constraint files generated with different timing period as the input of part3.
After several round of data collection, it has been found that metric5 is maximum when we used
the part2 output file with 25ns, and relaxed the period to 30ns by modify part2 output file
alu.sdc as the input of part3.