This document discusses design verification for a complex multiprocessor system-on-chip (SoC). It outlines the goals of validating the design for its intended applications and managing the complexity through: 1) breaking down verification into components; 2) staging verification over multiple environments; and 3) reusing tests, environments, and code across designs and teams.

1. Design Verification to Application
Validation of a Multiprocessor SoC
Ish Kumar Dham (dham@ti.com)
DSP Systems
Texas Instruments
14 Nov 2007 TI Proprietary Information

2. Structure
• Understanding the Complexity
– Design Goals
– Additional Verification Team Goals
– Application Validation Goals
– Environments & Tools
• Managing Complexity
– Breaking the complexity
– Staging it out
– Reuse
14 Nov 2007 TI Proprietary Information

3. Media Gateway
• Convergence of
Fixed Line &
Mobile
Mobile
Voice, Data
Multimedia Mobile Services
Network
• Mobile Broadband
Network
Data – not just
Voice Voice: email,
PSTN
Multimedia, Streaming
PSTN
Multimedia, Interactive
Media Gateway
• IP as the Pervasive
IP
IP
FAX
Network
Transport
Network
Network
Voice (VoIP) Technology
Data
Multimedia (Video/Audio)
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4. Innovation for Communications Infrastructure
Performance Power
6 x 500 MHz
Increases Channel C64x+ Cores allow
Density by 3X performance at
Over 500 G.711 lower voltage
Channels Large Shared L2
Over 200 G.729 Memory and next
Channels generation
C64x+ enables peripherals
Audio/Video reduce system
Transcode power dissipation
Enabled by world Separate power
class software: domains for high
Telogy Voice Software performance/high
Bundle, Voice & Video
Codecs, Telinnovations
power peripherals
Line Echo Cancelation
Software, PIQUA
Software
TNETV3020
14 Nov 2007 TI Proprietary Information

5. Design Complexity
• Large Design
– 10-15 M Gate Complexity
– Multiprocessor System – symmetric multiprocessing
• Local and Shared Memory
• Complex High Speed Interfaces : DDR, SRIO,
Gigabit Ethernet
• IP reused from previous designs + new IP
developed concurrently – locally as well as by
remote teams
• Power Management : Power Domains as well as
Clock Gating
– Dynamic as well as Static (some IPs always powered off
or powered on)
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6. Verification Goals
Release
Final Phy. Design To
to Applications
Runs Manufacturing
Team
Start Basic Major Modes RTL Tape Good
Ok to Verify Ok Freeze Out Chip
Setup Software Infra GLS,
Environment Integration Focus Manufacturing Tests
Key Module Functions All modes and
System Features Silicon Testbench
(FPGA)
14 Nov 2007 TI Proprietary Information

7. Application Validation Goals
Design Available on Accelerrated
Platform
Running
Apps
Start Basic Major Modes RTL Tape Good
Ok to Verify Ok Freeze Out Chip
Application Requirements Library Development All Application Scenarios
Testbench Requirements ROM Code Validation
Check out on Design Env. Real Applications
Basic Application
Scenarios Silicon Testbench
Critical Application Scenarios (FPGA)
Power Measurement
Tests
14 Nov 2007 TI Proprietary Information

8. Environments
Release
Final Phy. Design To
to Applications
Runs Manufacturing
Team
Sim-Acceleration
Formal
Simulation Tools FPGA
+ Si
Start Basic Major Modes RTL Tape Good
Ok to Verify Ok Freeze Chip
Specman Out
Setup Software Infra GLS,
Environment Integration Focus Manufacturing Tests
Key Module Functions All modes and
System Features Silicon Testbench
(FPGA)
14 Nov 2007 TI Proprietary Information

9. Managing Complexity
System
Complex
Performance,
t0
Power Mgmnt,
Verify Integration
RTL Simulation
Auto-Gen Basic Test
Reviews
Not all aspects easy to observe
Verify Components Separately
Formal, Specman
14 Nov 2007 TI Proprietary Information

10. Reuse
• Same test-bench used for RTL
simulations, GATE level, acceleration
platforms and final Silicon
– As Simulation Model, Synthesized to
Acceleration Environment and FPGA
• Same tests can run in all environments
– Not all are run. Actual runs are based off
needs.
• Reuse test benches and tests across
designs
• Share some low level and data bases code
with software teams
• Use test generators for basic tests
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11. Multiply & Not Add
• Break up tests into components that could be
permuted
X
– Same tests can be run from various memory locations
and PLL configurations
– With or without interrupts
• Tests written for one CPU run on other CPUs
• Multiple individual tests combined to run on
multiple CPUs
• Simple, small tests written so that changing
defines could make them large and complex tests
• Write tests like any software – build them in
layers
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12. Summary
• Verification teams not just prove designs
– they support H/W – S/W verification
too – Systems not just Chips
• Complexity broken out
• Application Validation and Design
Verification use a similar environment
• Early Application Validation
– High confidence on chip at Tape Out
– Applications running a few days after Silicon
14 Nov 2007 TI Proprietary Information