Serial peripheral interface (SPI) transfers the data between electronic devices like micro controllers and other peripherals. SPI consists of two control lines: select signal and clock signal, and two data lines: input and output. In single master-single slave, the communication is in between master and slave only which will make the design complex and costly, area will increase. In regular SPI mode, the number of chip-select lines is increased if the number of slaves increases. Due to this, the input data received by the master from the slaves are corrupted at master input slave output (MISO). The proposed daisy chain method is used to overcome this problem. The daisy chain method requires only one chip select line at master compared to the regular SPI mode. When the chip-select line is active low, all the slaves are active, and the clock is initiated to all the slaves to transfer the data from the master to the first slave through the master output slave input (MOSI). In this paper, the daisy-chain SPI is designed and developed using Verilog. The proposed design is verified using system Verilog (SV) and universal verification methodology (UVM) in QuestaSim.
Design and Verification of the UART and SPI protocol using UVMIRJET Journal
This document describes the design and verification of UART and SPI protocols using the Universal Verification Methodology (UVM). UART and SPI functional modules were designed in SystemVerilog and verified using a UVM testbench. The UVM testbench generated random stimuli and the scoreboard compared the simulated response to the expected response. Code coverage analysis was also performed to measure the amount of logic toggled. The UVM reports and code coverage results confirmed the functional correctness of the UART and SPI modules.
OPTICAL SWITCHING CONTROLLER USING FPGA AS A CONTROLLER FOR OCDMA ENCODER SYSTEMEditor IJCATR
This paper proposed a design of optical switching controller using FPGA for OCDMA encoder system. The encoder is one
of the new technologies that use to transmit the coded data in the optical communication system by using FPGA and optical switches.
It is providing a high security for data transmission due to all data will be transmitting in binary code form. The output signals from
FPGA are coded with a binary code that given to an optical switch before it signal modulate with the carrier and transmit to the
receiver. In this paper, AA and 55 data were used for source 1 and source 2. It is generated sample data and sent packet data to the
FPGA and stored it into RAM. The simulation results have done by using software Verilog Spartan 2 programming to simulate. After
that the output will produces at waveform to display the output. The main function of FPGA controlling unit is producing single pulse
and configuring optical switching system.
Serial Peripheral Interface Design for Advanced Microcontroller Bus Architect...IJMTST Journal
Design of System-on-Chip(SoC) receives a great deal of attention in recent days. The number of peripherals used in one SoC becomes larger and larger. Processors and peripherals usually communicate with each other using some protocol. With the development of SoC technique, the communication between processor and peripherals become a problem as processors have limited ports hence we design Serial Peripheral Interface to maximize the usage of the existing ports. We are designing a SPI Flash Controller which is compatible with the Advanced Microcontroller Bus Architecture (AMBA) developed by ARM. We are developing a SPI Module which can operate based on the Advanced High Performance Bus (AHB) signals. Any SPI Flash Slave can be interfaced with the SPI Module directly from the ARM Processor. This paper is concerned with design and implementation of a SPI Flash Controller on FPGA which can communicate with SPI Slaves. Tool used for simulation is ModelSim 10.1b and finally implementation include FPGA kit Spartan3 xc3s400-pq208 comprising of 208 pins synthesis carried on Xilinx v9.1.Implantable and medical devices (IMDs) have been advanced with the advancements in engineering and medical science. IMDs are used for applying new therapies to patients, monitoring human body parameters and making diagnosis as per the monitoring result. Increased use of IMDs has enhanced the chances of attacks to them. Therefore, to make use of IMDs for various applications, they need to be secured. A system is developed to achieve the security. The system monitors various human body parameters wirelessly and detects anomaly if unauthorized node participates in communication. The system uses request response protocol in wireless communication. Experiments show that body parameters can be successfully monitored and signal characteristic can be used to detect anomaly.
The document is an acknowledgement by the authors expressing gratitude to their guide Mr. Ratnesh S. Sengar and Mr. Saurabh Mishra for their guidance and support in successfully completing their project. It thanks them for their valuable suggestions, inspiration, and help throughout all stages of the project. The authors also acknowledge exchanging ideas with various other people.
1. To make asynchronous serial communication using a microcontroller's USART, the transmitter must configure the baud rate generator and enable transmission by writing data to the transmit register, while the receiver must configure the baud rate generator and enable reception to read incoming data from the receive register.
2. Key steps include setting the SPBRG register and BRGH bit to determine the baud rate, enabling the serial port and transmission/reception, handling 9-bit data if needed, and checking status registers for transmission completion or errors.
3. Asynchronous serial communication allows microcontrollers to transmit data bit by bit over a single line using start and stop bits for synchronization instead of a separate clock line.
High speed customized serial protocol for IP integration on FPGA based SOC ap...IJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
International Journal of Modern Engineering Research (IJMER) covers all the fields of engineering and science: Electrical Engineering, Mechanical Engineering, Civil Engineering, Chemical Engineering, Computer Engineering, Agricultural Engineering, Aerospace Engineering, Thermodynamics, Structural Engineering, Control Engineering, Robotics, Mechatronics, Fluid Mechanics, Nanotechnology, Simulators, Web-based Learning, Remote Laboratories, Engineering Design Methods, Education Research, Students' Satisfaction and Motivation, Global Projects, and Assessment…. And many more.
Giga bit per second Differential Scheme for High Speed InterconnectVLSICS Design
This document summarizes a research paper on developing a high-speed transmitter for off-chip communication using differential signaling. It describes a transmitter circuit that consists of low-speed input buffers, serializers to convert parallel data to serial data, and current-mode drivers to transmit the serial data differentially over transmission lines. The serializers use a delay locked loop to generate clock phases that sample the parallel inputs and transmit each bit over the serial link for an equal duration. The current-mode drivers convert the serial data to differential current levels on the transmission line. The design is intended to increase I/O bandwidth for high-speed chip-to-chip communication.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Design and Verification of the UART and SPI protocol using UVMIRJET Journal
This document describes the design and verification of UART and SPI protocols using the Universal Verification Methodology (UVM). UART and SPI functional modules were designed in SystemVerilog and verified using a UVM testbench. The UVM testbench generated random stimuli and the scoreboard compared the simulated response to the expected response. Code coverage analysis was also performed to measure the amount of logic toggled. The UVM reports and code coverage results confirmed the functional correctness of the UART and SPI modules.
OPTICAL SWITCHING CONTROLLER USING FPGA AS A CONTROLLER FOR OCDMA ENCODER SYSTEMEditor IJCATR
This paper proposed a design of optical switching controller using FPGA for OCDMA encoder system. The encoder is one
of the new technologies that use to transmit the coded data in the optical communication system by using FPGA and optical switches.
It is providing a high security for data transmission due to all data will be transmitting in binary code form. The output signals from
FPGA are coded with a binary code that given to an optical switch before it signal modulate with the carrier and transmit to the
receiver. In this paper, AA and 55 data were used for source 1 and source 2. It is generated sample data and sent packet data to the
FPGA and stored it into RAM. The simulation results have done by using software Verilog Spartan 2 programming to simulate. After
that the output will produces at waveform to display the output. The main function of FPGA controlling unit is producing single pulse
and configuring optical switching system.
Serial Peripheral Interface Design for Advanced Microcontroller Bus Architect...IJMTST Journal
Design of System-on-Chip(SoC) receives a great deal of attention in recent days. The number of peripherals used in one SoC becomes larger and larger. Processors and peripherals usually communicate with each other using some protocol. With the development of SoC technique, the communication between processor and peripherals become a problem as processors have limited ports hence we design Serial Peripheral Interface to maximize the usage of the existing ports. We are designing a SPI Flash Controller which is compatible with the Advanced Microcontroller Bus Architecture (AMBA) developed by ARM. We are developing a SPI Module which can operate based on the Advanced High Performance Bus (AHB) signals. Any SPI Flash Slave can be interfaced with the SPI Module directly from the ARM Processor. This paper is concerned with design and implementation of a SPI Flash Controller on FPGA which can communicate with SPI Slaves. Tool used for simulation is ModelSim 10.1b and finally implementation include FPGA kit Spartan3 xc3s400-pq208 comprising of 208 pins synthesis carried on Xilinx v9.1.Implantable and medical devices (IMDs) have been advanced with the advancements in engineering and medical science. IMDs are used for applying new therapies to patients, monitoring human body parameters and making diagnosis as per the monitoring result. Increased use of IMDs has enhanced the chances of attacks to them. Therefore, to make use of IMDs for various applications, they need to be secured. A system is developed to achieve the security. The system monitors various human body parameters wirelessly and detects anomaly if unauthorized node participates in communication. The system uses request response protocol in wireless communication. Experiments show that body parameters can be successfully monitored and signal characteristic can be used to detect anomaly.
The document is an acknowledgement by the authors expressing gratitude to their guide Mr. Ratnesh S. Sengar and Mr. Saurabh Mishra for their guidance and support in successfully completing their project. It thanks them for their valuable suggestions, inspiration, and help throughout all stages of the project. The authors also acknowledge exchanging ideas with various other people.
1. To make asynchronous serial communication using a microcontroller's USART, the transmitter must configure the baud rate generator and enable transmission by writing data to the transmit register, while the receiver must configure the baud rate generator and enable reception to read incoming data from the receive register.
2. Key steps include setting the SPBRG register and BRGH bit to determine the baud rate, enabling the serial port and transmission/reception, handling 9-bit data if needed, and checking status registers for transmission completion or errors.
3. Asynchronous serial communication allows microcontrollers to transmit data bit by bit over a single line using start and stop bits for synchronization instead of a separate clock line.
High speed customized serial protocol for IP integration on FPGA based SOC ap...IJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
International Journal of Modern Engineering Research (IJMER) covers all the fields of engineering and science: Electrical Engineering, Mechanical Engineering, Civil Engineering, Chemical Engineering, Computer Engineering, Agricultural Engineering, Aerospace Engineering, Thermodynamics, Structural Engineering, Control Engineering, Robotics, Mechatronics, Fluid Mechanics, Nanotechnology, Simulators, Web-based Learning, Remote Laboratories, Engineering Design Methods, Education Research, Students' Satisfaction and Motivation, Global Projects, and Assessment…. And many more.
Giga bit per second Differential Scheme for High Speed InterconnectVLSICS Design
This document summarizes a research paper on developing a high-speed transmitter for off-chip communication using differential signaling. It describes a transmitter circuit that consists of low-speed input buffers, serializers to convert parallel data to serial data, and current-mode drivers to transmit the serial data differentially over transmission lines. The serializers use a delay locked loop to generate clock phases that sample the parallel inputs and transmit each bit over the serial link for an equal duration. The current-mode drivers convert the serial data to differential current levels on the transmission line. The design is intended to increase I/O bandwidth for high-speed chip-to-chip communication.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
This document summarizes the implementation of pseudorandom binary sequences (PRBS), specifically maximal length sequences (MLS), for CDMA2000 using MATLAB Simulink. It discusses the properties of MLS, including their use as spreading codes in 2G and 3G standards. The autocorrelation and cross correlation properties of MLS are studied through simulation and verification. Implementation of a 42-stage MLS generator according to the CDMA2000 polynomial is presented.
Turbo codes are error-correcting codes with performance that is close to the
Shannon theoretical limit (SHA). The motivation for using turbo codes is
that the codes are an appealing mix of a random appearance on the channel
and a physically realizable decoding structure. The communication systems
have the problem of latency, fast switching, and reliable data transfer. The
objective of the research paper is to design and turbo encoder and decoder
hardware chip and analyze its performance. Two convolutional codes are
concatenated concurrently and detached by an interleaver or permuter in the
turbo encoder. The expected data from the channel is interpreted iteratively
using the two related decoders. The soft (probabilistic) data about an
individual bit of the decoded structure is passed in each cycle from one
elementary decoder to the next, and this information is updated regularly.
The performance of the chip is also verified using the maximum a posteriori
(MAP) method in the decoder chip. The performance of field-programmable
gate array (FPGA) hardware is evaluated using hardware and timing
parameters extracted from Xilinx ISE 14.7. The parallel concatenation offers
a better global rate for the same component code performance, and reduced
delay, low hardware complexity, and higher frequency support.
Serial peripheral Interface - Embedded System ProtocolAditya Porwal
Serial Peripheral Interface (SPI) is a synchronous serial data protocol used by micro-controllers for communicating with one or more peripheral devices quickly over short distances. It can also be used for communication between two micro-controllers.
The document discusses several topics related to digital signal processing and telecommunications networks:
1) It explains why analog signals need to be converted to digital for processing by microprocessors, and describes the steps of analog to digital and digital to analog conversion.
2) It defines pulse code modulation (PCM) and its role in encoding analog signals like speech into digital signals for transmission.
3) It discusses the use of multiplexing to combine multiple signals into a single channel for transmission over networks in order to save costs.
4) It provides an overview of the OSI model and its layered approach to network communication.
Performance Improvement of IEEE 802.22 WRAN Physical LayerIOSR Journals
The spectrum available for the wireless services is limited, the increased demand of wireless
application has put a lot of limitations on the utilization of available radio spectrum. For the efficient spectrum
utilization for wireless application IEEE 802.22 standard i.e. WRAN (Wireless Regional Area Network) is
developed which is based on cognitive radio technique that senses the free available spectrum. It allows sharing
of geographically unused channels allocated to the TV Broadcast Service, without interference.
In this paper we are evaluating the performance of WRAN over physical layer with QPSK, 16-QAM
and 64-QAM modulation with Convolution coding with code rate of 1/2, 2/3, 3/4, 5/6 and obtaining the BER
curves for rician channel. Simulation is performed in MATLAB
Performance Improvement of IEEE 802.22 WRAN Physical LayerIOSR Journals
Abstract: The spectrum available for the wireless services is limited, the increased demand of wireless
application has put a lot of limitations on the utilization of available radio spectrum. For the efficient spectrum
utilization for wireless application IEEE 802.22 standard i.e. WRAN (Wireless Regional Area Network) is
developed which is based on cognitive radio technique that senses the free available spectrum. It allows sharing
of geographically unused channels allocated to the TV Broadcast Service, without interference.
In this paper we are evaluating the performance of WRAN over physical layer with QPSK, 16-QAM
and 64-QAM modulation with Convolution coding with code rate of 1/2, 2/3, 3/4, 5/6 and obtaining the BER
curves for rician channel. Simulation is performed in MATLAB.
Keywords - CC, CP, CR, OFDMA, PHY Layer, WRAN
Performance Improvement of IEEE 802.22 WRAN Physical LayerIOSR Journals
Abstract: The spectrum available for the wireless services is limited, the increased demand of wireless application has put a lot of limitations on the utilization of available radio spectrum. For the efficient spectrum utilization for wireless application IEEE 802.22 standard i.e. WRAN (Wireless Regional Area Network) is developed which is based on cognitive radio technique that senses the free available spectrum. It allows sharing of geographically unused channels allocated to the TV Broadcast Service, without interference. In this paper we are evaluating the performance of WRAN over physical layer with QPSK, 16-QAM and 64-QAM modulation with Convolution coding with code rate of 1/2, 2/3, 3/4, 5/6 and obtaining the BER curves for rician channel. Simulation is performed in MATLAB. Keywords - CC, CP, CR, OFDMA, PHY Layer, WRAN
ANALYSIS OF ROUTING PROTOCOLS IN WIRELESS MESH NETWORKIJCSIT Journal
There are two methods to improve the performance of routing protocols in wireless mesh networks. One way is to improve the methods used for select the path. Second way is to improve the algorithms to add up the new characteristics of wireless mesh networks. We also propose a new protocol that is used for Multi Interfaces and Multiple Channels (MIMC) named as Hybrid Wireless Mesh Protocol.
IRJET-Simulation of Channel-Estimation for Digital Communication System based...IRJET Journal
This document summarizes a simulation of an OFDM digital communication system that uses different modulation techniques. It describes:
1) The OFDM system model that uses techniques like BPSK, QPSK, 16-PSK and 256-PSK modulation to transmit data in the form of a grayscale image file.
2) How the system works, including converting the image to OFDM symbols, transmitting over an AWGN channel, and reconstructing the image at the receiver.
3) The results of simulations comparing different modulation techniques in terms of runtime, bit error rate, and pixel error for varying signal to noise ratios. The simulations show higher order modulations having higher error rates but lower runtimes.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Iterative network channel decoding with cooperative space-time transmissionijasuc
This document summarizes an iterative network-channel decoding scheme for cooperative space-time transmission with network coding. The scheme uses convolutional codes as network codes at the relay node and Reed-Solomon codes as channel codes at the user nodes. An iterative joint network-channel decoder exchanges soft information between convolutional code-based network decoder and Reed-Solomon code-based channel decoders. Extrinsic information transfer analysis is performed to investigate the convergence properties of the proposed iterative decoder.
This document describes the design and implementation of a serial communication protocol conversion system and circular buffer in an FPGA for monitoring a Tesla meter. The system includes controllers for RS232 and RS485 serial communication, a protocol conversion unit between the two interfaces, and a circular buffer. The controllers are designed using Verilog HDL and implemented on a Spartan FPGA. Simulation and hardware results demonstrate that the system successfully converts between the RS232 and RS485 protocols in real-time and stores data in the circular buffer for offline analysis.
Serial Communication Interface with Error Detectioniosrjce
UART is used for serial data communication. UART is a piece of computer hardware that translates
between parallel bits of data and serial bits. UART is usually an integrated circuit used for serial
communications over a computer or peripheral device serial port. Bits have to be moved from one place to
another using wires or some other medium. Over many miles, the expense of the wires becomes large. To reduce
the expense of long communication links carrying several bits in parallel, data bits are sent sequentially. Errors
may occur either internally or externally while we transmit information from source to destination. The errors
generated during the transmission would affect the performance of the overall system. In order to reduce the
errors we should incorporate any error detecting schemes like hamming decoder, check parity systems etc.
Different serial communication devices are available.
This document discusses serial communication interfaces and error detection techniques. It begins with an introduction to serial communication interfaces and some common interfaces like RS-232, I2C, and SPI. It then discusses the differences between synchronous and asynchronous serial communication. The bulk of the document focuses on using Hamming codes for error detection and correction in serial transmission. It provides an example of how Hamming codes can be used to detect and correct single bit errors in transmitted data. The document concludes by stating that error correction can improve the reliability and fault tolerance of integrated circuits.
FPGA based Data Scrambler for Ultra-Wideband Communication Systemsidescitation
Ultra-Wideband (UWB) communication systems are
currently the focus of research and development in wireless
personal area networks (WPANs). These systems are capable
of transferring data from a rate of 110Mbps to 480Mbps in
realistic multipath environment. They consume very little
power and silicon area. In such systems, synchronization plays
very critical role to ensure correct and reliable system
operation. Improper synchronization can introduce timing
errors during transmission that can be eliminated using a
device called scrambler. In this paper, the scrambler for UWB
communication systems has been modeled and simulated using
Matlab and Xilinx’s System Generator for DSP (Digital Signal
Processing). Implementation of the scrambler has also been
done on Spartan 3E FPGA (Field Programmable Gate Array)
chip using Xilinx’s ISE Design Suite and results are compared.
Performance analysis and implementation of modified sdm based noc for mpsoc o...eSAT Journals
Abstract To meet todays demanding requirements lowpower consumption, high performance while maintaing flexibility and scalability,
system-On-Chip will combine several number of processors cores and other IPs with network-On-chip. To implement NoC based
MPSoC on an FPGA, NoCs should provide guaranteed services and be run-time reconfigurable. Current TDM and SDM based
NoCs takes more area and would not support run-time reconfiguration. This paper presents modified spatial division multiplexing
based NoC on FPGA, in this we have modified complex network interface and proposed flexible network interface and efficient
SDM based NoC.This architecture explored feasibility of connection requirements from IP cores during run-time.
Keywords: NoC, MPSoC, FPGA, NoCs, SDM Based NoC
This document discusses implementing security and steganography in 802.11n networks. It proposes hiding information in the cyclic prefix of OFDM symbols. Modifying the cyclic prefix does not require additional bandwidth and increases the potential hidden transmission capacity depending on the modulation scheme. Simulation results show the steganographic system does not increase costs for ordinary users and security is improved by using private keys to randomly select modified symbols.
IRJET- Power Line Carrier CommunicationIRJET Journal
This document describes power line carrier communication (PLCC), which uses power lines as a communication medium. It discusses using PLCC to transmit electricity billing data from individual homes to the electricity company without site visits. Key components of the system include a real-time clock, energy meter, microcontroller, LCD display, and FSK transmitter and receiver. Data transmission is done by modulating a signal onto the power line using FSK modulation. The system is intended to reduce the burden on electricity companies by allowing remote transmission of billing data without the need for site visits.
Implementation of a bit error rate tester of a wireless communication system ...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Amazon products reviews classification based on machine learning, deep learni...TELKOMNIKA JOURNAL
In recent times, the trend of online shopping through e-commerce stores and websites has grown to a huge extent. Whenever a product is purchased on an e-commerce platform, people leave their reviews about the product. These reviews are very helpful for the store owners and the product’s manufacturers for the betterment of their work process as well as product quality. An automated system is proposed in this work that operates on two datasets D1 and D2 obtained from Amazon. After certain preprocessing steps, N-gram and word embedding-based features are extracted using term frequency-inverse document frequency (TF-IDF), bag of words (BoW) and global vectors (GloVe), and Word2vec, respectively. Four machine learning (ML) models support vector machines (SVM), logistic regression (RF), logistic regression (LR), multinomial Naïve Bayes (MNB), two deep learning (DL) models convolutional neural network (CNN), long-short term memory (LSTM), and standalone bidirectional encoder representations (BERT) are used to classify reviews as either positive or negative. The results obtained by the standard ML, DL models and BERT are evaluated using certain performance evaluation measures. BERT turns out to be the best-performing model in the case of D1 with an accuracy of 90% on features derived by word embedding models while the CNN provides the best accuracy of 97% upon word embedding features in the case of D2. The proposed model shows better overall performance on D2 as compared to D1.
Design, simulation, and analysis of microstrip patch antenna for wireless app...TELKOMNIKA JOURNAL
In this study, a microstrip patch antenna that works at 3.6 GHz was built and tested to see how well it works. In this work, Rogers RT/Duroid 5880 has been used as the substrate material, with a dielectric permittivity of 2.2 and a thickness of 0.3451 mm; it serves as the base for the examined antenna. The computer simulation technology (CST) studio suite is utilized to show the recommended antenna design. The goal of this study was to get a more extensive transmission capacity, a lower voltage standing wave ratio (VSWR), and a lower return loss, but the main goal was to get a higher gain, directivity, and efficiency. After simulation, the return loss, gain, directivity, bandwidth, and efficiency of the supplied antenna are found to be -17.626 dB, 9.671 dBi, 9.924 dBi, 0.2 GHz, and 97.45%, respectively. Besides, the recreation uncovered that the transfer speed side-lobe level at phi was much better than those of the earlier works, at -28.8 dB, respectively. Thus, it makes a solid contender for remote innovation and more robust communication.
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Similar to Design and verification of daisy chain serial peripheral interface using system Verilog and universal verification methodology
This document summarizes the implementation of pseudorandom binary sequences (PRBS), specifically maximal length sequences (MLS), for CDMA2000 using MATLAB Simulink. It discusses the properties of MLS, including their use as spreading codes in 2G and 3G standards. The autocorrelation and cross correlation properties of MLS are studied through simulation and verification. Implementation of a 42-stage MLS generator according to the CDMA2000 polynomial is presented.
Turbo codes are error-correcting codes with performance that is close to the
Shannon theoretical limit (SHA). The motivation for using turbo codes is
that the codes are an appealing mix of a random appearance on the channel
and a physically realizable decoding structure. The communication systems
have the problem of latency, fast switching, and reliable data transfer. The
objective of the research paper is to design and turbo encoder and decoder
hardware chip and analyze its performance. Two convolutional codes are
concatenated concurrently and detached by an interleaver or permuter in the
turbo encoder. The expected data from the channel is interpreted iteratively
using the two related decoders. The soft (probabilistic) data about an
individual bit of the decoded structure is passed in each cycle from one
elementary decoder to the next, and this information is updated regularly.
The performance of the chip is also verified using the maximum a posteriori
(MAP) method in the decoder chip. The performance of field-programmable
gate array (FPGA) hardware is evaluated using hardware and timing
parameters extracted from Xilinx ISE 14.7. The parallel concatenation offers
a better global rate for the same component code performance, and reduced
delay, low hardware complexity, and higher frequency support.
Serial peripheral Interface - Embedded System ProtocolAditya Porwal
Serial Peripheral Interface (SPI) is a synchronous serial data protocol used by micro-controllers for communicating with one or more peripheral devices quickly over short distances. It can also be used for communication between two micro-controllers.
The document discusses several topics related to digital signal processing and telecommunications networks:
1) It explains why analog signals need to be converted to digital for processing by microprocessors, and describes the steps of analog to digital and digital to analog conversion.
2) It defines pulse code modulation (PCM) and its role in encoding analog signals like speech into digital signals for transmission.
3) It discusses the use of multiplexing to combine multiple signals into a single channel for transmission over networks in order to save costs.
4) It provides an overview of the OSI model and its layered approach to network communication.
Performance Improvement of IEEE 802.22 WRAN Physical LayerIOSR Journals
The spectrum available for the wireless services is limited, the increased demand of wireless
application has put a lot of limitations on the utilization of available radio spectrum. For the efficient spectrum
utilization for wireless application IEEE 802.22 standard i.e. WRAN (Wireless Regional Area Network) is
developed which is based on cognitive radio technique that senses the free available spectrum. It allows sharing
of geographically unused channels allocated to the TV Broadcast Service, without interference.
In this paper we are evaluating the performance of WRAN over physical layer with QPSK, 16-QAM
and 64-QAM modulation with Convolution coding with code rate of 1/2, 2/3, 3/4, 5/6 and obtaining the BER
curves for rician channel. Simulation is performed in MATLAB
Performance Improvement of IEEE 802.22 WRAN Physical LayerIOSR Journals
Abstract: The spectrum available for the wireless services is limited, the increased demand of wireless
application has put a lot of limitations on the utilization of available radio spectrum. For the efficient spectrum
utilization for wireless application IEEE 802.22 standard i.e. WRAN (Wireless Regional Area Network) is
developed which is based on cognitive radio technique that senses the free available spectrum. It allows sharing
of geographically unused channels allocated to the TV Broadcast Service, without interference.
In this paper we are evaluating the performance of WRAN over physical layer with QPSK, 16-QAM
and 64-QAM modulation with Convolution coding with code rate of 1/2, 2/3, 3/4, 5/6 and obtaining the BER
curves for rician channel. Simulation is performed in MATLAB.
Keywords - CC, CP, CR, OFDMA, PHY Layer, WRAN
Performance Improvement of IEEE 802.22 WRAN Physical LayerIOSR Journals
Abstract: The spectrum available for the wireless services is limited, the increased demand of wireless application has put a lot of limitations on the utilization of available radio spectrum. For the efficient spectrum utilization for wireless application IEEE 802.22 standard i.e. WRAN (Wireless Regional Area Network) is developed which is based on cognitive radio technique that senses the free available spectrum. It allows sharing of geographically unused channels allocated to the TV Broadcast Service, without interference. In this paper we are evaluating the performance of WRAN over physical layer with QPSK, 16-QAM and 64-QAM modulation with Convolution coding with code rate of 1/2, 2/3, 3/4, 5/6 and obtaining the BER curves for rician channel. Simulation is performed in MATLAB. Keywords - CC, CP, CR, OFDMA, PHY Layer, WRAN
ANALYSIS OF ROUTING PROTOCOLS IN WIRELESS MESH NETWORKIJCSIT Journal
There are two methods to improve the performance of routing protocols in wireless mesh networks. One way is to improve the methods used for select the path. Second way is to improve the algorithms to add up the new characteristics of wireless mesh networks. We also propose a new protocol that is used for Multi Interfaces and Multiple Channels (MIMC) named as Hybrid Wireless Mesh Protocol.
IRJET-Simulation of Channel-Estimation for Digital Communication System based...IRJET Journal
This document summarizes a simulation of an OFDM digital communication system that uses different modulation techniques. It describes:
1) The OFDM system model that uses techniques like BPSK, QPSK, 16-PSK and 256-PSK modulation to transmit data in the form of a grayscale image file.
2) How the system works, including converting the image to OFDM symbols, transmitting over an AWGN channel, and reconstructing the image at the receiver.
3) The results of simulations comparing different modulation techniques in terms of runtime, bit error rate, and pixel error for varying signal to noise ratios. The simulations show higher order modulations having higher error rates but lower runtimes.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Iterative network channel decoding with cooperative space-time transmissionijasuc
This document summarizes an iterative network-channel decoding scheme for cooperative space-time transmission with network coding. The scheme uses convolutional codes as network codes at the relay node and Reed-Solomon codes as channel codes at the user nodes. An iterative joint network-channel decoder exchanges soft information between convolutional code-based network decoder and Reed-Solomon code-based channel decoders. Extrinsic information transfer analysis is performed to investigate the convergence properties of the proposed iterative decoder.
This document describes the design and implementation of a serial communication protocol conversion system and circular buffer in an FPGA for monitoring a Tesla meter. The system includes controllers for RS232 and RS485 serial communication, a protocol conversion unit between the two interfaces, and a circular buffer. The controllers are designed using Verilog HDL and implemented on a Spartan FPGA. Simulation and hardware results demonstrate that the system successfully converts between the RS232 and RS485 protocols in real-time and stores data in the circular buffer for offline analysis.
Serial Communication Interface with Error Detectioniosrjce
UART is used for serial data communication. UART is a piece of computer hardware that translates
between parallel bits of data and serial bits. UART is usually an integrated circuit used for serial
communications over a computer or peripheral device serial port. Bits have to be moved from one place to
another using wires or some other medium. Over many miles, the expense of the wires becomes large. To reduce
the expense of long communication links carrying several bits in parallel, data bits are sent sequentially. Errors
may occur either internally or externally while we transmit information from source to destination. The errors
generated during the transmission would affect the performance of the overall system. In order to reduce the
errors we should incorporate any error detecting schemes like hamming decoder, check parity systems etc.
Different serial communication devices are available.
This document discusses serial communication interfaces and error detection techniques. It begins with an introduction to serial communication interfaces and some common interfaces like RS-232, I2C, and SPI. It then discusses the differences between synchronous and asynchronous serial communication. The bulk of the document focuses on using Hamming codes for error detection and correction in serial transmission. It provides an example of how Hamming codes can be used to detect and correct single bit errors in transmitted data. The document concludes by stating that error correction can improve the reliability and fault tolerance of integrated circuits.
FPGA based Data Scrambler for Ultra-Wideband Communication Systemsidescitation
Ultra-Wideband (UWB) communication systems are
currently the focus of research and development in wireless
personal area networks (WPANs). These systems are capable
of transferring data from a rate of 110Mbps to 480Mbps in
realistic multipath environment. They consume very little
power and silicon area. In such systems, synchronization plays
very critical role to ensure correct and reliable system
operation. Improper synchronization can introduce timing
errors during transmission that can be eliminated using a
device called scrambler. In this paper, the scrambler for UWB
communication systems has been modeled and simulated using
Matlab and Xilinx’s System Generator for DSP (Digital Signal
Processing). Implementation of the scrambler has also been
done on Spartan 3E FPGA (Field Programmable Gate Array)
chip using Xilinx’s ISE Design Suite and results are compared.
Performance analysis and implementation of modified sdm based noc for mpsoc o...eSAT Journals
Abstract To meet todays demanding requirements lowpower consumption, high performance while maintaing flexibility and scalability,
system-On-Chip will combine several number of processors cores and other IPs with network-On-chip. To implement NoC based
MPSoC on an FPGA, NoCs should provide guaranteed services and be run-time reconfigurable. Current TDM and SDM based
NoCs takes more area and would not support run-time reconfiguration. This paper presents modified spatial division multiplexing
based NoC on FPGA, in this we have modified complex network interface and proposed flexible network interface and efficient
SDM based NoC.This architecture explored feasibility of connection requirements from IP cores during run-time.
Keywords: NoC, MPSoC, FPGA, NoCs, SDM Based NoC
This document discusses implementing security and steganography in 802.11n networks. It proposes hiding information in the cyclic prefix of OFDM symbols. Modifying the cyclic prefix does not require additional bandwidth and increases the potential hidden transmission capacity depending on the modulation scheme. Simulation results show the steganographic system does not increase costs for ordinary users and security is improved by using private keys to randomly select modified symbols.
IRJET- Power Line Carrier CommunicationIRJET Journal
This document describes power line carrier communication (PLCC), which uses power lines as a communication medium. It discusses using PLCC to transmit electricity billing data from individual homes to the electricity company without site visits. Key components of the system include a real-time clock, energy meter, microcontroller, LCD display, and FSK transmitter and receiver. Data transmission is done by modulating a signal onto the power line using FSK modulation. The system is intended to reduce the burden on electricity companies by allowing remote transmission of billing data without the need for site visits.
Implementation of a bit error rate tester of a wireless communication system ...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Similar to Design and verification of daisy chain serial peripheral interface using system Verilog and universal verification methodology (20)
Amazon products reviews classification based on machine learning, deep learni...TELKOMNIKA JOURNAL
In recent times, the trend of online shopping through e-commerce stores and websites has grown to a huge extent. Whenever a product is purchased on an e-commerce platform, people leave their reviews about the product. These reviews are very helpful for the store owners and the product’s manufacturers for the betterment of their work process as well as product quality. An automated system is proposed in this work that operates on two datasets D1 and D2 obtained from Amazon. After certain preprocessing steps, N-gram and word embedding-based features are extracted using term frequency-inverse document frequency (TF-IDF), bag of words (BoW) and global vectors (GloVe), and Word2vec, respectively. Four machine learning (ML) models support vector machines (SVM), logistic regression (RF), logistic regression (LR), multinomial Naïve Bayes (MNB), two deep learning (DL) models convolutional neural network (CNN), long-short term memory (LSTM), and standalone bidirectional encoder representations (BERT) are used to classify reviews as either positive or negative. The results obtained by the standard ML, DL models and BERT are evaluated using certain performance evaluation measures. BERT turns out to be the best-performing model in the case of D1 with an accuracy of 90% on features derived by word embedding models while the CNN provides the best accuracy of 97% upon word embedding features in the case of D2. The proposed model shows better overall performance on D2 as compared to D1.
Design, simulation, and analysis of microstrip patch antenna for wireless app...TELKOMNIKA JOURNAL
In this study, a microstrip patch antenna that works at 3.6 GHz was built and tested to see how well it works. In this work, Rogers RT/Duroid 5880 has been used as the substrate material, with a dielectric permittivity of 2.2 and a thickness of 0.3451 mm; it serves as the base for the examined antenna. The computer simulation technology (CST) studio suite is utilized to show the recommended antenna design. The goal of this study was to get a more extensive transmission capacity, a lower voltage standing wave ratio (VSWR), and a lower return loss, but the main goal was to get a higher gain, directivity, and efficiency. After simulation, the return loss, gain, directivity, bandwidth, and efficiency of the supplied antenna are found to be -17.626 dB, 9.671 dBi, 9.924 dBi, 0.2 GHz, and 97.45%, respectively. Besides, the recreation uncovered that the transfer speed side-lobe level at phi was much better than those of the earlier works, at -28.8 dB, respectively. Thus, it makes a solid contender for remote innovation and more robust communication.
Design and simulation an optimal enhanced PI controller for congestion avoida...TELKOMNIKA JOURNAL
This document describes using a snake optimization algorithm to tune the gains of an enhanced proportional-integral controller for congestion avoidance in a TCP/AQM system. The controller aims to maintain a stable and desired queue size without noise or transmission problems. A linearized model of the TCP/AQM system is presented. An enhanced PI controller combining nonlinear gain and original PI gains is proposed. The snake optimization algorithm is then used to tune the parameters of the enhanced PI controller to achieve optimal system performance and response. Simulation results are discussed showing the proposed controller provides a stable and robust behavior for congestion control.
Improving the detection of intrusion in vehicular ad-hoc networks with modifi...TELKOMNIKA JOURNAL
Vehicular ad-hoc networks (VANETs) are wireless-equipped vehicles that form networks along the road. The security of this network has been a major challenge. The identity-based cryptosystem (IBC) previously used to secure the networks suffers from membership authentication security features. This paper focuses on improving the detection of intruders in VANETs with a modified identity-based cryptosystem (MIBC). The MIBC is developed using a non-singular elliptic curve with Lagrange interpolation. The public key of vehicles and roadside units on the network are derived from number plates and location identification numbers, respectively. Pseudo-identities are used to mask the real identity of users to preserve their privacy. The membership authentication mechanism ensures that only valid and authenticated members of the network are allowed to join the network. The performance of the MIBC is evaluated using intrusion detection ratio (IDR) and computation time (CT) and then validated with the existing IBC. The result obtained shows that the MIBC recorded an IDR of 99.3% against 94.3% obtained for the existing identity-based cryptosystem (EIBC) for 140 unregistered vehicles attempting to intrude on the network. The MIBC shows lower CT values of 1.17 ms against 1.70 ms for EIBC. The MIBC can be used to improve the security of VANETs.
Conceptual model of internet banking adoption with perceived risk and trust f...TELKOMNIKA JOURNAL
Understanding the primary factors of internet banking (IB) acceptance is critical for both banks and users; nevertheless, our knowledge of the role of users’ perceived risk and trust in IB adoption is limited. As a result, we develop a conceptual model by incorporating perceived risk and trust into the technology acceptance model (TAM) theory toward the IB. The proper research emphasized that the most essential component in explaining IB adoption behavior is behavioral intention to use IB adoption. TAM is helpful for figuring out how elements that affect IB adoption are connected to one another. According to previous literature on IB and the use of such technology in Iraq, one has to choose a theoretical foundation that may justify the acceptance of IB from the customer’s perspective. The conceptual model was therefore constructed using the TAM as a foundation. Furthermore, perceived risk and trust were added to the TAM dimensions as external factors. The key objective of this work was to extend the TAM to construct a conceptual model for IB adoption and to get sufficient theoretical support from the existing literature for the essential elements and their relationships in order to unearth new insights about factors responsible for IB adoption.
Efficient combined fuzzy logic and LMS algorithm for smart antennaTELKOMNIKA JOURNAL
The smart antennas are broadly used in wireless communication. The least mean square (LMS) algorithm is a procedure that is concerned in controlling the smart antenna pattern to accommodate specified requirements such as steering the beam toward the desired signal, in addition to placing the deep nulls in the direction of unwanted signals. The conventional LMS (C-LMS) has some drawbacks like slow convergence speed besides high steady state fluctuation error. To overcome these shortcomings, the present paper adopts an adaptive fuzzy control step size least mean square (FC-LMS) algorithm to adjust its step size. Computer simulation outcomes illustrate that the given model has fast convergence rate as well as low mean square error steady state.
Design and implementation of a LoRa-based system for warning of forest fireTELKOMNIKA JOURNAL
This paper presents the design and implementation of a forest fire monitoring and warning system based on long range (LoRa) technology, a novel ultra-low power consumption and long-range wireless communication technology for remote sensing applications. The proposed system includes a wireless sensor network that records environmental parameters such as temperature, humidity, wind speed, and carbon dioxide (CO2) concentration in the air, as well as taking infrared photos.The data collected at each sensor node will be transmitted to the gateway via LoRa wireless transmission. Data will be collected, processed, and uploaded to a cloud database at the gateway. An Android smartphone application that allows anyone to easily view the recorded data has been developed. When a fire is detected, the system will sound a siren and send a warning message to the responsible personnel, instructing them to take appropriate action. Experiments in Tram Chim Park, Vietnam, have been conducted to verify and evaluate the operation of the system.
Wavelet-based sensing technique in cognitive radio networkTELKOMNIKA JOURNAL
Cognitive radio is a smart radio that can change its transmitter parameter based on interaction with the environment in which it operates. The demand for frequency spectrum is growing due to a big data issue as many Internet of Things (IoT) devices are in the network. Based on previous research, most frequency spectrum was used, but some spectrums were not used, called spectrum hole. Energy detection is one of the spectrum sensing methods that has been frequently used since it is easy to use and does not require license users to have any prior signal understanding. But this technique is incapable of detecting at low signal-to-noise ratio (SNR) levels. Therefore, the wavelet-based sensing is proposed to overcome this issue and detect spectrum holes. The main objective of this work is to evaluate the performance of wavelet-based sensing and compare it with the energy detection technique. The findings show that the percentage of detection in wavelet-based sensing is 83% higher than energy detection performance. This result indicates that the wavelet-based sensing has higher precision in detection and the interference towards primary user can be decreased.
A novel compact dual-band bandstop filter with enhanced rejection bandsTELKOMNIKA JOURNAL
In this paper, we present the design of a new wide dual-band bandstop filter (DBBSF) using nonuniform transmission lines. The method used to design this filter is to replace conventional uniform transmission lines with nonuniform lines governed by a truncated Fourier series. Based on how impedances are profiled in the proposed DBBSF structure, the fractional bandwidths of the two 10 dB-down rejection bands are widened to 39.72% and 52.63%, respectively, and the physical size has been reduced compared to that of the filter with the uniform transmission lines. The results of the electromagnetic (EM) simulation support the obtained analytical response and show an improved frequency behavior.
Deep learning approach to DDoS attack with imbalanced data at the application...TELKOMNIKA JOURNAL
A distributed denial of service (DDoS) attack is where one or more computers attack or target a server computer, by flooding internet traffic to the server. As a result, the server cannot be accessed by legitimate users. A result of this attack causes enormous losses for a company because it can reduce the level of user trust, and reduce the company’s reputation to lose customers due to downtime. One of the services at the application layer that can be accessed by users is a web-based lightweight directory access protocol (LDAP) service that can provide safe and easy services to access directory applications. We used a deep learning approach to detect DDoS attacks on the CICDDoS 2019 dataset on a complex computer network at the application layer to get fast and accurate results for dealing with unbalanced data. Based on the results obtained, it is observed that DDoS attack detection using a deep learning approach on imbalanced data performs better when implemented using synthetic minority oversampling technique (SMOTE) method for binary classes. On the other hand, the proposed deep learning approach performs better for detecting DDoS attacks in multiclass when implemented using the adaptive synthetic (ADASYN) method.
The appearance of uncertainties and disturbances often effects the characteristics of either linear or nonlinear systems. Plus, the stabilization process may be deteriorated thus incurring a catastrophic effect to the system performance. As such, this manuscript addresses the concept of matching condition for the systems that are suffering from miss-match uncertainties and exogeneous disturbances. The perturbation towards the system at hand is assumed to be known and unbounded. To reach this outcome, uncertainties and their classifications are reviewed thoroughly. The structural matching condition is proposed and tabulated in the proposition 1. Two types of mathematical expressions are presented to distinguish the system with matched uncertainty and the system with miss-matched uncertainty. Lastly, two-dimensional numerical expressions are provided to practice the proposed proposition. The outcome shows that matching condition has the ability to change the system to a design-friendly model for asymptotic stabilization.
Implementation of FinFET technology based low power 4×4 Wallace tree multipli...TELKOMNIKA JOURNAL
Many systems, including digital signal processors, finite impulse response (FIR) filters, application-specific integrated circuits, and microprocessors, use multipliers. The demand for low power multipliers is gradually rising day by day in the current technological trend. In this study, we describe a 4×4 Wallace multiplier based on a carry select adder (CSA) that uses less power and has a better power delay product than existing multipliers. HSPICE tool at 16 nm technology is used to simulate the results. In comparison to the traditional CSA-based multiplier, which has a power consumption of 1.7 µW and power delay product (PDP) of 57.3 fJ, the results demonstrate that the Wallace multiplier design employing CSA with first zero finding logic (FZF) logic has the lowest power consumption of 1.4 µW and PDP of 27.5 fJ.
Evaluation of the weighted-overlap add model with massive MIMO in a 5G systemTELKOMNIKA JOURNAL
The flaw in 5G orthogonal frequency division multiplexing (OFDM) becomes apparent in high-speed situations. Because the doppler effect causes frequency shifts, the orthogonality of OFDM subcarriers is broken, lowering both their bit error rate (BER) and throughput output. As part of this research, we use a novel design that combines massive multiple input multiple output (MIMO) and weighted overlap and add (WOLA) to improve the performance of 5G systems. To determine which design is superior, throughput and BER are calculated for both the proposed design and OFDM. The results of the improved system show a massive improvement in performance ver the conventional system and significant improvements with massive MIMO, including the best throughput and BER. When compared to conventional systems, the improved system has a throughput that is around 22% higher and the best performance in terms of BER, but it still has around 25% less error than OFDM.
Reflector antenna design in different frequencies using frequency selective s...TELKOMNIKA JOURNAL
In this study, it is aimed to obtain two different asymmetric radiation patterns obtained from antennas in the shape of the cross-section of a parabolic reflector (fan blade type antennas) and antennas with cosecant-square radiation characteristics at two different frequencies from a single antenna. For this purpose, firstly, a fan blade type antenna design will be made, and then the reflective surface of this antenna will be completed to the shape of the reflective surface of the antenna with the cosecant-square radiation characteristic with the frequency selective surface designed to provide the characteristics suitable for the purpose. The frequency selective surface designed and it provides the perfect transmission as possible at 4 GHz operating frequency, while it will act as a band-quenching filter for electromagnetic waves at 5 GHz operating frequency and will be a reflective surface. Thanks to this frequency selective surface to be used as a reflective surface in the antenna, a fan blade type radiation characteristic at 4 GHz operating frequency will be obtained, while a cosecant-square radiation characteristic at 5 GHz operating frequency will be obtained.
Reagentless iron detection in water based on unclad fiber optical sensorTELKOMNIKA JOURNAL
A simple and low-cost fiber based optical sensor for iron detection is demonstrated in this paper. The sensor head consist of an unclad optical fiber with the unclad length of 1 cm and it has a straight structure. Results obtained shows a linear relationship between the output light intensity and iron concentration, illustrating the functionality of this iron optical sensor. Based on the experimental results, the sensitivity and linearity are achieved at 0.0328/ppm and 0.9824 respectively at the wavelength of 690 nm. With the same wavelength, other performance parameters are also studied. Resolution and limit of detection (LOD) are found to be 0.3049 ppm and 0.0755 ppm correspondingly. This iron sensor is advantageous in that it does not require any reagent for detection, enabling it to be simpler and cost-effective in the implementation of the iron sensing.
Impact of CuS counter electrode calcination temperature on quantum dot sensit...TELKOMNIKA JOURNAL
In place of the commercial Pt electrode used in quantum sensitized solar cells, the low-cost CuS cathode is created using electrophoresis. High resolution scanning electron microscopy and X-ray diffraction were used to analyze the structure and morphology of structural cubic samples with diameters ranging from 40 nm to 200 nm. The conversion efficiency of solar cells is significantly impacted by the calcination temperatures of cathodes at 100 °C, 120 °C, 150 °C, and 180 °C under vacuum. The fluorine doped tin oxide (FTO)/CuS cathode electrode reached a maximum efficiency of 3.89% when it was calcined at 120 °C. Compared to other temperature combinations, CuS nanoparticles crystallize at 120 °C, which lowers resistance while increasing electron lifetime.
In place of the commercial Pt electrode used in quantum sensitized solar cells, the low-cost CuS cathode is created using electrophoresis. High resolution scanning electron microscopy and X-ray diffraction were used to analyze the structure and morphology of structural cubic samples with diameters ranging from 40 nm to 200 nm. The conversion efficiency of solar cells is significantly impacted by the calcination temperatures of cathodes at 100 °C, 120 °C, 150 °C, and 180 °C under vacuum. The fluorine doped tin oxide (FTO)/CuS cathode electrode reached a maximum efficiency of 3.89% when it was calcined at 120 °C. Compared to other temperature combinations, CuS nanoparticles crystallize at 120 °C, which lowers resistance while increasing electron lifetime.
A progressive learning for structural tolerance online sequential extreme lea...TELKOMNIKA JOURNAL
This article discusses the progressive learning for structural tolerance online sequential extreme learning machine (PSTOS-ELM). PSTOS-ELM can save robust accuracy while updating the new data and the new class data on the online training situation. The robustness accuracy arises from using the householder block exact QR decomposition recursive least squares (HBQRD-RLS) of the PSTOS-ELM. This method is suitable for applications that have data streaming and often have new class data. Our experiment compares the PSTOS-ELM accuracy and accuracy robustness while data is updating with the batch-extreme learning machine (ELM) and structural tolerance online sequential extreme learning machine (STOS-ELM) that both must retrain the data in a new class data case. The experimental results show that PSTOS-ELM has accuracy and robustness comparable to ELM and STOS-ELM while also can update new class data immediately.
Electroencephalography-based brain-computer interface using neural networksTELKOMNIKA JOURNAL
This study aimed to develop a brain-computer interface that can control an electric wheelchair using electroencephalography (EEG) signals. First, we used the Mind Wave Mobile 2 device to capture raw EEG signals from the surface of the scalp. The signals were transformed into the frequency domain using fast Fourier transform (FFT) and filtered to monitor changes in attention and relaxation. Next, we performed time and frequency domain analyses to identify features for five eye gestures: opened, closed, blink per second, double blink, and lookup. The base state was the opened-eyes gesture, and we compared the features of the remaining four action gestures to the base state to identify potential gestures. We then built a multilayer neural network to classify these features into five signals that control the wheelchair’s movement. Finally, we designed an experimental wheelchair system to test the effectiveness of the proposed approach. The results demonstrate that the EEG classification was highly accurate and computationally efficient. Moreover, the average performance of the brain-controlled wheelchair system was over 75% across different individuals, which suggests the feasibility of this approach.
Adaptive segmentation algorithm based on level set model in medical imagingTELKOMNIKA JOURNAL
For image segmentation, level set models are frequently employed. It offer best solution to overcome the main limitations of deformable parametric models. However, the challenge when applying those models in medical images stills deal with removing blurs in image edges which directly affects the edge indicator function, leads to not adaptively segmenting images and causes a wrong analysis of pathologies wich prevents to conclude a correct diagnosis. To overcome such issues, an effective process is suggested by simultaneously modelling and solving systems’ two-dimensional partial differential equations (PDE). The first PDE equation allows restoration using Euler’s equation similar to an anisotropic smoothing based on a regularized Perona and Malik filter that eliminates noise while preserving edge information in accordance with detected contours in the second equation that segments the image based on the first equation solutions. This approach allows developing a new algorithm which overcome the studied model drawbacks. Results of the proposed method give clear segments that can be applied to any application. Experiments on many medical images in particular blurry images with high information losses, demonstrate that the developed approach produces superior segmentation results in terms of quantity and quality compared to other models already presented in previeous works.
Automatic channel selection using shuffled frog leaping algorithm for EEG bas...TELKOMNIKA JOURNAL
Drug addiction is a complex neurobiological disorder that necessitates comprehensive treatment of both the body and mind. It is categorized as a brain disorder due to its impact on the brain. Various methods such as electroencephalography (EEG), functional magnetic resonance imaging (FMRI), and magnetoencephalography (MEG) can capture brain activities and structures. EEG signals provide valuable insights into neurological disorders, including drug addiction. Accurate classification of drug addiction from EEG signals relies on appropriate features and channel selection. Choosing the right EEG channels is essential to reduce computational costs and mitigate the risk of overfitting associated with using all available channels. To address the challenge of optimal channel selection in addiction detection from EEG signals, this work employs the shuffled frog leaping algorithm (SFLA). SFLA facilitates the selection of appropriate channels, leading to improved accuracy. Wavelet features extracted from the selected input channel signals are then analyzed using various machine learning classifiers to detect addiction. Experimental results indicate that after selecting features from the appropriate channels, classification accuracy significantly increased across all classifiers. Particularly, the multi-layer perceptron (MLP) classifier combined with SFLA demonstrated a remarkable accuracy improvement of 15.78% while reducing time complexity.
Supermarket Management System Project Report.pdfKamal Acharya
Supermarket management is a stand-alone J2EE using Eclipse Juno program.
This project contains all the necessary required information about maintaining
the supermarket billing system.
The core idea of this project to minimize the paper work and centralize the
data. Here all the communication is taken in secure manner. That is, in this
application the information will be stored in client itself. For further security the
data base is stored in the back-end oracle and so no intruders can access it.
Applications of artificial Intelligence in Mechanical Engineering.pdfAtif Razi
Historically, mechanical engineering has relied heavily on human expertise and empirical methods to solve complex problems. With the introduction of computer-aided design (CAD) and finite element analysis (FEA), the field took its first steps towards digitization. These tools allowed engineers to simulate and analyze mechanical systems with greater accuracy and efficiency. However, the sheer volume of data generated by modern engineering systems and the increasing complexity of these systems have necessitated more advanced analytical tools, paving the way for AI.
AI offers the capability to process vast amounts of data, identify patterns, and make predictions with a level of speed and accuracy unattainable by traditional methods. This has profound implications for mechanical engineering, enabling more efficient design processes, predictive maintenance strategies, and optimized manufacturing operations. AI-driven tools can learn from historical data, adapt to new information, and continuously improve their performance, making them invaluable in tackling the multifaceted challenges of modern mechanical engineering.
Determination of Equivalent Circuit parameters and performance characteristic...pvpriya2
Includes the testing of induction motor to draw the circle diagram of induction motor with step wise procedure and calculation for the same. Also explains the working and application of Induction generator
A high-Speed Communication System is based on the Design of a Bi-NoC Router, ...DharmaBanothu
The Network on Chip (NoC) has emerged as an effective
solution for intercommunication infrastructure within System on
Chip (SoC) designs, overcoming the limitations of traditional
methods that face significant bottlenecks. However, the complexity
of NoC design presents numerous challenges related to
performance metrics such as scalability, latency, power
consumption, and signal integrity. This project addresses the
issues within the router's memory unit and proposes an enhanced
memory structure. To achieve efficient data transfer, FIFO buffers
are implemented in distributed RAM and virtual channels for
FPGA-based NoC. The project introduces advanced FIFO-based
memory units within the NoC router, assessing their performance
in a Bi-directional NoC (Bi-NoC) configuration. The primary
objective is to reduce the router's workload while enhancing the
FIFO internal structure. To further improve data transfer speed,
a Bi-NoC with a self-configurable intercommunication channel is
suggested. Simulation and synthesis results demonstrate
guaranteed throughput, predictable latency, and equitable
network access, showing significant improvement over previous
designs
Open Channel Flow: fluid flow with a free surfaceIndrajeet sahu
Open Channel Flow: This topic focuses on fluid flow with a free surface, such as in rivers, canals, and drainage ditches. Key concepts include the classification of flow types (steady vs. unsteady, uniform vs. non-uniform), hydraulic radius, flow resistance, Manning's equation, critical flow conditions, and energy and momentum principles. It also covers flow measurement techniques, gradually varied flow analysis, and the design of open channels. Understanding these principles is vital for effective water resource management and engineering applications.
DEEP LEARNING FOR SMART GRID INTRUSION DETECTION: A HYBRID CNN-LSTM-BASED MODELijaia
As digital technology becomes more deeply embedded in power systems, protecting the communication
networks of Smart Grids (SG) has emerged as a critical concern. Distributed Network Protocol 3 (DNP3)
represents a multi-tiered application layer protocol extensively utilized in Supervisory Control and Data
Acquisition (SCADA)-based smart grids to facilitate real-time data gathering and control functionalities.
Robust Intrusion Detection Systems (IDS) are necessary for early threat detection and mitigation because
of the interconnection of these networks, which makes them vulnerable to a variety of cyberattacks. To
solve this issue, this paper develops a hybrid Deep Learning (DL) model specifically designed for intrusion
detection in smart grids. The proposed approach is a combination of the Convolutional Neural Network
(CNN) and the Long-Short-Term Memory algorithms (LSTM). We employed a recent intrusion detection
dataset (DNP3), which focuses on unauthorized commands and Denial of Service (DoS) cyberattacks, to
train and test our model. The results of our experiments show that our CNN-LSTM method is much better
at finding smart grid intrusions than other deep learning algorithms used for classification. In addition,
our proposed approach improves accuracy, precision, recall, and F1 score, achieving a high detection
accuracy rate of 99.50%.
Impartiality as per ISO /IEC 17025:2017 StandardMuhammadJazib15
This document provides basic guidelines for imparitallity requirement of ISO 17025. It defines in detial how it is met and wiudhwdih jdhsjdhwudjwkdbjwkdddddddddddkkkkkkkkkkkkkkkkkkkkkkkwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwioiiiiiiiiiiiii uwwwwwwwwwwwwwwwwhe wiqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq gbbbbbbbbbbbbb owdjjjjjjjjjjjjjjjjjjjj widhi owqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq uwdhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhwqiiiiiiiiiiiiiiiiiiiiiiiiiiiiw0pooooojjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj whhhhhhhhhhh wheeeeeeee wihieiiiiii wihe
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Accident detection system project report.pdfKamal Acharya
The Rapid growth of technology and infrastructure has made our lives easier. The
advent of technology has also increased the traffic hazards and the road accidents take place
frequently which causes huge loss of life and property because of the poor emergency facilities.
Many lives could have been saved if emergency service could get accident information and
reach in time. Our project will provide an optimum solution to this draw back. A piezo electric
sensor can be used as a crash or rollover detector of the vehicle during and after a crash. With
signals from a piezo electric sensor, a severe accident can be recognized. According to this
project when a vehicle meets with an accident immediately piezo electric sensor will detect the
signal or if a car rolls over. Then with the help of GSM module and GPS module, the location
will be sent to the emergency contact. Then after conforming the location necessary action will
be taken. If the person meets with a small accident or if there is no serious threat to anyone’s
life, then the alert message can be terminated by the driver by a switch provided in order to
avoid wasting the valuable time of the medical rescue team.
SENTIMENT ANALYSIS ON PPT AND Project template_.pptx
Design and verification of daisy chain serial peripheral interface using system Verilog and universal verification methodology
1. TELKOMNIKA Telecommunication Computing Electronics and Control
Vol. 21, No. 1, February 2023, pp. 168~177
ISSN: 1693-6930, DOI: 10.12928/TELKOMNIKA.v21i1.24093 168
Journal homepage: http://telkomnika.uad.ac.id
Design and verification of daisy chain serial peripheral interface
using system Verilog and universal verification methodology
Rajesh Thumma, Pilli Prashanth
Department of Electronics and Communication Engineering, Anurag University, Hyderabad, India
Article Info ABSTRACT
Article history:
Received Aug 30, 2021
Revised Nov 12, 2022
Accepted Nov 22, 2022
Serial peripheral interface (SPI) transfers the data between electronic devices
like micro controllers and other peripherals. SPI consists of two control
lines: select signal and clock signal, and two data lines: input and output.
In single master-single slave, the communication is in between master and
slave only which will make the design complex and costly, area will
increase. In regular SPI mode, the number of chip-select lines is increased if
the number of slaves increases. Due to this, the input data received by the
master from the slaves are corrupted at master input slave output (MISO).
The proposed daisy chain method is used to overcome this problem.
The daisy chain method requires only one chip select line at master
compared to the regular SPI mode. When the chip-select line is active low,
all the slaves are active, and the clock is initiated to all the slaves to transfer
the data from the master to the first slave through the master output slave
input (MOSI). In this paper, the daisy-chain SPI is designed and developed
using Verilog. The proposed design is verified using system Verilog (SV)
and universal verification methodology (UVM) in QuestaSim.
Keywords:
Daisy-chain
I2C
SV
UVM
This is an open access article under the CC BY-SA license.
Corresponding Author:
Rajesh Thumma
Department of Electronics and Communication Engineering, Anurag University
Venkatapur, Narapally, Hyderabad, India
Email: rajesh.thumma88@gmail.com
1. INTRODUCTION
System on chip (SoC) architecture requires different components to develop an application. For the
communication and operation between these components, Interfaces are utilized. The communication speed
of the SoC depends on the types of interfaces. The speed rate of the serial peripheral interface (SPI) interface
is 1.1 Mbps. The interfaces are classified into two types, based on the data transmission. They are a serial
interface and a parallel interface.
According to the SoC component’s protocols, serial or parallel communication interfaces are
used [1]-[17]. The motorola semiconductors are the first developers of SPI. The SPI and inter-integrated
circuit (I2C) protocols are used [2] to transfer the data in sequential communication. These two protocols are
appropriate for interchanges between coordinated circuits and with onboard peripherals. The inter-integrated
circuit (I2C) transport utilizes two signals, a sequential clock signal (SCL) and a sequential information
signal SDA, to move information among numerous devices. When contrasted with I2C, SPI utilizes four signals
to move among various devices [3]-[25]. For intra chip communication, SPI is usually used. Both the master and
slave perform the dual role of transmitter and receiver in the SPI. The SPI master slave is designed from the initial
specifications to final system verification by using Verilog hardware description language (HDL) and achieved 71
to 75 megabytes second by implementing in Virtex-5 field programmable gate array (FPGA) [4]-[24]. Various SPI
design techniques are proposed and compared [5] their implementation with respect to chip selects lines.
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However, the number of chip-select lines are increased in the SPI conventional method, while in the daisy
chain technique, the number of chip-select lines is reduced in implementation and easy to design [5]-[21].
The master-slave communication protocol is designed by assigning the priority to each slave by communicating
with the master based on the highest priority slave [6]-[23]. However, the design will consume less power and
utilization sources compared with the other complex design. The high-speed SPI [7] bus is designed in
vertex5 to control and handle two slaves at a time and compared with the existing architectures. However,
accessing multiple devices using a master-slave will be overcome by applying the standard Serial peripheral
interface [8] and single/master communication protocol. The SPI has been designed with five 32-bit registers
using a compatible wishbone interface [9], [10] for serial synchronous communication. In this, 100% of
functional code coverage achieved with up to 64-bits of full-duplex communication is verified.
The interfacing and monitoring of battery-operated electric vehicles [11], [12] is designed using
complementary metal-oxide-semiconductor (CMOS) to transfer the data rate upto 1 Mbps. System Verilog is
the most promising language to reduce the system-on-a-chip (SOC) verification and reusable components of
the complex SOC design. using system Verilog [21], various components are designed, implemented with
object-oriented programming [13], [14] and applied a random technique to find functional coverage.
However, universal verification methodology [15], [17], [18] will reduce the complexity, time, and rewriting
code by accessing the inbuilt classes. Using universal verification methodology (UVM), the SPI master-slave
is designed and verified the 100% functional coverage and code coverage [19], [20].
The SPI is the most used in various interfacing circuits like analog to digital converters (ADCs),
static random access memory (SRAM), sensors, digital to analog converters (DACs), shift registers and
others. SPI is a master, slave-based synchronous, full-duplex interface [5]-[17]. The data is synchronized from
the master or slave at the falling or rising edge of the clock [22]. Both slave and master can send information
(data) simultaneously. This article proposes a daisy chain technique to design an SPI Master-slave interface
using Verilog and verified with system Verilog and UVM. The simulation verification is performed in a model
sim and QuestaSim. The simulation results are obtained in Xilinx Vivado, and both the verification methods
covered 100% of functional coverage, code coverage. In section 2 covers basic information of the SPI theory,
dasiy chain method and operation. Section 3 covers designing a daisy chain SPI using Verilog and is verified
in system Verilog and UVM. Section 4 covers the simulation results of the proposed design Xilinx and
QuestaSim.
2. SERIAL PERIPHERAL INTERFACE
SPI the data transfer between the master and slave devices are depends on the control signals and
data signals of the serial peripheral interface. There are two types of control signals, namely slave select (SS)
or chip select (CS), a clock signal (SCLK). The master output slave input (MOSI), master input slave output
(MISO) are two data signals. When the chip select line is active low its selects, the respected slave and the
data will read or write based on the clock polarity (CPOL) and clock phase (CPHA). The clock signal reads
the data addresses the clock pulses and writes when the chip select signal is high. The data is transferred from
master to slave and slave to the master through MOSI and MISO signals. There are four modes to transfer the
data with clock polarity and clock phase. Table 1 represents the SPI Modes with clock polarity.
Daisy chain SPI based on the number of slaves, the serial peripheral interface is classified into a single
master-single slave, single master-multiple slaves. In single master-single slave, the communication is in
between master and slave only. By using single master-single slave, the area will increase by increasing
the master-slaves, and the design will be complex, making the increase in cost and the area. So, the single
master-single slave is not preferable, and single master-multiple slaves are used in most of cases. The single
master-multiple slaves are further classified into regular SPI method and daisy chain method.
Table 1. SPI modes with CPOL and CPHA
SPI
mode
CPOL CPHA Clock polarity in idle
state
Clock phase used to sample and/or shift the data
0 0 0 Logic low On the rising edge, data was sampled, and on the falling edge, it was shifted
out
1 0 1 Logic low On the lowering edge, data was collected, and on the rising edge, it was
shifted out
2 1 1 Logic high On the lowering edge, data was collected, and on the rising edge, it was
shifted out
3 1 0 Logic high On the rising edge, data was sampled, and on the falling edge, it was shifted
out
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In regular SPI mode, the number of chip-select lines is increased if the number of slaves increases.
Figure 1 shows the regular SPI mode of operation. Due to this, the input data received by the master from the
slaves are corrupted at MISO. Because of this daisy chain method is most preferable to overcome this problem.
The daisy chain method requires only one chip select line at master compared to the regular SPI mode. When
the chip-select line is active low, all the slaves are active, and the clock is initiated to all the slaves to transfer
the data from the master to the first slave through the MOSI.
The first slave’s output is shared with a second slave, the second slave with the third, and the last
slave output is shared with the master; this forms a daisy chain configuration. The primary serial peripheral
interface with a single master multiple slave configuration shows in Figure 1. The proposed daisy chain SPI
configuration shows in Figure 2.
Figure 1. SPI single master-multiple slave configuration [26] Figure 2. A daisy chain SPI: single
master-multiple slave configuration [26]
3. VERIFICATION
The daisy chain SPI is designed with Verilog and verified using the system Verilog and universal
verification methodology. The flow chart of the verification methodology is shown in Figure 3. The Verilog
code is compiled and finds the zero errors which create the elaborated design. After simulation of the design,
the following are observed by taking the register-transfer level (RTL) analysis: RTL schematic, physical
design, elaborated design, and power report. To implement in FPGA, the constraint files are written for
generating a bitstream and dumped in the FPGA board.
Figure 3. Flow chart of the verification methodology [1]
3.1. System Verilog
The daisy chain verification environment is implemented with the system Verilog components. The input
and outputs are instantiated in class_packet. The class_packet is included in the generator and initiated naming as
packet 1. A mailbox is used between the generator and the driver to transfer the generator’s data to the driver. The
generator is included in the driver, and a virtual interface is provided to access the inputs from the interface in a
test. A mailbox driver can transfer the data between the driver to the scoreboard and the receiver to the scoreboard.
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The data received from the driver and receiver will compare on the scoreboard and send to display.
The class_driver is added in the receiver; design under test (DUT) output values are added to packet 2 using a
virtual interface. The packet 1 data from the driver to the scoreboard and the packet 2 data from the receiver
to the scoreboard are compared and included in the coverage. Different random values are added to the inputs
using coverage groups, and coverage is added to the environment.
The functions of generator, driver, receiver, scoreboard and coverage are instantiated in the environment.
The environment is included in the test to perform the test for the environment. A daisy-chain SPI DUT is
developed with a single master and two slaves. A detailed code operation is written for master, slave 1, slave 2
and included in the DUT. Input and outputs are instantiated in the interface to access virtually. The test, DUT
and Interfaces are included in the top block. The top block generates the clock, reset, start signals. The system
Verilog verification environment is shown in Figure 4.
3.2. Universal verification methodology
A rich set of standard rules and guidelines systematically doing the things is called methodology.
It provides the necessary infrastructure to build a robust, reliable and complex verification environment.
It contains a base class library set, which we can use to build our test benches. A methodology should support
coverage driven verification (CDV), transaction based verification (TBV), assertion based verification
(ABV), constrained random testing (CRT). There are various verification methodologies, advanced
verification methodology (AVM) developed by mentor graphics using system C and system Verilog.
Reference verification methodology (RVM) is developed by synopsys using open vera. Open verification
methodology (OVM) developed by mentor graphics using system Verilog. Verification methodology manual
(VMM) by synopsys using system Verilog.
A technical subcommittee of accellera voted to establish the UVM and decided to build this new
standard using the open verification methodology as its foundation. UVM is derived mainly from the OVM.
Advantages of UVM are Common test bench structure and run flow. Reusability through test bench, Time
required to build test bench is very less. It avoids poor coding practices, and Debugging is simple. The
complete UVM verification environment is shown in Figure 5.
To understand the UVM, it is required to understand the verification environment of system Verilog.
The architectures of system Verilog and UVM are similar, but generators are replaced with sequencers and
agents are introduced in UVM. At this moment, a design under test (DUT) is used. To test the functionality
of the DUT, an environment is required to connect the DUT. For this, a sequencer block is used to generate
sequences of bits to transmit into the DUT. Generally, sequencers are responsible for generating data
sequences, and they pass the data to another block called a driver. Why because the sequencer is unaware of
the communication bus. So, the sequencer transmits the data to the driver. Now, the driver starts
communicating with the DUT and by feeding the received data from the sequencer. A monitor block is used
to communicate between the driver and the DUT to evaluate the DUT’s responses. Monitors try to predict the
expected result by sampling the inputs and the outputs of the DUT. They send the prediction and result of the
DUT to the block called the scoreboard. The predicted data are compared and evaluated in the scoreboard.
Figure 4. System Verilog verification architecture [9] Figure 5. Verification environment of universal
verification methodology [3]
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A typical system is formed with all these blocks to perform the verification. The UVM test benches
use the same structure [13]. Figure 5 represents the verification environment of the UVM. A test block is
used generally to control all the blocks of the UVM. The Top block controls all the blocks and sub-blocks of
the test bench. This implies that just by changing a couple of code lines, it is possible to add, eliminate and
abrogate blocks in the test bench and construct various conditions without reworking the entire test. To delineate
the benefit of this verification, need to add a monitor and a driver to the Verification, the environment changes
to the I2C from the serial communication SPI and vice versa.
The serial peripheral interface is widely used due to its advantages. In single master–single slave
SPI communication, there is no difficulty at master input slave output (MISO) to transfer the data compared
to the single master-multiple slave SPI. To solve the above-mentioned problem, different design techniques
are proposed by the different authors. They are interrupt enabled priority-based SPI, parameterization method
using time-sharing multiples technique, high-speed SPI and wishbone compliant SPI. Table 2 represents the
comparison of design techniques and their design or verification languages.
Table 2. Comparison of various SPI design techniques
SPI design techniques Single master-
single slave SPI
Single master-
multiple slaves SPI
Verilog SV SV
coverage
UVM UVM
coverage
Proposed design - Yes Yes Yes Yes Yes Yes
Wishbone compliant SPI [10] Yes - Yes - - - -
High speed SPI [7] - Yes Yes - - - -
Interrupt enabled priority based SPI [6] - Yes Yes - - - -
Parameterization method, time
sharing multiplex (TSM) [8]
- Yes Yes - - - -
SPI master interface using System
Verilog [13]
Yes - - Yes Yes - -
SPI master slave core [9] Yes - Yes Yes Yes - -
SPI master slave core using UVM [3] Yes - Yes - - Yes Yes
Table 2 compares various SPI design techniques designed using the Verilog, system Verilog (SV), and
UVM. All the SPI design techniques are designed with the Verilog, but few of them are designed with advanced
verification methodologies like SV and UVM. SPI master interface using system Verilog [13], SPI master-slave
core [9] are verified using SV and SPI master-slave core using UVM [3] is verified in UVM achieves the 100%
code coverage. The proposed daisy-chain SPI is designed using Verilog HDL, and a verification environment
is implemented using SV and UVM to achieve 100% code coverage.
4. SIMULATION AND RESULTS
The daisy chain Serial Peripheral interface is designed and verified using various VLSI tools like
Xilinx Vivado 2015.2, ModelSim, Xilinx integrated synthesis environment (ISE), QuestaSim. Single
master-two slaves are configured in the daisy-chain. The following three inputs are applied in this design;
they are 𝑑𝑖𝑛 = 10110110, 𝑑𝑖𝑛1 = 11001101, 𝑑𝑖𝑛2 = 10010011 are given to the 𝑚𝑎𝑠𝑡𝑒𝑟, 𝑠𝑙𝑎𝑣𝑒1, 𝑠𝑙𝑎𝑣𝑒2,
respectively. The clock, reset, start and chip select lines control the proposed project’s entire design. The output
ports are instantiated as 𝑑𝑜𝑢𝑡, 𝑑𝑜𝑢𝑡1 and 𝑑𝑜𝑢𝑡2 ports and these ports are used to transfer the data between
the master and slaves shift registers. A Verilog code is written and compiled in Xilinx Vivado 2015.2, and
a detailed RTL code, test_bench, are designed with Verilog HDL. By successfully running the behavioural
simulation with 0 errors and 0 warnings, the following simulation results are shown in Figure 6.
The data outputs 𝑑𝑖𝑛 = 𝑑𝑜𝑢𝑡1, 𝑑𝑖𝑛1 = 𝑑𝑜𝑢𝑡2, and 𝑑𝑖𝑛2 = 𝑑𝑜𝑢𝑡 define that the data flow is
transferred in a daisy-chain fashion. The complete schematic diagram of daisy-chain SPI is obtained by
applying an elaborated design is shown in Figure 7, and Figure 8 shows the elaborated circuit design cells.
After adding the constraints to the xdc file, the design is synthesized. The synthesized device, synthesized
schematic of top-level and circuit level are shown in Figure 9, Figure 10 and Figure 11. After generating the
bitstream, it is dumped into the FPGA board to verify the functionality.
The design is verified in the verification environment using the system Verilog by using QuestaSim
10.0b tool. The inputs from the driver 𝑑_𝑖𝑛: 1, 𝑑_𝑖𝑛_1: 10, 𝑑_𝑖𝑛_2: 11, and outputs from the receiver
𝑑𝑜𝑢𝑡: 11, 𝑑𝑜𝑢𝑡1: 1, 𝑑𝑜𝑢𝑡2: 10 are compared at scoreboard. After comparison of the data received from the
driver and receiver in scoreboard has matched. The daisy chain SPI simulation results of the system Verilog
is shown in Figure 12.
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Figure 6. Simulation results of daisy-chain SPI
Figure 7. Elaborated schematic diagram
Figure 8. Elaborated circuit design
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Figure 9. Synthesized device diagram Figure 10. Synthesized design showing top level schematic
Figure 11: synthesized design schematic showing internal cells
Figure 12: Output results of System Verilog using QuestaSim 10.0b
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Coverage groups are developed for inputs 𝑑_𝑖𝑛, 𝑑_𝑖𝑛_1, 𝑑_𝑖𝑛_2 with random values, and a 100%
functional coverage report is achieved. Figure 13 represents the coverage report of system Verilog using
QuestaSim 10.0b. The design is verified in universal verification methodology by developing a verification
environment.
In this, the inputs from monitor 1, outputs from monitor two are compared at the scoreboard. Here
the inputs are consider as 𝑑_𝑖𝑛 = 182, 𝑑_𝑖𝑛_1 = 138, 𝑑_𝑖𝑛_2 = 7, the outputs from the monitor 2 are
𝑑𝑜𝑢𝑡 = 7, 𝑑𝑜𝑢𝑡1 = 182, 𝑑𝑜𝑢𝑡2 = 138 are matched at the scoreboard according to the daisy-chain method.
Figure 14 represents the simulation and summary report of the UVM using QuestaSim 10.0b.
The covearge A, coverage B, coverage C are developed for the inputs with random values and
achieved a 100% functional coverage and code coverage. Figure 15 represents the coverage report of the
UVM. The functional and code coveage reports are execucted using QuestaSim.
Figure 13: System Verilog coverage reports using QuestaSim 10.0b
Figure 14: Universal verification methodology output results using QuestaSim 10.0b
Figure 15: Coverage reports of UVM using QuestaSim 10.0b
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5. CONCLUSION
In this paper, the daisy-chain SPI is designed using Verilog. The developed design is verified using SV
and UVM. The open-source design suite tool, ModelSim personal edition, was used to write the Verilog code,
which gives the simulation results. The verification environment of the SV and UVM is developed using the
QuestaSim tool. ModelSim and QuestaSim are Mentor Graphics products, which are used to implement the
necessary functional registers. Universal verification methodology verifies the design in the most effective way.
The daisy chain SPI functionality, operation, depiction of registers, pin and signals are discussed. Functional
verification contains the verification platform’s description using system Verilog for the design under the
daisy-chain SPI test. The created verification environment validates the functionality and operation of
configurable daisy-chain SPI. The verification environment developed for daisy-chain SPI protocol was
reusable and using which design can be verified successfully. by using this verification environment, we can
achieve 100% functional and assertion coverage. The designed daisy chain SPI from Verilog is implemented
in FPGA.
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BIOGRAPHIES OF AUTHORS
Rajesh Thumma received his degrees B. Tech in Electronics and Communication
engineering from SKEC, in 2007, M. Tech from the BITS khammam under JNTU Hyderabad,
Telangana, India and PhD in School of Electronics Engineering from the KIIT University,
Bhubaneswar, India in 2018. He has research and teaching experience of more than 13 years.
He is visited University of west Bohemia, Pilsen, Czech Republic and Lublin University of
Technology, Lublin, Poland as a part research work. He is currently working as an Associate
Professor in the Department of Electronics and Communication engineering at Anurag
University, Hyderabad, India since July 2010. His research interest includes low power VLSI,
resonant Power converters and Machine leanring. He can be contacted at email:
rajesh.thumma88@gmail.com.
Pilli Prashanth is a Post graduate (M. Tech) Student in department of Electronics
and Communication with a specialization of VLSI System Design from Anurag university,
Hyderabad, India (2021). He received his B. Tech degree in Electrical and Electronics
Engineering from Indur institute of Engineering and Technology in 2017. His research
interests include low power design VLSI, Functional verification of digital circuits, VLSI
testing, Field Programmable Gate Arrays (FPGA). He can be contacted at email:
prashanthnarsimlu@gmail.com.