The document discusses the simulation evaluation of a CMOS comparator. It includes circuit diagrams showing the configuration of the comparator with inputs, outputs, and component values. The simulation evaluates the propagation delay from low to high (TPLH) and from high to low (TPHL) for the comparator to determine its switching characteristics.

1. CMOSコンパレータ
評価シミュレーション
2013年11月26日
Siam Bee Technologies
Tsuyoshi Horigome

2. Propagation delay [ L to H ] - TPLH
U1
BU7230G
IN
VDD
V1
V2
VSS
IN-
3Vdc
- +
V1 = 1.4
V2 = 1.6
TD = 1u
TR = 0.5n
TF = 0.5n
PW = 10u
PER = 1000u
IN+
OUT
OUT
Vref
1.5Vdc
R1
10k
C1
15p
0
0
0
VRL
3Vdc
0
0

3. tf
U1
BU7230G
IN
VDD
V1
V2
VSS
IN-
3Vdc
- +
OUT
OUT
Vref
1.5Vdc
R1
10k
C1
15p
0
0
0
VRL
3Vdc
0
U1
BU7230G
IN
0
V1 = 1.4
V2 = 1.6
TD = 1u
TR = 0.5n
TF = 0.5n
PW = 10u
PER = 1000u
IN+
VDD
V1
V2
VSS
IN-
3Vdc
- +
V1 = 1.4
V2 = 1.6
TD = 1u
TR = 0.5n
TF = 0.5n
PW = 10u
PER = 1000u
IN+
OUT
OUT
Vref
1.5Vdc
R1
10k
C1
15p
0
0
0
VRL
3Vdc
0
0

4. Propagation delay [ H to L ] - TPHL
U1
BU7230G
IN
IN+
VDD
V1
V2
VSS
IN-
3Vdc
- +
V1 = 1.4
V2 = 1.6
TD = 1u
TR = 0.5n
TF = 0.5n
PW = 10u
PER = 1000u
OUT
OUT
Vref
1.5Vdc
R1
10k
C1
15p
0
0
0
VRL
3Vdc
0
0