The document discusses input/output organization, including topics such as asynchronous data transfers, programmed I/O, interrupts, and direct memory access. It covers CPU modifications, control unit changes, processing of interrupts, and the functioning of I/O processors. The document also details serial communication standards, data transfer modes, and components like UART and RS-232C for synchronous and asynchronous communication.

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Chapter 10
Chapter 10
Input/Output Organization
Input/Output Organization

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Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Chapter Outline
Chapter Outline
• Asynchronous data transfers
Asynchronous data transfers
• Programmed I/O
Programmed I/O
• Interrupts
Interrupts
• Direct Memory Access
Direct Memory Access
• I/O Processors
I/O Processors
• Serial Communication
Serial Communication
• Serial Communication Standards
Serial Communication Standards

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Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Asynchronous Data Transfers
Asynchronous Data Transfers

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Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Source-initiated Data Transfer
Source-initiated Data Transfer

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Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Destination-initiated Data
Destination-initiated Data
Transfer
Transfer

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Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Source-initiated Data Transfer
Source-initiated Data Transfer
with Handshaking
with Handshaking

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Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Destination-initiated Data
Destination-initiated Data
Transfer with Handshaking
Transfer with Handshaking

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Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Programmed I/O
Programmed I/O

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Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Example
Example

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Example
Example

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Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Example
Example

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Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Example
Example

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Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Example
Example

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Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
New Instructions
New Instructions

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Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
New Control Signals
New Control Signals
• IO differentiates I/O and memory
IO differentiates I/O and memory
accesses
accesses
– IO = 1 for I/O access
IO = 1 for I/O access
– IO = 0 for memory access
IO = 0 for memory access

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Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
New States and RTL Code
New States and RTL Code

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Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
CPU Modifications
CPU Modifications
• Modify register section
Modify register section

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Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
CPU Modifications
CPU Modifications
• Modify register section
Modify register section
• Modify ALU
Modify ALU

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Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
CPU Modifications
CPU Modifications
• Modify register section
Modify register section
• Modify ALU
Modify ALU
• Modify control unit (hard-wired)
Modify control unit (hard-wired)

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Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
CPU Modifications
CPU Modifications
• Modify register section
Modify register section
• Modify ALU
Modify ALU
• Modify control unit (hard-wired)
Modify control unit (hard-wired)
• Register and ALU sections unchanged
Register and ALU sections unchanged

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Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
CPU Modifications
CPU Modifications
• Modify register section
Modify register section
• Modify ALU
Modify ALU
• Modify control unit (hard-wired)
Modify control unit (hard-wired)
• Register and ALU sections unchanged
Register and ALU sections unchanged
• One new micro-operation: DR
One new micro-operation: DR 
 Input
Input
Port
Port

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Control Unit Changes
Control Unit Changes

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Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Control Unit Changes - INC
Control Unit Changes - INC
and CLR signals
and CLR signals

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Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Control Unit Changes - INC
Control Unit Changes - INC
and CLR signals
and CLR signals

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Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Control Unit Changes -
Control Unit Changes -
Memory Read Signal
Memory Read Signal
• Memory Read = READ ^
Memory Read = READ ^ IO
IO’
’

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Interrupts
Interrupts
• Polling
Polling

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Interrupts
Interrupts
• IRQ - Interrupt Request
IRQ - Interrupt Request
• IACK - Interrupt Acknowledge
IACK - Interrupt Acknowledge

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Types of Interrupts
Types of Interrupts
• External
External

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Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Types of Interrupts
Types of Interrupts
• External
External
• Internal
Internal

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Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Types of Interrupts
Types of Interrupts
• External
External
• Internal
Internal
• Software
Software

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Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Processing Interrupts
Processing Interrupts
• Do nothing (until the current instruction
Do nothing (until the current instruction
has been executed)
has been executed)

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Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Processing Interrupts
Processing Interrupts
• Do nothing (until the current instruction
Do nothing (until the current instruction
has been executed)
has been executed)
• Get handler address (vectored)
Get handler address (vectored)

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Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Processing Interrupts
Processing Interrupts
• Do nothing (until the current instruction
Do nothing (until the current instruction
has been executed)
has been executed)
• Get handler address (vectored)
Get handler address (vectored)
• Invoke handler routine
Invoke handler routine

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Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Vectored Interrupt Hardware
Vectored Interrupt Hardware

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Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Non-vectored Interrupt
Non-vectored Interrupt
Hardware
Hardware

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Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Multiple Non-vectored
Multiple Non-vectored
Interrupts
Interrupts

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Daisy Chaining
Daisy Chaining

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IACK
IACKin
in and IACK
and IACKout
out

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Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Parallel Priority Interrupts
Parallel Priority Interrupts

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CPU Modifications
CPU Modifications

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CPU Modifications
CPU Modifications

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Interrupt States
Interrupt States

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Direct Memory Access
Direct Memory Access

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DMA Controller
DMA Controller

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DMA Transfer Modes
DMA Transfer Modes
• Block/Burst Mode
Block/Burst Mode

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DMA Transfer Modes
DMA Transfer Modes
• Block/Burst Mode
Block/Burst Mode
• Cycle Stealing Mode
Cycle Stealing Mode

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DMA Transfer Modes
DMA Transfer Modes
• Block/Burst Mode
Block/Burst Mode
• Cycle Stealing Mode
Cycle Stealing Mode
• Transparent Mode
Transparent Mode

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CPU Modifications - Micro-
CPU Modifications - Micro-
operations
operations

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Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
CPU Modifications - Micro-
CPU Modifications - Micro-
operations
operations

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Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
CPU Modifications
CPU Modifications

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Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
CPU Modifications
CPU Modifications

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Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
I/O Processors
I/O Processors

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Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
I/O Processors - operations
I/O Processors - operations
• Block transfer commands
Block transfer commands

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Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
I/O Processors - operations
I/O Processors - operations
• Block transfer commands
Block transfer commands
• ALU operations
ALU operations

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Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
I/O Processors - operations
I/O Processors - operations
• Block transfer commands
Block transfer commands
• ALU operations
ALU operations
• Control commands
Control commands

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Asynchronous Serial
Asynchronous Serial
Communication
Communication
• bps - Bits Per Second (baud rate)
bps - Bits Per Second (baud rate)

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Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Asynchronous Serial
Asynchronous Serial
Communication
Communication
• bps - Bits Per Second (baud rate)
bps - Bits Per Second (baud rate)
• start bit
start bit

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Asynchronous Serial
Asynchronous Serial
Communication
Communication
• bps - Bits Per Second (baud rate)
bps - Bits Per Second (baud rate)
• start bit
start bit
• parity bit
parity bit

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Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Asynchronous Serial
Asynchronous Serial
Communication
Communication
• bps - Bits Per Second (baud rate)
bps - Bits Per Second (baud rate)
• start bit
start bit
• parity bit
parity bit
• stop bit(s)
stop bit(s)

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Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Asynchronous Serial
Asynchronous Serial
Communication
Communication
• bps - Bits Per Second (baud rate)
bps - Bits Per Second (baud rate)
• start bit
start bit
• parity bit
parity bit
• stop bit(s)
stop bit(s)
• bit time
bit time

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Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Asynchronous Serial
Asynchronous Serial
Communication
Communication

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Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Synchronous Serial
Synchronous Serial
Communication - HDLC
Communication - HDLC

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Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Universal Asynchronous
Universal Asynchronous
Receiver/Transmitters
Receiver/Transmitters

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UART Internal Configuration
UART Internal Configuration

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Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
• Request To Send
Request To Send
• Clear To Send
Clear To Send
• Transmission Data
Transmission Data
• Data Terminal Ready
Data Terminal Ready
• Data Set Ready
Data Set Ready
• Received Data
Received Data
• Data Carrier Detect
Data Carrier Detect
• Ring Indicator
Ring Indicator
• Ground
Ground
RS 232C Standard - Signals
RS 232C Standard - Signals

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Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
RS 232C Standard -
RS 232C Standard -
Connection
Connection
• Use RTS, CTS, DTR, and DSR to verify
Use RTS, CTS, DTR, and DSR to verify
that both devices are active
that both devices are active

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Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
RS 232C Standard -
RS 232C Standard -
Connection
Connection
• Use RTS, CTS, DTR, and DSR to verify
Use RTS, CTS, DTR, and DSR to verify
that both devices are active
that both devices are active
• Use RI to indicate call status
Use RI to indicate call status

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Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
RS 232C Standard -
RS 232C Standard -
Connection
Connection
• Use RTS, CTS, DTR, and DSR to verify
Use RTS, CTS, DTR, and DSR to verify
that both devices are active
that both devices are active
• Use RI to indicate call status
Use RI to indicate call status
• Use DCD to establish connectivity
Use DCD to establish connectivity

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Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
RS 232C Standard -
RS 232C Standard -
Connection
Connection
• Use RTS, CTS, DTR, and DSR to verify
Use RTS, CTS, DTR, and DSR to verify
that both devices are active
that both devices are active
• Use RI to indicate call status
Use RI to indicate call status
• Use DCD to establish connectivity
Use DCD to establish connectivity
• Use TD and RD to transfer data, and
Use TD and RD to transfer data, and
RTS and CTS to coordinate transfers
RTS and CTS to coordinate transfers

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Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
RS 422 Standard - Signals
RS 422 Standard - Signals

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Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Universal Serial Bus Standard
Universal Serial Bus Standard
• Connects one port to several devices
Connects one port to several devices

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Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Universal Serial Bus Standard
Universal Serial Bus Standard
• Connects one port to several devices
Connects one port to several devices
• Transfers data in packets
Transfers data in packets
– Token packets
Token packets
– Data packets
Data packets
– Handshake packets
Handshake packets
– Special Packets
Special Packets

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Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
USB Packet Formats
USB Packet Formats

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Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Summary
Summary
• Asynchronous data transfers
Asynchronous data transfers
• Programmed I/O
Programmed I/O
• Interrupts
Interrupts
• Direct Memory Access
Direct Memory Access
• I/O Processors
I/O Processors
• Serial Communication
Serial Communication
• Serial Communication Standards
Serial Communication Standards