Chapter10.ppt

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This document discusses various methods of input/output organization in computer systems. It covers asynchronous and programmed input/output, interrupts and direct memory access for efficient data transfer, as well as serial communication standards like RS-232 and USB. Specific topics include asynchronous and synchronous serial communication, programmed I/O using new CPU instructions, interrupt processing with vectored and prioritized interrupts, and the use of DMA controllers and I/O processors to offload I/O processing from the CPU.

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Chapter 10
Input/Output Organization

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Chapter Outline
• Asynchronous data transfers
• Programmed I/O
• Interrupts
• Direct Memory Access
• I/O Processors
• Serial Communication
• Serial Communication Standards

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Asynchronous Data Transfers

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Source-initiated Data Transfer

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Destination-initiated Data
Transfer

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Source-initiated Data Transfer
with Handshaking

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Destination-initiated Data
Transfer with Handshaking

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Programmed I/O

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Example

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New Instructions

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New Control Signals
• IO differentiates I/O and memory
accesses
– IO = 1 for I/O access
– IO = 0 for memory access

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New States and RTL Code

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CPU Modifications
• Modify register section

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CPU Modifications
• Modify register section
• Modify ALU

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CPU Modifications
• Modify register section
• Modify ALU
• Modify control unit (hard-wired)

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Control Unit Changes

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Control Unit Changes - INC
and CLR signals

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Control Unit Changes -
Memory Read Signal
• Memory Read = READ ^ IO’

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Interrupts
• Polling

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Interrupts
• IRQ - Interrupt Request
• IACK - Interrupt Acknowledge

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Types of Interrupts
• External

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Types of Interrupts
• External
• Internal

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Types of Interrupts
• External
• Internal
• Software

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Processing Interrupts
• Do nothing (until the current instruction
has been executed)

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Vectored Interrupt Hardware

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Non-vectored Interrupt
Hardware

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Multiple Non-vectored
Interrupts

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Daisy Chaining

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IACKin and IACKout

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Parallel Priority Interrupts

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CPU Modifications

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Interrupt States

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Direct Memory Access

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DMA Controller

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DMA Transfer Modes
• Block/Burst Mode

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DMA Transfer Modes
• Block/Burst Mode
• Cycle Stealing Mode

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DMA Transfer Modes
• Block/Burst Mode
• Cycle Stealing Mode
• Transparent Mode

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CPU Modifications - Micro-
operations

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I/O Processors

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I/O Processors - operations
• Block transfer commands

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I/O Processors - operations
• Block transfer commands
• ALU operations

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I/O Processors - operations
• Block transfer commands
• ALU operations
• Control commands

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Asynchronous Serial
Communication
• bps - Bits Per Second (baud rate)

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Asynchronous Serial
Communication
• bps - Bits Per Second (baud rate)
• start bit

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Asynchronous Serial
Communication
• bps - Bits Per Second (baud rate)
• start bit
• parity bit

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Asynchronous Serial
Communication

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Synchronous Serial
Communication - HDLC

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Universal Asynchronous
Receiver/Transmitters

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UART Internal Configuration

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• Request To Send
• Clear To Send
• Transmission Data
• Data Terminal Ready
• Data Set Ready
• Received Data
• Data Carrier Detect
• Ring Indicator
• Ground
RS 232C Standard - Signals

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RS 232C Standard -
Connection
• Use RTS, CTS, DTR, and DSR to verify
that both devices are active

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RS 422 Standard - Signals

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Universal Serial Bus Standard
• Connects one port to several devices

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Universal Serial Bus Standard
• Connects one port to several devices
• Transfers data in packets
– Token packets
– Data packets
– Handshake packets
– Special Packets

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USB Packet Formats

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Summary
• Asynchronous data transfers
• Programmed I/O
• Interrupts
• Direct Memory Access
• I/O Processors
• Serial Communication
• Serial Communication Standards

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Chapter10.ppt

2. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Chapter Outline • Asynchronous data transfers • Programmed I/O • Interrupts • Direct Memory Access • I/O Processors • Serial Communication • Serial Communication Standards

21. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 CPU Modifications • Modify register section • Modify ALU • Modify control unit (hard-wired) • Register and ALU sections unchanged • One new micro-operation: DR  Input Port

33. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Processing Interrupts • Do nothing (until the current instruction has been executed) • Get handler address (vectored) • Invoke handler routine

65. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 • Request To Send • Clear To Send • Transmission Data • Data Terminal Ready • Data Set Ready • Received Data • Data Carrier Detect • Ring Indicator • Ground RS 232C Standard - Signals

68. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 RS 232C Standard - Connection • Use RTS, CTS, DTR, and DSR to verify that both devices are active • Use RI to indicate call status • Use DCD to establish connectivity

69. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 RS 232C Standard - Connection • Use RTS, CTS, DTR, and DSR to verify that both devices are active • Use RI to indicate call status • Use DCD to establish connectivity • Use TD and RD to transfer data, and RTS and CTS to coordinate transfers

72. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Universal Serial Bus Standard • Connects one port to several devices • Transfers data in packets – Token packets – Data packets – Handshake packets – Special Packets

74. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Summary • Asynchronous data transfers • Programmed I/O • Interrupts • Direct Memory Access • I/O Processors • Serial Communication • Serial Communication Standards

Chapter10.ppt

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Chapter10.ppt