The document provides an overview of computer arithmetic, covering fundamental operations like addition, subtraction, multiplication, and division, as well as algorithms for fixed-point and floating-point arithmetic. It details the hardware implementations needed for these operations and the representation of numbers in various forms including signed-magnitude and signed-2's complement. Additionally, it discusses the complexities involved in floating-point operations and includes specifics on hardware algorithms for arithmetic operations using binary-coded decimal (BCD) systems.

1. Computer
Arithmetic
BY ASST. PROF. SHWETA MAURYA

2. Topics To be Covered
 Introduction
 Addition and Subtraction
 Multiplication Algorithms
 Division Algorithms
 Floating-point Arithmetic operations
 Decimal Arithmetic Unit
 Decimal Arithmetic operations

3. Arithmetic Operation
 Arithmetic instructions in digital computers manipulate data to produce results necessary for the solutions
of computational problems.
 4 basic arithmetic operations:
-Addition
-Subtraction
- Multiplication
- Division
 Addition,subtraction,multiplication,and division for the following types of data:
Fixed point binary data in signed-magnitude representation

Fixed point binary data in signed-2’s compliment representation

Floating point binary data

Binary-coded decimal(BCD) data


4. Addition and subtraction
 The addition and subtraction algorithm for data
represented in ::
1. signed magnitude
2.signed-2’s complement :
 It is important to realize that the adopted
representation for negative numbers refers to the
representation of numbers in the register before and
after the execution of the arithmetic operations

5. Addition and Subtraction
with Signed-magnitude Data:
 We designated the magnitude of the two numbers by A
and B. when the signed numbers are added or
subtracted.
 There are 8 different conditions to consider, depending
on the sign of the numbers and the operation
performed.

6.  The last column is needed to prevent negative zero. In other
words ,when two equal numbers are subtracted, the result should
be +0 not -0.
 Algorithm:
>When the signs of A and B are identical , add the two magnitude
and attach the sign of A to the result.
>When the sign of A and B are different ,compare the
magnitudes.
and attached the sign of maximum one.

7. Hardware implementation
 To implement the two arithmetic operations with hardware, it is first
necessary that the two numbers be stored in registers.
 Let A and B be two registers that hold the magnitude of the numbers.
 As and Bs be two flip flops that hold the corresponding signs.
 The results of the operation may be transferred into A and As .

8. Hardware implementation
– Cont..

9. Hardware Algorithm Flowchart

10. Addition and Subtraction with
signed2’s complement data
 The left most bit of binary number represents the sign bit;
::0 for positive
:: 1 for negative.
 If the sign bit is 1, the entire the entire number is represented in 2’s
compliment form.
 The addition of two numbers in signed-2’s complement form consists of
adding the number with the sign bits treated the same as the other bits of the
number .A carry out of the sign bit position is discarded .
 The subtraction consists of first taking the 2’s compliment of the subtrahend
and then adding it to the minuend.
 When two numbers of n digits each are added and the sum occupies n+1
Digits, we say that an overflow occurred.
 When the two carries are applied to an exclusive-OR gate, the overflow is
detected when the output of the gate is equal to 1.

11. Hardware Implementation

12. Hardware Algorithm- Flowchart

13. Multiplication Algoerithm

14. Hardware Implementation for Signed
Magnitude Data
 Adder for the summation of only two binary numbers and successively
accumulate the partial products in a register.
 Instead of shifting the multiplicand to the left , the partial product is shifted to the
right
 The hardware for multiplication consists of the equipment shown in fig. plus
two are more registers.
 These registers are together with registers A and B..
 The multiplier stored in the Q register and its sign in Qs .
 The sequence counter SC is initially set to a number equal to the number of bits
in the multiplier. The counter is decremented by 1 after forming each partial
product.
 The sum of A and B forms a partial product which is transferred to the EA
register.
 The shift will be denoted by the statement “ shr EAQ “to designate the
right shift depicted . The least significant bit of A is shifted into the most
significant position of Q.

15. Hardware Implementation
 Below is the Hardware organization :

16. Hardware Algorithem
 Initially the multiplicand is in B and the multiplier in Q there corresponding
signs are in Bs and Qs .,respectively.
 Register A and E are cleared and the sequence counter SG is set to a
number equal to the number of bits of the multiplier.
 After the initialization , the low order bit of the multiplier is in Qn is tested .
- if it is 1, :::: >the multiplicand In B is added to the present partial product in
A .
- If it is 0, nothing is done .
 Register EAQ shifted once to the right to form the new partial product.
 The process stops when SC=0.
 Note that the partial product formed in A is shifted into Q one bit at a time
and eventually replaces multiplier.
 The final product is available in both A and Q,with A holding the most
significant bits and Q holding the least significant bits.

19. Division Algorithm
 Division of two fixed-point binary numbers in signed
magnitude
representation is done with paper and pencil by a process of
successive compare ,shift ,and subtract operations ..

20. Example of binary division
with digital hardware
 Instead of shifting the divisor to the right, the dividend or partial remainder, is
shifted to the left, thus leaving the two numbers in the required relative
position, subtraction may be achieved by adding A to the 2’s compliment
of B.
 EAQ is shifted to the left with 0 instead of Qn and the previous value of E lost.
 The divisor is stored in the B register and the double length dividend is stored
in register A and Q The information about relative magnitude is available in
E. if E=1,it signifies that A ≥B. A quotient bit 1 is inserted into Qn and the
partial remainder is shifted left to repeat the process. If E=0, it signifies that
A<B
so the quotient in Qn remains a 0.
 The sign of the remainder is the same as the sign of the dividend .

22. Divide overflow
 This occurs as operation is implemented as Hardware .
 Register length is finite and can not hold a number which exceed the length of register.
 A divide-overflow condition occurs when high order half bits of dividend >= divisor.
 Over flow condition is usually detected when a special flip-flop is set .
Which will call it a divide overflow flip-flop and label it DVF
 Handling ::
 Can be handled in variety of ways :
- In some computers it is the responsibility of the programmers to check if DVF is set
after each divide instruction
-The occurrence of a divide overflow stopped the computer and this condition was
referred to as a DIVIDE STOP.
-
- The best way to avoid a divide overflow is to use floating point data

23. Hardware Allgorithm:

24. Hardware Allgorithm:

25. Hardware Algorithm:

26. Floating Point Arithmetic
Operations
 2 parts – Mantissa->signed fixed point number
 – exponent->the position of the decimal(binary)
point
 – Eg:6132.739 – +06132739->fraction – 4->
exponent – Similar to +0.6132739*10^+4 • General
form M*r^e
 – M->mantissa
 – r->radix
 – E->exponent

27.  For binary fp; –
 Similar to fp decimal point, but uses radix 2 – Eg:
+1001.11
 – 01001110(mantssa)
 – 000100(exponent)

28. Normalization
 A floating point no. is said to be normalized if the
most significant digit of the mantissa is nonzero. •
 Eg:350->normalized
 – 00035-> not normalized.
 – Can be normalized by shifting it 3 positions to
the left and discarding the leading zeros.(10^3)
 Zero cannot be normalized bcoz it doesnot have
a nonzero digit.
 – Denoted by all zeros at mantissa and
exponenet.

29.  Operations on fp numbers requires complex
hardware and takes more time.
 • Addition or subtraction requires:
 – Alignment of radix point(exponents must be
equal).
 – Done by shifting mantissa and adjust exponent
accordingly.
 – Eg: 0.5372400*10^2+
 0.1580000*10^-1

30.  Either shift the 1st no 3 positions to the left or shift
the 2nd by 3 position to the right. •
 2 nd method is more preferable.
 – So, .5272400*10^2+
 .0001580*10^2
 .5373980 *10^2
 Normalized addition will cause an overflow and
can be corrected by shifting the sum once to the
right and incrementing the exponent.

31.  Underflow
 – Floating point number has a 0 in the MSB of the
mantissa.
 – Shift the mantissa to the left and decrement the
exponent(normalization)
 • Multiplication and division doesnot require
alignment.
 – Result(multiply mantissa and add the exponent for
multiplication)
 – Divide the mantissa and subtract the exponent for
division

32.  • The operation performed with exponent are: –
Compare &increment(align mantissa) – Add
&subtract(multiplication and division) –
Decrement(nomalization) • Exponent
representation – Signed magnitude – Signed 2’s
complement – Signed 1’s complement – Biased
exponent

33. Register Configuration
 The same registers & adders are in the case of
fixed point arithmetic are used for processing
mantissa. • Differs the way in which exponents are
handled

34.  There are three registers, BR, AC,and QR.
Each register is subdivided into two parts.
The mantissa part has same upper case
letters, the exponent part uses the corresponding
lower case letters.

A parallel adder adds the two mantissas
and transfers the sum into A and the carry
into E. A separate parallel adder is used
for the exponents. Since the exponents
are biased.

36.  BR,AC,QR(divided into 2 parts).
• Mantissa is stored in B,A and Q registers
• Exponent in b,a,q registers.
– Mantissa in signed magnitude in A and sign in As
and MSB in A1.
– Biased exponent in a.
– A1->1 if the no. Has to be normalized
– Similarly for other registers

37.  2Parallel adders
– 1 ,Adds two mantissas and sum stores in A,Carry
to E.
– 2nd adds the exponents(don’t have distinct sign
bit,but taken as +ve).
• Exponent overflow is neglected.
Exponents are connected to comparator that
provides 3 binary outputs to indicate their
relative magnitude.

38.  The number in the mantissa is taken as a
fraction, so binary point resides to the left of
the magnitude part.
• Numbers are normalized both during initial
and after the operation.

40. A floating point operation may
produce:

41. Addition and Subtraction
 During addition and subtraction , the two floating point operands are in AC
and BR. The sum of difference is formed in the AC . The algorithm can be
divided into four consecutive parts :
 1. Check for zeros.
• 2. Align the mantissas.
• 3. Add or subtract the mantissas.
• 4. Normalize the result.

44. Multiplication
 The multiplication of two floating point numbers requires that we
multiply the mantissas and add the exponents
 The multiplication of the mantissa is performed same as fixed point to
provide a double precision product.
 The multiplication algorithm can be subdivided into four parts :-
1. Check for zeros.
2. Add the exponents.
3. Multiply the mantissa.
4. Normalize the product.

48. Floating Point - Division
 Floating point division requires that the exponents be
subtracted
and the mantissa divided.
 The mantissa division is done as in fixed point except that the
dividend has a single precision mantissa that is placed in the
AC.
 The division algorithm can be divided into five parts..
1. Check for zeros.
2. Initialize registers and evaluate the sign.
3. Align the dividend
4. Subtract the exponents.
5. Divide the mantissa.

52. BCD Adder
 Also Known as 8421 digit.
 A 4-bit binary adder.
 Adds two 4-bit digits having a BCD.
 Resulting format 4-bit output digit.
 Sum exceeding decimal value of 9, a carry’s generated.
 A 4-bit BCD code’s used to represent 0 to 9 digits.
 Adding BCD numbers using BCD addition.
 Adding 6 with the sum while exceeding 9 and generating a carry.

54. BCD Adder [ > 9]

56. BCD Adder circuit

57. BCD Adder
 Youtube link ::
 https://www.youtube.com/watch?v=9O7OJi7RCLQ
 Applications in Decimal Number Display.
 Systematic running of counters.
 Organized digital clocks.