Branch prediction Notes. In computer architecture, a branch predictor is a digital circuit that tries to guess which way a branch (e.g. an if-then-else structure) will go before this is known for sure.
Artificial Intelligence (AI) and Data Science (DS) are shaping the future of aviation and space industries. For example, using AI and DS in prognostics and health management can make a paradigm shift in system reliability and availability as well as improve mission safety. We will talk about how AI and DS improve complex engineering systems’ prognostics and change the maintenance strategy from fail and fix to predict and prevent. In addition, we will understand how data-driven prognostics can be seen as a forecast application from AI and DS perspective. We will discover how AI and DS are involved in remaining useful life estimation of complex engineering systems. This enables safe deep space exploration and developing highly reliable systems without having to design systems with many redundant components.
Optimization of automatic voltage regulator by proportional integral derivati...eSAT Journals
Abstract
This paper is basically based on the optimization of working of Automatic voltage regulator by the proportional Intigral
derivative controller. In this analysis, optimization is done by very novel concept Particle Swarm Optimization and simulated
using MATLAB Simulink software. The primary reason for a programmed voltage controller framework is to keep the voltage
extent of a synchronous generator at a predetermined level the generator excitation framework keeps up the generator voltage
and controls the reactive power stream.
IndexTerms:AutomaticVoltageRegulator,MATLAB
Operating system 07 batch processing operating systemVaibhav Khanna
The main function of a batch processing system is to automatically keep executing one job to the next job in the batch.
The main idea behind a batch processing system is to reduce the interference of the operator during the processing or execution of jobs by the computer.
All functions of a batch processing system are carried out by the batch monitor. The batch monitor permanently resides in the low end of the main store.
The current jobs out of the whole batch are executed in the remaining storage area.
In other words, a batch monitor is responsible for controlling all the environment of the system operation.
The batch monitor accepts batch initiation commands from the operator, processes a job, performs the job of job termination and batch termination.
This document discusses machine learning techniques for predicting the strength of building components. It begins with an overview of beam-column joints and issues with their failure during earthquakes. It then discusses the behavior of beam-column joints during seismic activity. Next, it provides an introduction to machine learning, describing supervised learning algorithms like linear regression, logistic regression, support vector machines, decision trees, random forest, and artificial neural networks. It explains key concepts for each algorithm like their definitions, applications, and working principles. The document aims to explore using machine learning to develop holistic numerical models for analyzing beam-column joint strength.
This document discusses learning components and types of learning in artificial intelligence. It will differentiate between supervised, unsupervised and reinforcement learning, and implement applications of each. Students will learn and implement perceptron and neural networks, as well as ensemble learning techniques like bagging and boosting. The objective is to discuss learning components, types of learning in AI, and implement algorithms for supervised, unsupervised and reinforcement learning.
Low-power Innovative techniques for Wearable ComputingOmar Elshal
A presentation i did for the Ubiquitous and Wearable Computing seminar during my senior year in university.
The presentation introduces many research papers on the field then discusses one of them thoroughly.
Branch prediction is necessary to reduce penalties from branches in modern deep pipelines. It predicts the direction (taken or not taken) and target of branches. Common techniques include bimodal prediction using saturating counters and two-level prediction using branch history tables and pattern history tables. Real processors use hybrid predictors combining different techniques. Mispredictions require flushing the pipeline and incur a performance penalty.
Artificial Intelligence (AI) and Data Science (DS) are shaping the future of aviation and space industries. For example, using AI and DS in prognostics and health management can make a paradigm shift in system reliability and availability as well as improve mission safety. We will talk about how AI and DS improve complex engineering systems’ prognostics and change the maintenance strategy from fail and fix to predict and prevent. In addition, we will understand how data-driven prognostics can be seen as a forecast application from AI and DS perspective. We will discover how AI and DS are involved in remaining useful life estimation of complex engineering systems. This enables safe deep space exploration and developing highly reliable systems without having to design systems with many redundant components.
Optimization of automatic voltage regulator by proportional integral derivati...eSAT Journals
Abstract
This paper is basically based on the optimization of working of Automatic voltage regulator by the proportional Intigral
derivative controller. In this analysis, optimization is done by very novel concept Particle Swarm Optimization and simulated
using MATLAB Simulink software. The primary reason for a programmed voltage controller framework is to keep the voltage
extent of a synchronous generator at a predetermined level the generator excitation framework keeps up the generator voltage
and controls the reactive power stream.
IndexTerms:AutomaticVoltageRegulator,MATLAB
Operating system 07 batch processing operating systemVaibhav Khanna
The main function of a batch processing system is to automatically keep executing one job to the next job in the batch.
The main idea behind a batch processing system is to reduce the interference of the operator during the processing or execution of jobs by the computer.
All functions of a batch processing system are carried out by the batch monitor. The batch monitor permanently resides in the low end of the main store.
The current jobs out of the whole batch are executed in the remaining storage area.
In other words, a batch monitor is responsible for controlling all the environment of the system operation.
The batch monitor accepts batch initiation commands from the operator, processes a job, performs the job of job termination and batch termination.
This document discusses machine learning techniques for predicting the strength of building components. It begins with an overview of beam-column joints and issues with their failure during earthquakes. It then discusses the behavior of beam-column joints during seismic activity. Next, it provides an introduction to machine learning, describing supervised learning algorithms like linear regression, logistic regression, support vector machines, decision trees, random forest, and artificial neural networks. It explains key concepts for each algorithm like their definitions, applications, and working principles. The document aims to explore using machine learning to develop holistic numerical models for analyzing beam-column joint strength.
This document discusses learning components and types of learning in artificial intelligence. It will differentiate between supervised, unsupervised and reinforcement learning, and implement applications of each. Students will learn and implement perceptron and neural networks, as well as ensemble learning techniques like bagging and boosting. The objective is to discuss learning components, types of learning in AI, and implement algorithms for supervised, unsupervised and reinforcement learning.
Low-power Innovative techniques for Wearable ComputingOmar Elshal
A presentation i did for the Ubiquitous and Wearable Computing seminar during my senior year in university.
The presentation introduces many research papers on the field then discusses one of them thoroughly.
Branch prediction is necessary to reduce penalties from branches in modern deep pipelines. It predicts the direction (taken or not taken) and target of branches. Common techniques include bimodal prediction using saturating counters and two-level prediction using branch history tables and pattern history tables. Real processors use hybrid predictors combining different techniques. Mispredictions require flushing the pipeline and incur a performance penalty.
This document proposes an efficient memory design for error tolerant applications using built-in self-repair (BISR). It uses built-in self-test (BIST) to test memories for faults and sends that information to built-in redundancy analysis (BIRA) to determine repair solutions. Memories are serially tested and repaired to reduce testing time and switching activities. The proposed approach uses multiple single input change (MSIC) vectors to test memories concurrently, reducing area and performance overhead compared to traditional BISR systems.
AN EFFICIENT MEMORY DESIGN FOR ERROR TOLERANT APPLICATION1 (1).pdfKeshvan Dhanapal
This document describes an efficient memory design for error tolerant applications. It aims to test memories, detect faults, and improve repair ability. The design uses a built-in self-repair (BISR) scheme combining built-in self-test (BIST) and built-in redundancy analysis (BIRA). BIST tests memories and sends fault information to BIRA. BIRA finds repair solutions for faulty memories. The design reduces testing time and switching activities while improving repairability.
AN EFFICIENT MEMORY DESIGN FOR ERROR TOLERANT APPLICATION1.pptxKeshvan Dhanapal
This document proposes an efficient memory design for error tolerant applications using built-in self-repair (BISR). It uses built-in self-test (BIST) to test memories for faults and sends that information to built-in redundancy analysis (BIRA) to determine repair solutions. Memories are serially tested and repaired to reduce testing time and switching activities. The proposed approach uses multiple single input change patterns to test memories concurrently before repairing faulty ones serially based on size. This achieves better performance and resource utilization than existing BIST, DMR, and TMR schemes.
Design of management dashboard (smart electric grids)Jatin Pherwani
Presentation for my Final year Design Project at Dept. of Design IIT Guwahati. The aim of this project is to allow efficient management of smart electricity grids in rural as well as urban areas primarily by catering the needs of engineers and technicians involved in monitoring and controlling the grid parameters for a huge and self sustaining electricity network
This document discusses different types of instruction hazards in pipelines including structural hazards, data hazards, and control hazards. It focuses on control hazards caused by branches, where the destination of the branch is unknown until it is evaluated. To resolve this, it discusses different branch prediction strategies like stalling, deciding the branch in the ID stage, delayed branches using compiler reordering, and branch prediction. Branch prediction involves using a branch history table (BHT) to predict if the branch will be taken or not based on its past behavior. The document provides statistics on typical branch behavior and analyzes the accuracy of 1-bit branch prediction. It also discusses scheduling instructions into the delay slot of delayed branches.
Embedded Systems (18EC62) – Embedded System Design Concepts (Module 4)Shrishail Bhat
This document discusses the characteristics and quality attributes of embedded systems. It describes several key characteristics of embedded systems, including being application specific, reactive and operating in real time, able to function in harsh environments, potentially distributed across multiple components, and having constraints on size, weight and power consumption. The document also distinguishes between operational quality attributes, like response time, throughput, reliability and maintainability, and non-operational attributes such as testability, evolvability and portability. Maintainability and reliability are discussed in detail through examples of mean time between failures and mean time to repair calculations.
The document discusses using machine learning techniques to predict the strength of building components, specifically beam-column joints. It begins with definitions of beam-column joints and issues associated with them, such as failures during earthquakes. Then it provides an overview of machine learning, including common algorithms like linear regression, logistic regression, decision trees, and artificial neural networks. The remainder of the document discusses using an artificial neural network approach specifically to model and predict the shear strength of exterior reinforced concrete beam-column joints based on experimental data. Key parameters that would be inputs to the neural network model are identified.
This document describes an early fault detection system called Faultdec. It uses a probabilistic model and state observer to monitor the internal state of a system, like a cricket ball stitching machine, and detect potential faults before they occur. The system works by discretizing the internal states into normal, degraded, and failed states. It then maps the state densities to a probability of fault. Faultdec uses hardware like an FPGA and concurrent design to rapidly monitor inputs and detect degraded states. When a degraded state is detected, an alarm is issued to allow corrective action to be taken before an actual failure occurs. The goal is to provide real-time fault awareness and avoidance for critical systems.
The transformer is the most important equipment in the transmission and distribution system.
This expert system is the principle of condition based maintenance strategy. The system consider discrete diagnostical results.
For the comparison we need to consider some other parameters what do not indicate the status of the insulation but it has influence for that.
In the research work, the expert system tested by real data from the Hungarian distribution system. The source of the testing data is 13 HV/MV distribution transformers in Hungary
Allocation of processors to processes in Distributed Systems. Strategies or algorithms for processor allocation. Design and Implementation Issues of Strategies.
The document provides guidance on using random sequential sampling with Excel and Audit Commander software. It describes sampling population data in Excel worksheets and selecting initial samples of 150 observations for variable and attribute sampling. The samples are sorted by random numbers and values from the actual column are copied over to the audited value column.
CS304PC:Computer Organization and Architecture Session 15 program control.pptxAsst.prof M.Gokilavani
This document summarizes the topics covered in session 15 of the CS304PC course on computer organization and architecture. It discusses general register organization, instruction formats, addressing modes, data transfer and manipulation, and program control. Specifically, it describes status registers, condition codes, and how program control instructions like branches, jumps, skips, calls and returns use condition codes to control program flow. It also covers program interrupts, defining external, internal, and software interrupts and providing examples of each type.
A Review of Different Types of Schedulers Used In Energy ManagementIRJET Journal
This document reviews different types of schedulers used for energy management in embedded systems. It discusses dynamic voltage and frequency scaling (DVFS) which aims to reduce energy consumption by varying CPU frequency and voltage dynamically. Real-time DVFS ensures quality of service by developing task schedules while reducing energy via DVFS. The paper surveys various DVFS scheduling algorithms that utilize CPU idle time to change frequency/voltage or use other techniques to meet power requirements. These algorithms can be offline, using worst-case execution times to pre-schedule all tasks, or online, making decisions in real-time based on past task executions to improve scheduling.
Models of Operational research, Advantages & disadvantages of Operational res...Sunny Mervyne Baa
This document discusses operational research models and their advantages and disadvantages. It describes several common OR models including linear programming, network flow programming, integer programming, nonlinear programming, dynamic programming, stochastic programming, combinatorial optimization, stochastic processes, discrete time Markov chains, continuous time Markov chains, queuing, and simulation. It notes advantages of OR in developing better systems, control, and decisions. However, it also lists limitations such as dependence on computers, inability to quantify all factors, distance between managers and researchers, costs of money and time, and challenges implementing OR solutions.
Based on visual basic differential workbench system design and implementation...eSAT Journals
Abstract
In this paper, we take the equipment precision differential bench which homemade by Shanghai University of Engineering and Technology for the study, and use the Visual Basic for precision motion system of differential table design and secondary development. Through experiments, we can get the change in position under different sports differential table, through the measurement of data analysis, we can get in the form of differential motion error table for further compensation error of the foundation.
Keywords: Visual Basic, Differential, The error analysis
This document discusses transaction processing in database management systems (DBMS). It describes the ACID properties that transactions must satisfy - atomicity, consistency, isolation, and durability. An example of a fund transfer transaction is provided to illustrate these properties. Concurrency control is discussed as a mechanism for allowing concurrent transactions while maintaining isolation. The concepts of schedules, conflicting instructions, conflict serializability, and view serializability are introduced for evaluating the correctness of concurrent transaction executions.
Rapid Motor Adaptation for Legged Robots (RMA) allows quadruped robots to rapidly adapt their walking gait when faced with new terrains or conditions. RMA consists of a base policy trained via reinforcement learning to walk in simulation, and an adaptation module that estimates environment factors to allow the base policy to adapt in real-time. When deployed on the A1 robot, RMA achieved a high success rate walking over various challenging terrains like sand, mud, and obstacles, without any failures in trials. The adaptation module allows the robot to adapt its gait within fractions of a second to respond to changes in conditions, outperforming alternatives that are slower to adapt or require explicit system identification.
Design and simulation of radio frequencyeSAT Journals
Abstract
Present day guided weapon systems, especially tactical class missiles use RF seeker, for target tracking towards terminal engagement. The seeker system including its antenna assembly will be onboard the missile. Due to the missile trajectory corrections, the seeker antenna pointing to the target may get disturbed resulting in track loss. To avoid this track loss, it becomes necessary to stabilize the antenna system in two planes. The fundamental role of stabilization loop in seeker application is to precisely follow the angular rate of the target. In order to achieve this requirement, it is essential to highly isolate the gimbaled antenna from the missile body motion due to the maneuvering of target or low frequency vibration during flight. However, the isolation ratio and stability margin of stabilization loop adopting the gimbaled platform with both low stiffness and heavy inertia are limited by mechanical characteristic such as low resonance frequency and its high magnitude. The selection of proper feedback sensors, modeling of the total system are key features of this project. In the end, the performance and the stability of designed stabilization loop are demonstrated using simulation in both frequency and time domain. The Hardware for the system is under realization by the Industry. The whole scheme is simulated in MATLAB off-line for this project.
Keywords: Missile, RF seeker, Track loss, Stabilization loop, Angular Rate Command, Bore-Sight Error, Maneuvering and Gimbaled Platform.
Power system planning involves arranging a scheme beforehand to adequately satisfy future load requirements. It determines new and upgraded generation, transmission, and distribution elements. Load forecasting is an important part of planning to estimate future loads. Short term forecasting is used for operations while long term forecasting informs infrastructure development decisions. Various statistical, artificial intelligence, and hybrid methods are used for load forecasting at different timescales, each with their own advantages and limitations regarding accuracy. Accurate load forecasting is essential for utility planning and operations.
This document proposes an efficient memory design for error tolerant applications using built-in self-repair (BISR). It uses built-in self-test (BIST) to test memories for faults and sends that information to built-in redundancy analysis (BIRA) to determine repair solutions. Memories are serially tested and repaired to reduce testing time and switching activities. The proposed approach uses multiple single input change (MSIC) vectors to test memories concurrently, reducing area and performance overhead compared to traditional BISR systems.
AN EFFICIENT MEMORY DESIGN FOR ERROR TOLERANT APPLICATION1 (1).pdfKeshvan Dhanapal
This document describes an efficient memory design for error tolerant applications. It aims to test memories, detect faults, and improve repair ability. The design uses a built-in self-repair (BISR) scheme combining built-in self-test (BIST) and built-in redundancy analysis (BIRA). BIST tests memories and sends fault information to BIRA. BIRA finds repair solutions for faulty memories. The design reduces testing time and switching activities while improving repairability.
AN EFFICIENT MEMORY DESIGN FOR ERROR TOLERANT APPLICATION1.pptxKeshvan Dhanapal
This document proposes an efficient memory design for error tolerant applications using built-in self-repair (BISR). It uses built-in self-test (BIST) to test memories for faults and sends that information to built-in redundancy analysis (BIRA) to determine repair solutions. Memories are serially tested and repaired to reduce testing time and switching activities. The proposed approach uses multiple single input change patterns to test memories concurrently before repairing faulty ones serially based on size. This achieves better performance and resource utilization than existing BIST, DMR, and TMR schemes.
Design of management dashboard (smart electric grids)Jatin Pherwani
Presentation for my Final year Design Project at Dept. of Design IIT Guwahati. The aim of this project is to allow efficient management of smart electricity grids in rural as well as urban areas primarily by catering the needs of engineers and technicians involved in monitoring and controlling the grid parameters for a huge and self sustaining electricity network
This document discusses different types of instruction hazards in pipelines including structural hazards, data hazards, and control hazards. It focuses on control hazards caused by branches, where the destination of the branch is unknown until it is evaluated. To resolve this, it discusses different branch prediction strategies like stalling, deciding the branch in the ID stage, delayed branches using compiler reordering, and branch prediction. Branch prediction involves using a branch history table (BHT) to predict if the branch will be taken or not based on its past behavior. The document provides statistics on typical branch behavior and analyzes the accuracy of 1-bit branch prediction. It also discusses scheduling instructions into the delay slot of delayed branches.
Embedded Systems (18EC62) – Embedded System Design Concepts (Module 4)Shrishail Bhat
This document discusses the characteristics and quality attributes of embedded systems. It describes several key characteristics of embedded systems, including being application specific, reactive and operating in real time, able to function in harsh environments, potentially distributed across multiple components, and having constraints on size, weight and power consumption. The document also distinguishes between operational quality attributes, like response time, throughput, reliability and maintainability, and non-operational attributes such as testability, evolvability and portability. Maintainability and reliability are discussed in detail through examples of mean time between failures and mean time to repair calculations.
The document discusses using machine learning techniques to predict the strength of building components, specifically beam-column joints. It begins with definitions of beam-column joints and issues associated with them, such as failures during earthquakes. Then it provides an overview of machine learning, including common algorithms like linear regression, logistic regression, decision trees, and artificial neural networks. The remainder of the document discusses using an artificial neural network approach specifically to model and predict the shear strength of exterior reinforced concrete beam-column joints based on experimental data. Key parameters that would be inputs to the neural network model are identified.
This document describes an early fault detection system called Faultdec. It uses a probabilistic model and state observer to monitor the internal state of a system, like a cricket ball stitching machine, and detect potential faults before they occur. The system works by discretizing the internal states into normal, degraded, and failed states. It then maps the state densities to a probability of fault. Faultdec uses hardware like an FPGA and concurrent design to rapidly monitor inputs and detect degraded states. When a degraded state is detected, an alarm is issued to allow corrective action to be taken before an actual failure occurs. The goal is to provide real-time fault awareness and avoidance for critical systems.
The transformer is the most important equipment in the transmission and distribution system.
This expert system is the principle of condition based maintenance strategy. The system consider discrete diagnostical results.
For the comparison we need to consider some other parameters what do not indicate the status of the insulation but it has influence for that.
In the research work, the expert system tested by real data from the Hungarian distribution system. The source of the testing data is 13 HV/MV distribution transformers in Hungary
Allocation of processors to processes in Distributed Systems. Strategies or algorithms for processor allocation. Design and Implementation Issues of Strategies.
The document provides guidance on using random sequential sampling with Excel and Audit Commander software. It describes sampling population data in Excel worksheets and selecting initial samples of 150 observations for variable and attribute sampling. The samples are sorted by random numbers and values from the actual column are copied over to the audited value column.
CS304PC:Computer Organization and Architecture Session 15 program control.pptxAsst.prof M.Gokilavani
This document summarizes the topics covered in session 15 of the CS304PC course on computer organization and architecture. It discusses general register organization, instruction formats, addressing modes, data transfer and manipulation, and program control. Specifically, it describes status registers, condition codes, and how program control instructions like branches, jumps, skips, calls and returns use condition codes to control program flow. It also covers program interrupts, defining external, internal, and software interrupts and providing examples of each type.
A Review of Different Types of Schedulers Used In Energy ManagementIRJET Journal
This document reviews different types of schedulers used for energy management in embedded systems. It discusses dynamic voltage and frequency scaling (DVFS) which aims to reduce energy consumption by varying CPU frequency and voltage dynamically. Real-time DVFS ensures quality of service by developing task schedules while reducing energy via DVFS. The paper surveys various DVFS scheduling algorithms that utilize CPU idle time to change frequency/voltage or use other techniques to meet power requirements. These algorithms can be offline, using worst-case execution times to pre-schedule all tasks, or online, making decisions in real-time based on past task executions to improve scheduling.
Models of Operational research, Advantages & disadvantages of Operational res...Sunny Mervyne Baa
This document discusses operational research models and their advantages and disadvantages. It describes several common OR models including linear programming, network flow programming, integer programming, nonlinear programming, dynamic programming, stochastic programming, combinatorial optimization, stochastic processes, discrete time Markov chains, continuous time Markov chains, queuing, and simulation. It notes advantages of OR in developing better systems, control, and decisions. However, it also lists limitations such as dependence on computers, inability to quantify all factors, distance between managers and researchers, costs of money and time, and challenges implementing OR solutions.
Based on visual basic differential workbench system design and implementation...eSAT Journals
Abstract
In this paper, we take the equipment precision differential bench which homemade by Shanghai University of Engineering and Technology for the study, and use the Visual Basic for precision motion system of differential table design and secondary development. Through experiments, we can get the change in position under different sports differential table, through the measurement of data analysis, we can get in the form of differential motion error table for further compensation error of the foundation.
Keywords: Visual Basic, Differential, The error analysis
This document discusses transaction processing in database management systems (DBMS). It describes the ACID properties that transactions must satisfy - atomicity, consistency, isolation, and durability. An example of a fund transfer transaction is provided to illustrate these properties. Concurrency control is discussed as a mechanism for allowing concurrent transactions while maintaining isolation. The concepts of schedules, conflicting instructions, conflict serializability, and view serializability are introduced for evaluating the correctness of concurrent transaction executions.
Rapid Motor Adaptation for Legged Robots (RMA) allows quadruped robots to rapidly adapt their walking gait when faced with new terrains or conditions. RMA consists of a base policy trained via reinforcement learning to walk in simulation, and an adaptation module that estimates environment factors to allow the base policy to adapt in real-time. When deployed on the A1 robot, RMA achieved a high success rate walking over various challenging terrains like sand, mud, and obstacles, without any failures in trials. The adaptation module allows the robot to adapt its gait within fractions of a second to respond to changes in conditions, outperforming alternatives that are slower to adapt or require explicit system identification.
Design and simulation of radio frequencyeSAT Journals
Abstract
Present day guided weapon systems, especially tactical class missiles use RF seeker, for target tracking towards terminal engagement. The seeker system including its antenna assembly will be onboard the missile. Due to the missile trajectory corrections, the seeker antenna pointing to the target may get disturbed resulting in track loss. To avoid this track loss, it becomes necessary to stabilize the antenna system in two planes. The fundamental role of stabilization loop in seeker application is to precisely follow the angular rate of the target. In order to achieve this requirement, it is essential to highly isolate the gimbaled antenna from the missile body motion due to the maneuvering of target or low frequency vibration during flight. However, the isolation ratio and stability margin of stabilization loop adopting the gimbaled platform with both low stiffness and heavy inertia are limited by mechanical characteristic such as low resonance frequency and its high magnitude. The selection of proper feedback sensors, modeling of the total system are key features of this project. In the end, the performance and the stability of designed stabilization loop are demonstrated using simulation in both frequency and time domain. The Hardware for the system is under realization by the Industry. The whole scheme is simulated in MATLAB off-line for this project.
Keywords: Missile, RF seeker, Track loss, Stabilization loop, Angular Rate Command, Bore-Sight Error, Maneuvering and Gimbaled Platform.
Power system planning involves arranging a scheme beforehand to adequately satisfy future load requirements. It determines new and upgraded generation, transmission, and distribution elements. Load forecasting is an important part of planning to estimate future loads. Short term forecasting is used for operations while long term forecasting informs infrastructure development decisions. Various statistical, artificial intelligence, and hybrid methods are used for load forecasting at different timescales, each with their own advantages and limitations regarding accuracy. Accurate load forecasting is essential for utility planning and operations.
This document discusses graph algorithms and directed acyclic graphs (DAGs). It explains that the edges in a graph can be identified as tree, back, forward, or cross edges based on the color of vertices during depth-first search (DFS). It also defines DAGs as directed graphs without cycles and describes how to perform a topological sort of a DAG by inserting vertices into a linked list based on their finishing times from DFS. Finally, it discusses how to find strongly connected components (SCCs) in a graph using DFS on the original graph and its transpose.
This document discusses string matching algorithms. It begins with an introduction to the naive string matching algorithm and its quadratic runtime. Then it proposes three improved algorithms: FC-RJ, FLC-RJ, and FMLC-RJ, which attempt to match patterns by restricting comparisons based on the first, first and last, or first, middle, and last characters, respectively. Experimental results show that these three proposed algorithms outperform the naive algorithm by reducing execution time, with FMLC-RJ working best for three-character patterns.
The document discusses shortest path problems and algorithms. It defines the shortest path problem as finding the minimum weight path between two vertices in a weighted graph. It presents the Bellman-Ford algorithm, which can handle graphs with negative edge weights but detects negative cycles. It also presents Dijkstra's algorithm, which only works for graphs without negative edge weights. Key steps of the algorithms include initialization, relaxation of edges to update distance estimates, and ensuring the shortest path property is satisfied.
The document discusses strongly connected component decomposition (SCCD) which uses depth-first search (DFS) to separate a directed graph into subsets of mutually reachable vertices. It describes running DFS on the original graph and its transpose to find these subsets in Θ(V+E) time, then provides an example applying the three step process of running DFS on the graph and transpose, finding two strongly connected components.
Red-black trees are self-balancing binary search trees. They guarantee an O(log n) running time for operations by ensuring that no path from the root to a leaf is more than twice as long as any other. Nodes are colored red or black, and properties of the coloring are designed to keep the tree balanced. Inserting and deleting nodes may violate these properties, so rotations are used to restore the red-black properties and balance of the tree.
This document discusses recurrences and the master method for solving recurrence relations. It defines a recurrence as an equation that describes a function in terms of its value on smaller functions. The master method provides three cases for solving recurrences of the form T(n) = aT(n/b) + f(n). If f(n) is asymptotically smaller than nlogba, the solution is Θ(nlogba). If f(n) is Θ(nlogba), the solution is Θ(nlogba lgn). If f(n) is asymptotically larger and the regularity condition holds, the solution is Θ(f(n)). It provides examples of applying
The document discusses the Rabin-Karp algorithm for string matching. It defines Rabin-Karp as a string search algorithm that compares hash values of strings rather than the strings themselves. It explains that Rabin-Karp works by calculating a hash value for the pattern and text subsequences to compare, and only does a brute force comparison when hash values match. The worst-case complexity is O(n-m+1)m but the average case is O(n+m) plus processing spurious hits. Real-life applications include bioinformatics to find protein similarities.
The document discusses minimum spanning trees (MST) and two algorithms for finding them: Prim's algorithm and Kruskal's algorithm. It begins by defining an MST as a spanning tree (connected acyclic graph containing all vertices) with minimum total edge weight. Prim's algorithm grows a single tree by repeatedly adding the minimum weight edge connecting the growing tree to another vertex. Kruskal's algorithm grows a forest by repeatedly merging two components via the minimum weight edge connecting them. Both algorithms produce optimal MSTs by adding only "safe" edges that cannot be part of a cycle.
This document discusses the analysis of insertion sort and merge sort algorithms. It covers the worst-case and average-case analysis of insertion sort. For merge sort, it describes the divide-and-conquer technique, the merge sort algorithm including recursive calls, how it works to merge elements, and analyzes merge sort through constructing a recursion tree to prove its runtime is O(n log n).
The document discusses loop invariants and uses insertion sort as an example. The invariant for insertion sort is that at the start of each iteration of the outer for loop, the elements in A[1...j-1] are sorted. It shows that this invariant is true before the first iteration, remains true after each iteration by how insertion sort works, and when the loops terminate the entire array A[1...n] will be sorted, proving correctness.
Linear sorting algorithms like counting sort, bucket sort, and radix sort can sort arrays of numbers in linear O(n) time by exploiting properties of the data. Counting sort works for integers within a range [0,r] by counting the frequency of each number and using the frequencies to place numbers in the correct output positions. Bucket sort places numbers uniformly distributed between 0 and 1 into buckets and sorts the buckets. Radix sort treats multi-digit numbers as strings by sorting based on individual digit positions from least to most significant.
The document discusses heap data structures and algorithms. A heap is a binary tree that satisfies the heap property of a parent being greater than or equal to its children. Common operations on heaps like building
Sri Guru Hargobind Ji - Bandi Chor Guru.pdfBalvir Singh
Sri Guru Hargobind Ji (19 June 1595 - 3 March 1644) is revered as the Sixth Nanak.
• On 25 May 1606 Guru Arjan nominated his son Sri Hargobind Ji as his successor. Shortly
afterwards, Guru Arjan was arrested, tortured and killed by order of the Mogul Emperor
Jahangir.
• Guru Hargobind's succession ceremony took place on 24 June 1606. He was barely
eleven years old when he became 6th Guru.
• As ordered by Guru Arjan Dev Ji, he put on two swords, one indicated his spiritual
authority (PIRI) and the other, his temporal authority (MIRI). He thus for the first time
initiated military tradition in the Sikh faith to resist religious persecution, protect
people’s freedom and independence to practice religion by choice. He transformed
Sikhs to be Saints and Soldier.
• He had a long tenure as Guru, lasting 37 years, 9 months and 3 days
Null Bangalore | Pentesters Approach to AWS IAMDivyanshu
#Abstract:
- Learn more about the real-world methods for auditing AWS IAM (Identity and Access Management) as a pentester. So let us proceed with a brief discussion of IAM as well as some typical misconfigurations and their potential exploits in order to reinforce the understanding of IAM security best practices.
- Gain actionable insights into AWS IAM policies and roles, using hands on approach.
#Prerequisites:
- Basic understanding of AWS services and architecture
- Familiarity with cloud security concepts
- Experience using the AWS Management Console or AWS CLI.
- For hands on lab create account on [killercoda.com](https://killercoda.com/cloudsecurity-scenario/)
# Scenario Covered:
- Basics of IAM in AWS
- Implementing IAM Policies with Least Privilege to Manage S3 Bucket
- Objective: Create an S3 bucket with least privilege IAM policy and validate access.
- Steps:
- Create S3 bucket.
- Attach least privilege policy to IAM user.
- Validate access.
- Exploiting IAM PassRole Misconfiguration
-Allows a user to pass a specific IAM role to an AWS service (ec2), typically used for service access delegation. Then exploit PassRole Misconfiguration granting unauthorized access to sensitive resources.
- Objective: Demonstrate how a PassRole misconfiguration can grant unauthorized access.
- Steps:
- Allow user to pass IAM role to EC2.
- Exploit misconfiguration for unauthorized access.
- Access sensitive resources.
- Exploiting IAM AssumeRole Misconfiguration with Overly Permissive Role
- An overly permissive IAM role configuration can lead to privilege escalation by creating a role with administrative privileges and allow a user to assume this role.
- Objective: Show how overly permissive IAM roles can lead to privilege escalation.
- Steps:
- Create role with administrative privileges.
- Allow user to assume the role.
- Perform administrative actions.
- Differentiation between PassRole vs AssumeRole
Try at [killercoda.com](https://killercoda.com/cloudsecurity-scenario/)
Prediction of Electrical Energy Efficiency Using Information on Consumer's Ac...PriyankaKilaniya
Energy efficiency has been important since the latter part of the last century. The main object of this survey is to determine the energy efficiency knowledge among consumers. Two separate districts in Bangladesh are selected to conduct the survey on households and showrooms about the energy and seller also. The survey uses the data to find some regression equations from which it is easy to predict energy efficiency knowledge. The data is analyzed and calculated based on five important criteria. The initial target was to find some factors that help predict a person's energy efficiency knowledge. From the survey, it is found that the energy efficiency awareness among the people of our country is very low. Relationships between household energy use behaviors are estimated using a unique dataset of about 40 households and 20 showrooms in Bangladesh's Chapainawabganj and Bagerhat districts. Knowledge of energy consumption and energy efficiency technology options is found to be associated with household use of energy conservation practices. Household characteristics also influence household energy use behavior. Younger household cohorts are more likely to adopt energy-efficient technologies and energy conservation practices and place primary importance on energy saving for environmental reasons. Education also influences attitudes toward energy conservation in Bangladesh. Low-education households indicate they primarily save electricity for the environment while high-education households indicate they are motivated by environmental concerns.
Digital Twins Computer Networking Paper Presentation.pptxaryanpankaj78
A Digital Twin in computer networking is a virtual representation of a physical network, used to simulate, analyze, and optimize network performance and reliability. It leverages real-time data to enhance network management, predict issues, and improve decision-making processes.
Supermarket Management System Project Report.pdfKamal Acharya
Supermarket management is a stand-alone J2EE using Eclipse Juno program.
This project contains all the necessary required information about maintaining
the supermarket billing system.
The core idea of this project to minimize the paper work and centralize the
data. Here all the communication is taken in secure manner. That is, in this
application the information will be stored in client itself. For further security the
data base is stored in the back-end oracle and so no intruders can access it.
Determination of Equivalent Circuit parameters and performance characteristic...pvpriya2
Includes the testing of induction motor to draw the circle diagram of induction motor with step wise procedure and calculation for the same. Also explains the working and application of Induction generator
Blood finder application project report (1).pdfKamal Acharya
Blood Finder is an emergency time app where a user can search for the blood banks as
well as the registered blood donors around Mumbai. This application also provide an
opportunity for the user of this application to become a registered donor for this user have
to enroll for the donor request from the application itself. If the admin wish to make user
a registered donor, with some of the formalities with the organization it can be done.
Specialization of this application is that the user will not have to register on sign-in for
searching the blood banks and blood donors it can be just done by installing the
application to the mobile.
The purpose of making this application is to save the user’s time for searching blood of
needed blood group during the time of the emergency.
This is an android application developed in Java and XML with the connectivity of
SQLite database. This application will provide most of basic functionality required for an
emergency time application. All the details of Blood banks and Blood donors are stored
in the database i.e. SQLite.
This application allowed the user to get all the information regarding blood banks and
blood donors such as Name, Number, Address, Blood Group, rather than searching it on
the different websites and wasting the precious time. This application is effective and
user friendly.
Open Channel Flow: fluid flow with a free surfaceIndrajeet sahu
Open Channel Flow: This topic focuses on fluid flow with a free surface, such as in rivers, canals, and drainage ditches. Key concepts include the classification of flow types (steady vs. unsteady, uniform vs. non-uniform), hydraulic radius, flow resistance, Manning's equation, critical flow conditions, and energy and momentum principles. It also covers flow measurement techniques, gradually varied flow analysis, and the design of open channels. Understanding these principles is vital for effective water resource management and engineering applications.
2. Branch predictor
• In computer architecture, a branch predictor is
a digital circuit that tries to guess which way
a branch (e.g. an if-then-else structure) will go
before this is known for sure.
• The purpose of the branch predictor is to improve
the flow in the instruction pipeline.
• Branch predictors play a critical role in achieving
high effective performance in many
modern pipelined microprocessor architectures
Dr. Amit Kumar, Dept of CSE, JUET, Guna
3. Branch predictor
• Without branch prediction, the processor
would have to wait until the conditional
jump (branch) instruction has passed the
execute stage before the next instruction
can enter the fetch stage in the pipeline.
• The branch predictor attempts to avoid
this waste of time by trying to guess
whether the conditional jump is most likely
to be taken or not taken.
Dr. Amit Kumar, Dept of CSE, JUET, Guna
4. Branch predictor
• Branch prediction is not the same as branch
target prediction.
• Branch prediction attempts to guess whether a
conditional jump will be taken or not.
• Branch target prediction attempts to guess the
target of a taken conditional or unconditional
jump before it is computed by decoding and
executing the instruction itself. Branch
prediction and branch target prediction are
often combined into the same circuitry.
Dr. Amit Kumar, Dept of CSE, JUET, Guna
5. Branch Prediction Techniques
• Static prediction is the simplest branch prediction
technique because it does not rely on information
about the dynamic history of code executing.
Instead it predicts the outcome of a branch based
solely on the branch instruction.
• The early implementations
of SPARC and MIPS (two of the first
commercial RISC architectures) used single
direction static branch prediction.
• They always predicted that a conditional jump
would not be taken, so they always fetched the
next sequential instruction.
Dr. Amit Kumar, Dept of CSE, JUET, Guna
6. Static prediction
• Only when the branch or jump was evaluated
and found to be taken did the instruction
pointer get set to a non-sequential address.
• Both CPUs evaluated branches in the decode
stage and had a single cycle instruction fetch.
• As a result, the branch target recurrence was
two cycles long, and the machine would always
fetch the instruction immediately after any
taken branch.
• Both architectures defined branch delay slots in
order to utilize these fetched instructions.Dr. Amit Kumar, Dept of CSE, JUET, Guna
7. Static prediction
• A more complex form of static prediction assumes that
backwards branches will be taken, and forward-pointing
branches will not be taken.
• A backwards branch is one that has a target address that
is lower than its own address.
• This technique can help with prediction accuracy of
loops, which are usually backward-pointing branches,
and are taken more often than not taken.
• Static prediction is used as a fall-back technique in some
processors with dynamic branch prediction when there
isn't any information for dynamic predictors to use.
• Both the Motorola MPC7450 (G4e) and the
Intel Pentium 4 use this technique as a fall-back.
Dr. Amit Kumar, Dept of CSE, JUET, Guna
8. Next line prediction
• Some superscalar processors (MIPS R8000, Alpha
21264 and Alpha 21464 (EV8)) fetch each line of
instructions with a pointer to the next line.
• This next line predictor handles branch target
prediction as well as branch direction prediction.
• When a next line predictor points to aligned groups
of 2, 4 or 8 instructions, the branch target will
usually not be the first instruction fetched, and so
the initial instructions fetched are wasted.
• Assuming for simplicity a uniform distribution of
branch targets, 0.5, 1.5, and 3.5 instructions fetched
are discarded, respectively.
Dr. Amit Kumar, Dept of CSE, JUET, Guna
9. Saturating counter
• A saturating counter or bimodal predictor is
a state machine with four states:
• Strongly not taken
• Weakly not taken
• Weakly taken
• Strongly taken
When a branch is evaluated, the corresponding
state machine is updated.
Branches evaluated as not taken decrement the
state towards strongly not taken, and branches
evaluated as taken increment the state towards
strongly taken.
Dr. Amit Kumar, Dept of CSE, JUET, Guna
10. Saturating counter
The advantage of the two-bit counter over a one-bit
scheme is that a conditional jump has to deviate twice
from what it has done most in the past before the
prediction changes. For example, a loop-closing
conditional jump is mispredicted once rather than twice.
Dr. Amit Kumar, Dept of CSE, JUET, Guna
11. Saturating counter
• The original, non-MMX Intel Pentium processor
uses a saturating counter, though with an
imperfect implementation.
• On the SPEC'89 benchmarks, very large bimodal
predictors saturate at 93.5% correct, once every
branch maps to a unique counter.
• The predictor table is indexed with the
instruction address bits, so that the processor
can fetch a prediction for every instruction
before the instruction is decoded.
Dr. Amit Kumar, Dept of CSE, JUET, Guna
12. Two-level adaptive predictor
• If there are three if statements in a code, the
third if statement might be taken depending
upon whether the previous two were
taken/not-taken.
• In such scenarios two-level adaptive predictor
works more efficiently than a saturation
counter.
• Conditional jumps that are taken every second
time or have some other regularly recurring
pattern are not predicted well by the saturating
counter.
Dr. Amit Kumar, Dept of CSE, JUET, Guna
13. Two-level adaptive predictor
A two-level adaptive predictor remembers the
history of the last n occurrences of the branch and
uses one saturating counter for each of the
possible 2n history patterns.
Consider the example of n = 2. This
means that the last two occurrences
of the branch are stored in a 2-bit
shift register. This branch history
register can have 4 different binary
values: 00, 01, 10, and 11; where 0
means "not taken" and 1 means
"taken".
Dr. Amit Kumar, Dept of CSE, JUET, Guna
14. Two-level adaptive predictor
• Now, we make a pattern history table with four
entries, one for each of the 2n = 4 possible
branch histories.
• Each entry in the pattern history table contains a
2-bit saturating counter.
• The branch history register is used for choosing
which of the four saturating counters to use.
• If the history is 00 then the first counter is used.
• If the history is 11 then the last of the four
counters is used.Dr. Amit Kumar, Dept of CSE, JUET, Guna
15. Two-level adaptive predictor
• Assume, for example, that a conditional jump is
taken every third time.
• The branch sequence is 001001001... In this
case, entry number 00 in the pattern history
table will go to state "strongly taken", indicating
that after two zeroes comes a one.
• Entry number 01 will go to state "strongly not
taken", indicating that after 01 comes a 0.
• The same is the case with entry number 10,
while entry number 11 is never used because
there are never two consecutive ones.Dr. Amit Kumar, Dept of CSE, JUET, Guna
16. Two-level adaptive predictor
• The general rule for a two-level adaptive
predictor with an n-bit history is that it can
predict any repetitive sequence with any period
if all n-bit sub-sequences are different.
• The advantage of the two-level adaptive
predictor is that it can quickly learn to predict an
arbitrary repetitive pattern. This method was
invented by T.-Y. Yeh and Yale Patt at the
University of Michigan.
Dr. Amit Kumar, Dept of CSE, JUET, Guna
17. Local branch prediction
• A local branch predictor has a separate history buffer for
each conditional jump instruction.
• It may use a two-level adaptive predictor. The history
buffer is separate for each conditional jump instruction,
while the pattern history table may be separate as well
or it may be shared between all conditional jumps.
• The Intel Pentium MMX, Pentium II and III have local
branch predictors with a local 4-bit history and a local
pattern history table with 16 entries for each conditional
jump.
• On the SPEC'89 benchmarks, very large local predictors
saturate at 97.1% correct
Dr. Amit Kumar, Dept of CSE, JUET, Guna
18. Global branch prediction
• A global branch predictor does not keep a separate
history record for each conditional jump.
• Instead it keeps a shared history of all conditional
jumps.
• The advantage of a shared history is that any
correlation between different conditional jumps is
part of making the predictions.
• The disadvantage is that the history is diluted by
irrelevant information if the different conditional
jumps are uncorrelated, and that the history buffer
may not include any bits from the same branch if
there are many other branches in between. It may
use a two-level adaptive predictor.
Dr. Amit Kumar, Dept of CSE, JUET, Guna
19. Global branch prediction
• This scheme is only better than the saturating
counter scheme for large table sizes, and it is
rarely as good as local prediction.
• The history buffer must be longer in order to
make a good prediction.
• The size of the pattern history table grows
exponentially with the size of the history buffer.
• Hence, the big pattern history table must be
shared among all conditional jumps.
Dr. Amit Kumar, Dept of CSE, JUET, Guna
20. Global branch prediction
• A two-level adaptive predictor with globally
shared history buffer and pattern history table is
called a "gshare" predictor if it XORs the global
history and branch PC, and "gselect" if it
concatenates them.
• Global branch prediction is used in AMD
microprocessors and in Intel Pentium M, Core
and Core 2.
• On the SPEC'89 benchmarks, very large gshare
predictors saturate at 96.6% correct, which is just
a little worse than large local predictorsDr. Amit Kumar, Dept of CSE, JUET, Guna
21. Alloyed branch prediction
• An alloyed branch predictor combines the
local and global prediction principles by
concatenating local and global branch
histories, possibly with some bits from the
program counter as well.
• Tests indicate that the VIA Nano processor
may be using this technique.
Dr. Amit Kumar, Dept of CSE, JUET, Guna
22. Agree predictor
• An agree predictor is a two-level adaptive
predictor with globally shared history buffer and
pattern history table, and an additional local
saturating counter.
• The outputs of the local and the global predictors
are XORed with each other to give the final
prediction.
• The purpose is to reduce contentions in the
pattern history table where two branches with
opposite prediction happen to share the same
entry in the pattern history table.
• The agree predictor was used in the first version
of the Intel Pentium 4, but was later abandoned.
Dr. Amit Kumar, Dept of CSE, JUET, Guna
23. Hybrid predictor
• A hybrid predictor, also called combined
predictor, implements more than one
prediction mechanism.
• The final prediction is based either on a meta-
predictor that remembers which of the
predictors has made the best predictions in
the past, or a majority vote function based on
an odd number of different predictors.
• Scott McFarling proposed combined branch
prediction in his 1993 paper.
Dr. Amit Kumar, Dept of CSE, JUET, Guna
24. Hybrid predictor
• On the SPEC'89 benchmarks, such a predictor
is about as good as the local predictor.
• Predictors like gshare use multiple table
entries to track the behavior of any particular
branch.
• This multiplication of entries makes it much
more likely that two branches will map to the
same table entry (a situation called aliasing),
which in turn makes it much more likely that
prediction accuracy will suffer for those
branches.
Dr. Amit Kumar, Dept of CSE, JUET, Guna
25. Hybrid predictor
• Once you have multiple predictors, it is
beneficial to arrange that each predictor will
have different aliasing patterns, so that it is
more likely that at least one predictor will
have no aliasing.
• Combined predictors with different indexing
functions for the different predictors are
called gskew predictors, and are analogous to
skewed associated caches used for data and
instruction caching.
Dr. Amit Kumar, Dept of CSE, JUET, Guna
26. Loop predictor
• A conditional jump that controls a loop is
best predicted with a special loop
predictor.
• A conditional jump in the bottom of a loop
that repeats N times will be taken N-1
times and then not taken once.
• If the conditional jump is placed at the top
of the loop, it will be not taken N-1 times
and then taken once.
Dr. Amit Kumar, Dept of CSE, JUET, Guna
27. Loop predictor
• A conditional jump that goes many times one
way and then the other way once is detected as
having loop behavior. Such a conditional jump
can be predicted easily with a simple counter.
• A loop predictor is part of a hybrid predictor
where a meta-predictor detects whether the
conditional jump has loop behavior.
• Many microprocessors today have loop
predictors.
Dr. Amit Kumar, Dept of CSE, JUET, Guna
28. Prediction of indirect jumps
• An indirect jump instruction can choose among
more than two branches.
• Newer processors from Intel and AMD can
predict indirect branches by using a two-level
adaptive predictor.
• This kind of instruction contributes more than
one bit to the history buffer.
• Processors without this mechanism will simply
predict an indirect jump to go to the same target
as it did last time.
Dr. Amit Kumar, Dept of CSE, JUET, Guna
29. Prediction of function returns
• A function will normally return to where it is
called from.
• The return is an indirect jump that reads its
target address from the call stack.
• Many microprocessors have a separate
prediction mechanism for return instructions.
• This mechanism is based on a so-called return
stack buffer, which is a local mirror of the call
stack.
• The size of the return stack buffer is typically 4 -
16 entries.
Dr. Amit Kumar, Dept of CSE, JUET, Guna
30. Overriding branch prediction
• The trade-off between fast branch prediction and
good branch prediction is sometimes dealt with by
having two branch predictors.
• The first branch predictor is fast and simple.
• The second branch predictor, which is slower,
more complicated, and with bigger tables, will
override a possibly wrong prediction made by the
first predictor.
• The Alpha 21264 and Alpha EV8 microprocessors
used a fast single-cycle next line predictor to
handle the branch target recurrence and provide a
simple and fast branch prediction.
Dr. Amit Kumar, Dept of CSE, JUET, Guna
31. Overriding branch prediction
• Because the next line predictor is so
inaccurate, and the branch resolution
recurrence takes so long, both cores have two-
cycle secondary branch predictors which can
override the prediction of the next line
predictor at the cost of a single lost fetch
cycle.
• The Intel Core i7 has two branch target
buffers and possibly two or more branch
predictors.
Dr. Amit Kumar, Dept of CSE, JUET, Guna
32. Neural branch prediction
• Machine learning for branch prediction
using Learning Vector Quantization
(LVQ) and multi-layer perceptrons, called
"neural branch prediction," was proposed by
Prof. Lucian Vintan (Lucian Blaga University of
Sibiu).
• The neural branch predictor research was
developed much further by Prof. Daniel Jimenez
(Rutgers University, USA).
• In 2001, (HPCA Conference) first perceptron
predictor was presented that was feasible to
implement in hardware.Dr. Amit Kumar, Dept of CSE, JUET, Guna
33. Neural branch prediction
• The main advantage of the neural predictor is
its ability to exploit long histories while
requiring only linear resource growth. Classical
predictors require exponential resource
growth.
• Jimenez reports a global improvement of 5.7%
over a McFarling-style hybrid predictor.
• He also used a gshare/perceptron overriding
hybrid predictors.
• The main disadvantage of the perceptron
predictor is its high latency.
Dr. Amit Kumar, Dept of CSE, JUET, Guna
34. Neural branch prediction
• Even after taking advantage of high-speed
arithmetic tricks, the computation latency is
relatively high compared to the clock period of
many modern microarchitectures.
• In order to reduce the prediction latency,
Jimenez proposed in 2003 the fast-path neural
predictor, where the perceptron predictor
chooses its weights according to the current
branch’s path, rather than according to the
branch’s PC.
Dr. Amit Kumar, Dept of CSE, JUET, Guna
35. Neural branch prediction
• Many other researchers developed this concept
(A. Seznec, M. Monchiero, D. Tarjan & K.
Skadron, V. Desmet, Akkary et al., K. Aasaraai,
Michael Black, etc.).
• Most of the state of the art branch predictors are
using a perceptron predictor (Intel's
"Championship Branch Prediction Competition”.
Intel already implements this idea in one of the
IA-74's simulators (2003).
Dr. Amit Kumar, Dept of CSE, JUET, Guna