memory testing

1. AN EFFICIENT MEMORY
DESIGN FOR ERROR
TOLERANT APPLICATION
Presented by
D KESAVAN
AP/ECE

2. Objective
• To test the memories and to detect the
number of faults and to improve repair ability
of the systems
• The faulty memories are serially tested and
repaired
• Reduce testing time and switching activities

3. Introduction
• Built in self repair scheme(BISR) uses the
built in self test(BIST) and Built in repair
analysis(BIRA).
• BIST is used test and detect faulty memories
• It send the fault information to BIRA
• BIRA is used to find the repair solutions to the
faulty memories

4. BASIC MEMORY MODEL

5. MEMORY MODEL-CONTN
• Memory cell is composed of two fundamental
components: the ‘storage node’ and ‘select device’.
• The ‘select device’ component facilitates the memory
cell to be addressed to read/write in an array.
• Row and address decoders determine the cell address
that needs to be accessed.
• Based on the addresses on the row and column
decoders, the corresponding row and column get
selected which then get connected to sense amplifier.
• The sense amplifier amplifies and sends out the data.

6. Built-in redundancy analysis (BIRA)
• The faulty cells are repaired line by line, including
faulty cells which are repaired with a spare row or
column, instead of using a bit-by-bit approach. This is
called a redundancy analysis (RA)
• BIRA module helps to calculate the repair signature
based on the memory failure data and the implemented
memory redundancy scheme.
• It determines whether the memory is repairable in the
production testing environments.
• The repair signature will be stored in the BIRA
registers for further processing by MBIST Controllers
or ATE device.

7. Existing schemes
• DMR
• TMR
• BIST

8. DMR
• In reliability engineering, dual modular redundancy (DMR) is
when components of a system are duplicated,
providing redundancy in case one should fail.
• It is particularly applied to systems where the duplicated
components work in parallel, particularly in fault-tolerant computer
systems
• A typical example is a complex computer system which has
duplicated nodes, so that should one node fail, another is ready to
carry on its work.
• DMR provides robustness to the failure of one component, and error
detection in case instruments or computers that should give the same
result give different results, but does not provide error correction,
as which component is correct and which is malfunctioning cannot
be automatically determined

9. TMR

10. TMR
• In which three systems perform a process and that
result is processed by a majority-voting system to
produce a single output.
• If any one of the three systems fails, the other two
systems can correct and mask the fault.
• Triple Modular Redundancy. Three identical logic
circuits (logic gates) are used to compute the
specified Boolean function.
• The set of data at the input of the first circuit are
identical to the input of the second and third
gates.

11. BIST
• A built-in self-test (BIST) or built-in test (BIT)
is a mechanism that permits a machine to test
itself with test pattern generator
• The basic BIST architecture requires the
addition of three hardware blocks to a digital
circuit: a test pattern generator, a response
analyzer, and a test controller.
• The test pattern generator generates the test
patterns for the CUT.

12. DRAWBACK
• Area
• Time complexity
• Less fault coverage

13. Combined BIST & BIRA Method
• To handle permanent faults, this technique will
suggested
• If any permanent faults are detected the testing
control avoid the prohibited zone to apply the
MIC(Memory image completion) pattern
• It will avoids usage of the faulty zone
• This technique is used to reduce the testing cost
and complexity

14. Memory Built-in Self Repair (BISR)

15. Memory Built-in Self Repair (BISR)
• Memories occupy a large area of the SoC design
and very often have a smaller feature size.
• Both of these factors indicate that memories have
a significant impact on yield.
• To avoid yield loss, redundant or spare rows and
columns of storage cells are often added so that
faulty cells can be redirected to redundant cells.
• Memory repair includes row repair, column repair
or a combination of both

16. Memory Built-in Self Repair (BISR)
• Memory repair is implemented in two steps. The first step is
to analyze the failures diagnosed by the MBIST Controller
during the test for repairable memories, and the second step
is to determine the repair signature to repair the memories.
• All the repairable memories have repair registers which
hold the repair signature.
• BIRA (Built-In Redundancy Analysis) module helps to
calculate the repair signature based on the memory failure
data and the implemented memory redundancy scheme.
• It also determines whether the memory is repairable in the
production testing environments.
• The repair signature will be stored in the BIRA registers for
further processing by MBIST Controllers or ATE device.

17. Memory Built-in Self Repair (BISR)
• The repair signature is then passed on to the repair register’s scan
chain for subsequent Fusebox programming, which is located at the
chip design level.
• The reading and writing of a Fusebox is controlled through TAP
(Test Access Port) and dedicated repair registers scan chains
connecting memories to fuses.
• The repair information is then scanned out of the scan chains,
compressed, and is burnt on-the-fly into the eFuse array by applying
high voltage pulses.
• On-chip reset, the repair information from the eFuse is automatically
loaded and decompressed in the repair registers, which are directly
connected to the memories.
• This results in all memories with redundancies being repaired.
Finally, BIST is run on the repaired memories which verify the
correctness of memories.

18. Combined BIST and BIRA

19. Explanation
• It mainly consists of BIST and BIRA modules.
• The main purpose is to classify the memories as faulty or not,
and the number of faults in each memory is stored in the
dedicated wrapper.
• When the fault is detected by BIST, the fault information is
sent to BIRA through the port Fault_info.
• After the test is completed or stopped, the signal Test_ finish is
activated and BIRA executes the RA process to find repair
solutions

20. Explanation- Contn
• In this research, a BISR technique for multiple embedded memories with
SIC(Simplified Instructional computer) pattern generation is proposed.
• To find optimum point of the performance of BISR for multiple embedded
memories, the proposed BISR scheme is proposed. All memories are
concurrently tested by the small dedicated BIST to figure out the faulty, the
number of faults, and irreparability.
• After all memories are tested, only faulty memories are serially tested and
repaired by the global BIRA according to the sizes of memories in
descending order.
• In this method, we generates multiple single input change (MSIC) vectors
in a pattern, i.e., each vector applied to a scan chain is an SIC vector.
• A SIC counter is developed to generate a class of minimum transition
sequences respectively, while imposing negligible area and performance
overheads on the traditional BISR systems.

21. Performance analysis
0
5
10
15
20
25
30
Slice lut iob
Existing
Proposed

22. Applications
• Satellite systems
• Medical fields

23. Future works
• An Efficient VLSI Test Data Compression Scheme for Circular Scan
Architecture Based on Modified Ant Colony Meta-heuristic is
designed
• A new test data compression scheme for circular scan architecture is
proposed in this paper.
• A stochastic heuristic based bio-inspired optimization approach
namely ant colony algorithm (ACO) is applied after modification
and customization to improve compression efficiency. In circular
scan architecture, test data compression is achieved by updating the
conflicting bits between the most recently captured response and test
vector to be applied next.
• The quantity of conflicting bits also manifests the Hamming
distance between the most recently captured response and the next
test vector.

24. Future works-Contn
• A significant reduction in test data volume and test application time
is achieved by reducing Hamming distance.
• The problem is renovated as a traveling salesman problem (TSP).
• The test vectors are presumed as cities and Hamming distance
between a pair of test vectors is treated as intercity distance and a
modified ACO algorithm in combination with mutation operator is
applied here to resolve this combinatorial optimization problem.
• The experimental results confirm the efficacy of this approach.
• An average improvement of 6.36% in compression ratio and 4.77%
in test application time is achieved. The exhibited technique sustains
an optimal level of performance without incurring any extra DFT
(design for testability) cost.

25. Future works-Contn
• High-Speed RLWE-Oriented Polynomial Multiplier Utilizing
Karatsuba Algorithm is designed
• Cryptography based on ring learning with error (RLWE) problem
has become increasingly popular due to its resistance against
quantum analysis. The most time-consuming operation in RLWE
cryptosystem is polynomial multiplication
• Lattice-based cryptography (LBC) is one of the promising post-
quantum candidates which offers good security and performance.
• Karatsuba algorithm with better complexity compared to SPMA, is
not widely studied for FPGA implementation of LBC.
• If overclocking or tuning for additional performance, you can
manually set the multiplier.

26. Future works-Contn
• In this paper, we proposed an optimized Karatsuba
architecture with novel technique to implement the
negacyclic convolution.
• The proposed architecture is more than 2.09× faster and
56.06% additional hardware resources is reduced
compared to other architecture.
• This shows that the Karatsuba algorithm can produce
hardware architecture with higher speed yet maintain
balanced area-time efficiency
• This is especially useful for developing IoT edge nodes
or gateway devices that require high speed but able to
tolerate some additional hardware area.

27. CIRCULAR SCAN ARCHITECTURE
• The basic idea of circular-scan architecture is using the captured response
of the previously applied test pattern as a template for the next pattern.
• In this architecture, only the conflicting bits of previously captured
response are updated through a data input pin.
• A new circular-scan architecture that makes it possible to select several
scan chains in parallel.
• In the proposed architecture, multiple conflict bits are selected and updated
simultaneously In comparison with original architecture which it is possible
to select only one scan chain at each time using a regular decoder, the
parallel updating of conflict bits results in more reduction in test data
volume and test application time.
• Scan chains are selected in parallel, using a multiple-hot decoder.
• Experimental results show an average improvement of 26% in test data
volume and test application time, in the 5 largest ISCAS'89 benchmark
circuits.

28. ACO
• Ant colony optimization (ACO) is a population-based metaheuristic
that can be used to find approximate solutions to difficult
optimization problems.
• In ACO, a set of software agents called artificial ants search for
good solutions to a given optimization problem.
• To apply ACO, the optimization problem is transformed into the
problem of finding the best path on a weighted graph.
• The artificial ants (hereafter ants) incrementally build solutions by
moving on the graph.
• The solution construction process is stochastic and is biased by
a pheromone model, that is, a set of parameters associated with
graph components (either nodes or edges) whose values are
modified at runtime by the ants.

29. ACO

30. Karatsuba multiplication

31. REFERENCES
• [1] Semico Res. Corp., Phoenix, AZ, USA, ASIC IP Rep., 2007. [Online].
Available: http://www.semico.com/content/semico-systemschip-%
E2%80%93-braver-new-world
• [2] Zheng-Yan Wong; Denis C.-K. Wong; Wai-Kong Lee; Kai-Ming Mok,
“High-Speed RLWE-Oriented Polynomial Multiplier Utilizing Karatsuba
Algorithm,” in IEEE Transactions on Circuits and Systems II: Express
Briefs ., 04 January 2021, pp 1 - 1.
• [3] Sanjoy Mitra, Debaprasad Das, “An Efficient VLSI Test Data
Compression Scheme for Circular Scan Architecture Based on Modified
Ant Colony Meta-heuristic June 2020”,Journal of Electronic Testing 36(5)
• [4] P. Öhler, S. Hellebrand, and H.-J. Wunderlich, “An integrated built-in
test and repair approach for memories with 2D redundancy,” in Proc. 12th
IEEE Eur. Test Symp., May 2007, pp. 91–96.
• [5] W. Jeong, I. Kang, K. Jin, and S. Kang, “A fast built-in redundancy
analysis for memories with optimal repair rate using a line-based search
tree,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 17, no. 12, pp.
1665–1678, Dec. 2009.

32. THANK YOU