Automating Testing with Telelogic DOORS @ NXP - Automatisation de test avec Telelogic DOORS chez NXP Semiconductors (Presentation Telelogic UGC 2008 France)
This document provides a summary of an individual's professional experience in embedded automotive software development using AUTOSAR. It includes details on their education, technical skills, work experience with various automotive companies as a software engineer and technical leader specializing in areas like network design, communication stack development, integration and testing. It also lists their academic qualifications and achievements.
The document discusses a project to implement a distributed process control system with wireless accessibility. It describes the Process Control Studio software, which allows designing and monitoring industrial processes on a laptop or PDA. The software includes features like alarming, data storage, and a mobile edition. Wireless connectivity is provided via WiFi, and an Ethernet controller allows interfacing with local measurements and controls. The controller performs data acquisition from analog and digital sensors using an ADC and can control actuators with a DAC. It also implements on-off and PID control algorithms using a microcontroller. The goal is to provide localized wireless monitoring and control of industrial processes.
Sudha Madhuri has over 9 years of experience as a Software Professional and Scrum Master with expertise in C/C++, Java, and telecom domains including protocols, data handling, and billing. She has led projects for Tata Consultancy Services and Wipro Technologies as Project Leader, Scrum Master, Technical Coordinator, and Team Leader, delivering software for Ericsson in areas like switches, radio access networks, and VOIP gateways. Sudha holds a B.Tech in Electronics and Communications Engineering and is legally authorized to work in Canada.
The document summarizes the rationale and main contributions of a thesis on managing and analyzing bitstream generators for Xilinx FPGAs. The thesis proposes a novel framework for debugging and validating partial dynamic reconfiguration architectures on Xilinx FPGAs in a way that is independent of Xilinx software and automates constraint checking, error resolution, and exploration of reconfiguration possibilities. The framework includes modules for parsing designs, performing constraint and conflict analysis, and allowing design alterations through region redefinition and bitstream relocation. It is demonstrated on an image processing application with reconfigurable filters and detectors.
SDN-enhanced Services in Enterprises and Data CentersAnees Shaikh
The document discusses software-defined networking (SDN) and opportunities for using SDN to enhance network services in enterprises and data centers. It notes that while SDN controllers currently provide low-level APIs focused on network control, more work is needed to develop higher-level APIs and abstractions that can be consumed by applications and integrated with IT processes. The document presents examples of potential new network models and abstractions that could enable uses cases like network security management, application connectivity services, and workload migration.
The document proposes a framework called Rebit for analyzing and managing bitstream generators for partial dynamic reconfiguration (PDR) on Xilinx FPGAs. It aims to address issues with existing PDR flows, which require manual definition of reconfigurable regions (RRs) and have no guarantees that constraints will be satisfied. Rebit allows automated constraint checking, guided error resolution, and exploration of relocation possibilities to validate PDR designs independently of Xilinx software. It is demonstrated on a case study of an edge detection application with two reconfigurable modules.
MADES Seminar @ Laboratory of Model-Driven Engineering Applied to Embedded Sy...Alessandra Bagnato
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Lieu: salle 1073 (Nano-innov – Bat. 862)
Date: 24 Septembre 2012
Heure: 14:00 – 15:00
Orateur: Alessandra Bagnato
Titre: UML, SysML and MARTE in Use, a High Level Methodology for Real-time and Embedded Systems
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Résumé/Abstract
Rapid evolution of real-time and embedded systems (RTES) is continuing at an increasing rate, and new methodologies and design tools are needed to reduce design complexity while decreasing development costs and integrating aspects such as verification and validation. Model-Driven Engineering offers an interesting solution to the above mentioned challenges and is being widely used in various industrial and academic research projects.
The proposed seminar aims at presenting the development context and needs that have fostered the creation of a methodology and a set of UML, SysML and MARTE model-based diagrams within the research and development work carried out EU funded MADES project [http://www.mades-project.org/] which aims to develop novel model-driven techniques to improve existing practices in development of RTES for avionics and surveillance embedded systems industries.
The seminar aims at highlighting the current practice and needs in real Avionics development case studies and in particular takes advantage of the vision of an avionics system integrator, highlighting the perspective of the different needs of its different customers within the Avionics industry that have been taken as a basis to build the methodology and the set of diagrams.
The MADES Project is expected to deliver important improvements in each phase of embedded systems development lifecycle by providing new tools and technologies that support design, validation, simulation, and code generation, while providing better support for component reuse.
MADES technologies are expected to reduce development costs of complex embedded systems for the Aerospace, Defence and other key European industries, while enabling a next generation of highly complex embedded systems to be developed that are more reliable, yet costing less to maintain and evolve as industry needs change and hardware capabilities increase.
This document provides a summary of an individual's professional experience in embedded automotive software development using AUTOSAR. It includes details on their education, technical skills, work experience with various automotive companies as a software engineer and technical leader specializing in areas like network design, communication stack development, integration and testing. It also lists their academic qualifications and achievements.
The document discusses a project to implement a distributed process control system with wireless accessibility. It describes the Process Control Studio software, which allows designing and monitoring industrial processes on a laptop or PDA. The software includes features like alarming, data storage, and a mobile edition. Wireless connectivity is provided via WiFi, and an Ethernet controller allows interfacing with local measurements and controls. The controller performs data acquisition from analog and digital sensors using an ADC and can control actuators with a DAC. It also implements on-off and PID control algorithms using a microcontroller. The goal is to provide localized wireless monitoring and control of industrial processes.
Sudha Madhuri has over 9 years of experience as a Software Professional and Scrum Master with expertise in C/C++, Java, and telecom domains including protocols, data handling, and billing. She has led projects for Tata Consultancy Services and Wipro Technologies as Project Leader, Scrum Master, Technical Coordinator, and Team Leader, delivering software for Ericsson in areas like switches, radio access networks, and VOIP gateways. Sudha holds a B.Tech in Electronics and Communications Engineering and is legally authorized to work in Canada.
The document summarizes the rationale and main contributions of a thesis on managing and analyzing bitstream generators for Xilinx FPGAs. The thesis proposes a novel framework for debugging and validating partial dynamic reconfiguration architectures on Xilinx FPGAs in a way that is independent of Xilinx software and automates constraint checking, error resolution, and exploration of reconfiguration possibilities. The framework includes modules for parsing designs, performing constraint and conflict analysis, and allowing design alterations through region redefinition and bitstream relocation. It is demonstrated on an image processing application with reconfigurable filters and detectors.
SDN-enhanced Services in Enterprises and Data CentersAnees Shaikh
The document discusses software-defined networking (SDN) and opportunities for using SDN to enhance network services in enterprises and data centers. It notes that while SDN controllers currently provide low-level APIs focused on network control, more work is needed to develop higher-level APIs and abstractions that can be consumed by applications and integrated with IT processes. The document presents examples of potential new network models and abstractions that could enable uses cases like network security management, application connectivity services, and workload migration.
The document proposes a framework called Rebit for analyzing and managing bitstream generators for partial dynamic reconfiguration (PDR) on Xilinx FPGAs. It aims to address issues with existing PDR flows, which require manual definition of reconfigurable regions (RRs) and have no guarantees that constraints will be satisfied. Rebit allows automated constraint checking, guided error resolution, and exploration of relocation possibilities to validate PDR designs independently of Xilinx software. It is demonstrated on a case study of an edge detection application with two reconfigurable modules.
MADES Seminar @ Laboratory of Model-Driven Engineering Applied to Embedded Sy...Alessandra Bagnato
-------
Lieu: salle 1073 (Nano-innov – Bat. 862)
Date: 24 Septembre 2012
Heure: 14:00 – 15:00
Orateur: Alessandra Bagnato
Titre: UML, SysML and MARTE in Use, a High Level Methodology for Real-time and Embedded Systems
-------
Résumé/Abstract
Rapid evolution of real-time and embedded systems (RTES) is continuing at an increasing rate, and new methodologies and design tools are needed to reduce design complexity while decreasing development costs and integrating aspects such as verification and validation. Model-Driven Engineering offers an interesting solution to the above mentioned challenges and is being widely used in various industrial and academic research projects.
The proposed seminar aims at presenting the development context and needs that have fostered the creation of a methodology and a set of UML, SysML and MARTE model-based diagrams within the research and development work carried out EU funded MADES project [http://www.mades-project.org/] which aims to develop novel model-driven techniques to improve existing practices in development of RTES for avionics and surveillance embedded systems industries.
The seminar aims at highlighting the current practice and needs in real Avionics development case studies and in particular takes advantage of the vision of an avionics system integrator, highlighting the perspective of the different needs of its different customers within the Avionics industry that have been taken as a basis to build the methodology and the set of diagrams.
The MADES Project is expected to deliver important improvements in each phase of embedded systems development lifecycle by providing new tools and technologies that support design, validation, simulation, and code generation, while providing better support for component reuse.
MADES technologies are expected to reduce development costs of complex embedded systems for the Aerospace, Defence and other key European industries, while enabling a next generation of highly complex embedded systems to be developed that are more reliable, yet costing less to maintain and evolve as industry needs change and hardware capabilities increase.
Soma Mishra is a senior software analyst with over 6 years of experience designing solutions for telecom mediation using the COMPTEL Eventlink tool. She has extensive experience in requirements gathering, design, testing, and support. Some of her projects include migrating an offline mediation system to COMPTEL Eventlink, implementing roaming and settlement streams, and processing VoLTE calls. She is proficient in Perl, Shell scripting, PL/SQL, and working with HP UNIX environments.
This document describes a unified functional verification approach for mixed analog-digital ASIC designs. It discusses using discrete-time models in VHDL to represent analog blocks and Verilog for digital blocks. Specman is used for random stimulus generation and coverage analysis. The approach is demonstrated on a voice codec chip with digital filters, ADCs, embedded DSP, and analog/digital interfaces. Separate analog and digital environments are unified to improve coverage and reduce duplication. A Simulink model is used as a fast DSP reference model.
Hardware-Software allocation specification of IMA systems for early simulationÁkos Horváth
This document describes a model-driven development tool for allocating system functionalities to integrated modular avionics (IMA) platforms. The tool uses models and transformations to perform allocation, enable early validation of design rules, and generate traceability links. It is based on open-source Eclipse modeling frameworks like EMF, EMF-IncQuery, and VIATRA and integrates with MATLAB Simulink models. Future work includes improving semi-automated allocation, supporting open-source technologies through the Polarsys initiative, and creating a standalone traceability framework. The tool aims to apply model-driven methods to help design integrated modular avionics systems.
Extending SDN beyond the control planeAnees Shaikh
1) SDN has made progress extending programmatic control to network packets and traffic, but network management remains device-centric without SDN principles.
2) The document proposes applying SDN concepts like centralized control, network abstractions and APIs, and standard protocols to network configuration management.
3) A key idea is defining vendor-neutral configuration data models using standards like YANG to provide a common way to manage multi-vendor networks through automation and standard interfaces.
1) The document describes DynaRIA, a tool for analyzing Ajax-based rich internet applications (RIAs). DynaRIA provides features for comprehension, testing, debugging, and quality assessment of RIAs.
2) Several case studies were conducted using DynaRIA to evaluate its effectiveness. Tasks like understanding features, detecting errors, and assessing quality were accomplished using DynaRIA's visualizations and analysis features.
3) DynaRIA was found to provide useful support for comprehension, testing, and quality analysis of RIAs. Future work involves expanded evaluation of DynaRIA's cognitive support and extending its analysis capabilities.
What are the different opportunities for a VLSI Front end Verification engineer? What career path exists and how to build a career path in Verification of VLSI chip designs?
Sharing my experiences and Career journey as Verification Engineer
This document provides a summary of Ranan Fraer's experience and qualifications. He has over 18 years of experience in software engineering for electronic design automation technologies at Intel, specializing in pre-silicon validation and power-performance analysis from circuit to system levels. He has expertise in formal verification, dynamic verification, transaction-level modeling, and microarchitectural performance analysis.
Neha Jain seeks a position where she can contribute to an organization's success through her skills. She has a Master's in VLSI Systems and Technology with a CGPA of 8.02. Her technical skills include Verilog HDL, SystemVerilog, C programming, and tools like Cadence and Xilinx. Her M.Tech project involved power analysis of a ring-based network-on-chip architecture. She has work experience as a design and verification engineer and has taught digital electronics courses.
Learn an overview of design trends and designer challenges, simulator extensions for models and abstraction levels in PSpice, and examples of a coding algorithm models into PSpice PCB level cycle
This document discusses accelerating verification of high-level synthesis (HLS) blocks using the JEDA HLV Tool Suite. It provides a new verification flow that allows identifying untested and dead code earlier at the SystemC/C-level, improving testbenches faster using faster C models. The JEDA tools provide hardware-aware coverage measurement at the SystemC level that reliably carries over to the RTL level, allowing for both fast time to RTL and efficient verification. This enables achieving true faster time to market by moving verification automation to the high level.
Advances in Verification - Workshop at BMS College of EngineeringRamdas Mozhikunnath
Day 1 of workshop at BMS college of Engineering
Covers SystemVerilog language fundamentals - Language constructs, building blocks, Arrays, Process, Classes
TRACK C: Methodology for Mixed Mode Design & Verification of Complex SoCs/ Ja...chiportal
This document discusses methodology for mixed mode design and verification of complex system-on-chips. It begins with examples of mixed signal SoCs including RF analog front ends and power management ICs. It then discusses the analog and digital design flows and lessons learned from mixed mode projects. Key lessons include the need for clear communication between analog and digital teams, respecting differences in their flows, phasing implementation to allow for changes, and reusing the digital verification environment for mixed mode verification. The conclusion emphasizes that mixed mode design and verification is an iterative team process.
An Approach to Overcome Modeling Inaccuracies for Performance Simulation Sig...Pankaj Singh
RNM is finding prominence in functional verification signoff, However there is clear modeling gap when it comes to performance simulation of high-speed SerDes. Sometimes the pre-silicon simulation results show passing results with respect to Jitter tolerance (JTOL) specification which may not match the actual silicon validation results. These performance issues manifest due to inaccuracies of model where it may not comprehend the actual circuit behavior. There is no clear methodology to overcome these model gaps for performance simulation signoff.
This paper discusses in detail the techniques used to accurately model and verify high-speed SerDes systems for performance simulation.
Qualifying a high performance memory subsysten for Functional SafetyPankaj Singh
Addressing the Challenges of Safety verification for LPDDR4.
✓Avoid traditional approach of starting functional safety after functional verification : Iterative and expensive development phase
1. Functional Safety Need to be Architected and not added later.
2. Safety Analysis must start prior to implementation. ‘Design for safety/verification’
3. Reuse & Synergize : Nominal and Functional Safety Verification.
✓Fault optimization with formal and other techniques is necessary to overcome challenges with scaling simulation and analysis.
✓Integrated push button fault simulation flow is need of hour and saves verification engineers time.
✓Analog defect modelling and coverage can be performed based on IEEE P2427.
The document discusses the Adaptive MILS Evidential Tool Bus (AM-ETB) which is used to create and maintain certification evidence for adaptive MILS systems. The AM-ETB uses assurance case patterns to develop modular assurance cases. It coordinates the execution of verification tools to generate evidence and update assurance cases. The AM-ETB implementation includes a pattern repository, evidence repository, workflow engine, tool agents, and assurance case repository.
The document discusses an Audi telematics project in collaboration with IBM. IBM provided the overall architecture, components for the telematics control unit, and project management. The goal was to develop an end-to-end telematics prototype integrating the vehicle with external content and applications through a wireless gateway. IBM's architecture offered flexibility, security, and integration of the vehicle with the internet and wireless networks. The project helped build the foundation for Audi's telematics platform and global leadership position.
Qiang Yu is a software engineer with over 13 years of experience developing embedded real-time systems using C/C++. He has worked across several sectors including data storage, railway, security, oil and gas, and IoT. His specialties include agile development, architecture design, C/C++, Linux, networking, and wireless technologies. Recent roles include developing frameworks for oil and gas tools at Schlumberger, low power wireless communications for well monitoring at Expro, and railway signaling simulation and modeling at Atkins.
Tool-Driven Technology Transfer in Software EngineeringHeiko Koziolek
This talk presentst the tool-driven technology transfer process ABB Corporate Research applies in selected software engineering University collaborations. As an example, we have created an add-in to a popular UML tool and developed the tooling in close interaction with the target users. Centering the technology transfer around tool implementations brings many benefits such as the need to make conceptual contributions applicable and the ability to quickly benefit from the new concepts. A challenge to this form of technology transfer is the long-term commitment to the maintenance of the tooling, which we try to address by creating an open developer community. Tool-driven technology transfer projects have proven to be valuable a instrument of bringing advanced software engineering technologies into our organization.
- Ankit Sarin has over 7 years of experience in embedded firmware development, hardware design, and integration testing. He has worked on projects in various domains including industrial automation, SCADA, rail, oil and gas, and consumer products.
- His skills include embedded C/C++, assembly language, various protocols and interfaces. He has experience with development tools and environments on 8/16/32 bit platforms.
- His most recent role is as a senior software engineer at Larsen & Toubro where he works on firmware development for solar inverters and railway products. Previously he has worked on projects for Invensys, Cognizant, and Philips.
Ahmed Hassan Moustafa Mahmoud is seeking a job in the technology sector with experience in LTE protocol stack software engineering and embedded software development. He has over 9 years of experience in these fields, most recently as an LTE RRC protocol stack software engineer at Intel Mobile Communications in India and previously in Egypt. Prior to that, he held embedded software roles at El Sewedy Electrometer Egypt including as an embedded software team leader and senior embedded software engineer. He has a Bachelor's degree in Electronics and Communications Engineering from Cairo University.
Soma Mishra is a senior software analyst with over 9 years of experience in software analysis, design, testing, and maintenance. She has expertise in solution architecture, business analysis, requirement gathering, and project management. Her skills include system configuration, software analysis, solution designing, and unit testing. She is proficient in technologies like Oracle, PL/SQL, UNIX, and has worked on projects involving roaming management systems and telecom mediation.
Soma Mishra is a senior software analyst with over 6 years of experience designing solutions for telecom mediation using the COMPTEL Eventlink tool. She has extensive experience in requirements gathering, design, testing, and support. Some of her projects include migrating an offline mediation system to COMPTEL Eventlink, implementing roaming and settlement streams, and processing VoLTE calls. She is proficient in Perl, Shell scripting, PL/SQL, and working with HP UNIX environments.
This document describes a unified functional verification approach for mixed analog-digital ASIC designs. It discusses using discrete-time models in VHDL to represent analog blocks and Verilog for digital blocks. Specman is used for random stimulus generation and coverage analysis. The approach is demonstrated on a voice codec chip with digital filters, ADCs, embedded DSP, and analog/digital interfaces. Separate analog and digital environments are unified to improve coverage and reduce duplication. A Simulink model is used as a fast DSP reference model.
Hardware-Software allocation specification of IMA systems for early simulationÁkos Horváth
This document describes a model-driven development tool for allocating system functionalities to integrated modular avionics (IMA) platforms. The tool uses models and transformations to perform allocation, enable early validation of design rules, and generate traceability links. It is based on open-source Eclipse modeling frameworks like EMF, EMF-IncQuery, and VIATRA and integrates with MATLAB Simulink models. Future work includes improving semi-automated allocation, supporting open-source technologies through the Polarsys initiative, and creating a standalone traceability framework. The tool aims to apply model-driven methods to help design integrated modular avionics systems.
Extending SDN beyond the control planeAnees Shaikh
1) SDN has made progress extending programmatic control to network packets and traffic, but network management remains device-centric without SDN principles.
2) The document proposes applying SDN concepts like centralized control, network abstractions and APIs, and standard protocols to network configuration management.
3) A key idea is defining vendor-neutral configuration data models using standards like YANG to provide a common way to manage multi-vendor networks through automation and standard interfaces.
1) The document describes DynaRIA, a tool for analyzing Ajax-based rich internet applications (RIAs). DynaRIA provides features for comprehension, testing, debugging, and quality assessment of RIAs.
2) Several case studies were conducted using DynaRIA to evaluate its effectiveness. Tasks like understanding features, detecting errors, and assessing quality were accomplished using DynaRIA's visualizations and analysis features.
3) DynaRIA was found to provide useful support for comprehension, testing, and quality analysis of RIAs. Future work involves expanded evaluation of DynaRIA's cognitive support and extending its analysis capabilities.
What are the different opportunities for a VLSI Front end Verification engineer? What career path exists and how to build a career path in Verification of VLSI chip designs?
Sharing my experiences and Career journey as Verification Engineer
This document provides a summary of Ranan Fraer's experience and qualifications. He has over 18 years of experience in software engineering for electronic design automation technologies at Intel, specializing in pre-silicon validation and power-performance analysis from circuit to system levels. He has expertise in formal verification, dynamic verification, transaction-level modeling, and microarchitectural performance analysis.
Neha Jain seeks a position where she can contribute to an organization's success through her skills. She has a Master's in VLSI Systems and Technology with a CGPA of 8.02. Her technical skills include Verilog HDL, SystemVerilog, C programming, and tools like Cadence and Xilinx. Her M.Tech project involved power analysis of a ring-based network-on-chip architecture. She has work experience as a design and verification engineer and has taught digital electronics courses.
Learn an overview of design trends and designer challenges, simulator extensions for models and abstraction levels in PSpice, and examples of a coding algorithm models into PSpice PCB level cycle
This document discusses accelerating verification of high-level synthesis (HLS) blocks using the JEDA HLV Tool Suite. It provides a new verification flow that allows identifying untested and dead code earlier at the SystemC/C-level, improving testbenches faster using faster C models. The JEDA tools provide hardware-aware coverage measurement at the SystemC level that reliably carries over to the RTL level, allowing for both fast time to RTL and efficient verification. This enables achieving true faster time to market by moving verification automation to the high level.
Advances in Verification - Workshop at BMS College of EngineeringRamdas Mozhikunnath
Day 1 of workshop at BMS college of Engineering
Covers SystemVerilog language fundamentals - Language constructs, building blocks, Arrays, Process, Classes
TRACK C: Methodology for Mixed Mode Design & Verification of Complex SoCs/ Ja...chiportal
This document discusses methodology for mixed mode design and verification of complex system-on-chips. It begins with examples of mixed signal SoCs including RF analog front ends and power management ICs. It then discusses the analog and digital design flows and lessons learned from mixed mode projects. Key lessons include the need for clear communication between analog and digital teams, respecting differences in their flows, phasing implementation to allow for changes, and reusing the digital verification environment for mixed mode verification. The conclusion emphasizes that mixed mode design and verification is an iterative team process.
An Approach to Overcome Modeling Inaccuracies for Performance Simulation Sig...Pankaj Singh
RNM is finding prominence in functional verification signoff, However there is clear modeling gap when it comes to performance simulation of high-speed SerDes. Sometimes the pre-silicon simulation results show passing results with respect to Jitter tolerance (JTOL) specification which may not match the actual silicon validation results. These performance issues manifest due to inaccuracies of model where it may not comprehend the actual circuit behavior. There is no clear methodology to overcome these model gaps for performance simulation signoff.
This paper discusses in detail the techniques used to accurately model and verify high-speed SerDes systems for performance simulation.
Qualifying a high performance memory subsysten for Functional SafetyPankaj Singh
Addressing the Challenges of Safety verification for LPDDR4.
✓Avoid traditional approach of starting functional safety after functional verification : Iterative and expensive development phase
1. Functional Safety Need to be Architected and not added later.
2. Safety Analysis must start prior to implementation. ‘Design for safety/verification’
3. Reuse & Synergize : Nominal and Functional Safety Verification.
✓Fault optimization with formal and other techniques is necessary to overcome challenges with scaling simulation and analysis.
✓Integrated push button fault simulation flow is need of hour and saves verification engineers time.
✓Analog defect modelling and coverage can be performed based on IEEE P2427.
The document discusses the Adaptive MILS Evidential Tool Bus (AM-ETB) which is used to create and maintain certification evidence for adaptive MILS systems. The AM-ETB uses assurance case patterns to develop modular assurance cases. It coordinates the execution of verification tools to generate evidence and update assurance cases. The AM-ETB implementation includes a pattern repository, evidence repository, workflow engine, tool agents, and assurance case repository.
The document discusses an Audi telematics project in collaboration with IBM. IBM provided the overall architecture, components for the telematics control unit, and project management. The goal was to develop an end-to-end telematics prototype integrating the vehicle with external content and applications through a wireless gateway. IBM's architecture offered flexibility, security, and integration of the vehicle with the internet and wireless networks. The project helped build the foundation for Audi's telematics platform and global leadership position.
Qiang Yu is a software engineer with over 13 years of experience developing embedded real-time systems using C/C++. He has worked across several sectors including data storage, railway, security, oil and gas, and IoT. His specialties include agile development, architecture design, C/C++, Linux, networking, and wireless technologies. Recent roles include developing frameworks for oil and gas tools at Schlumberger, low power wireless communications for well monitoring at Expro, and railway signaling simulation and modeling at Atkins.
Tool-Driven Technology Transfer in Software EngineeringHeiko Koziolek
This talk presentst the tool-driven technology transfer process ABB Corporate Research applies in selected software engineering University collaborations. As an example, we have created an add-in to a popular UML tool and developed the tooling in close interaction with the target users. Centering the technology transfer around tool implementations brings many benefits such as the need to make conceptual contributions applicable and the ability to quickly benefit from the new concepts. A challenge to this form of technology transfer is the long-term commitment to the maintenance of the tooling, which we try to address by creating an open developer community. Tool-driven technology transfer projects have proven to be valuable a instrument of bringing advanced software engineering technologies into our organization.
- Ankit Sarin has over 7 years of experience in embedded firmware development, hardware design, and integration testing. He has worked on projects in various domains including industrial automation, SCADA, rail, oil and gas, and consumer products.
- His skills include embedded C/C++, assembly language, various protocols and interfaces. He has experience with development tools and environments on 8/16/32 bit platforms.
- His most recent role is as a senior software engineer at Larsen & Toubro where he works on firmware development for solar inverters and railway products. Previously he has worked on projects for Invensys, Cognizant, and Philips.
Ahmed Hassan Moustafa Mahmoud is seeking a job in the technology sector with experience in LTE protocol stack software engineering and embedded software development. He has over 9 years of experience in these fields, most recently as an LTE RRC protocol stack software engineer at Intel Mobile Communications in India and previously in Egypt. Prior to that, he held embedded software roles at El Sewedy Electrometer Egypt including as an embedded software team leader and senior embedded software engineer. He has a Bachelor's degree in Electronics and Communications Engineering from Cairo University.
Soma Mishra is a senior software analyst with over 9 years of experience in software analysis, design, testing, and maintenance. She has expertise in solution architecture, business analysis, requirement gathering, and project management. Her skills include system configuration, software analysis, solution designing, and unit testing. She is proficient in technologies like Oracle, PL/SQL, UNIX, and has worked on projects involving roaming management systems and telecom mediation.
IoT implementation with InduSoft Web Studio and TagWell from SoftPLC: SoftPLC...AVEVA
Pairing InduSoft Web Studio with SoftPLC Corporation's TagWell cloud platform is an effective way to bring systems into the new frontier of the Internet of Things and Machine to Machine communication. With SoftPLC’s TagWell, InduSoft Web Studio users can take advantage of native driver communications to effortlessly connect systems that range from wireless interfaces, to a cellular/satellite connected office-based SCADA, or distributed remote units to cloud-based SCADA systems.
This document is a resume for Christopher J. Reder. It summarizes his education, work experience, and technical skills. He has a B.S. in Electrical Engineering from Auburn University and over 15 years of experience in software engineering roles developing networking hardware and software. His experience includes work at Cisco Systems, Extreme Networks, Overture Networks, Hatteras Networks, Digital Concepts Inc., and ADTRAN Inc., where he has led projects, mentored other engineers, implemented new features, found and fixed bugs, and interfaced with customers.
Anand Patil has over 11 years of experience developing .NET and SQL applications. He currently works as a Technology Specialist at Honeywell Technology Solutions, where he designs and implements cloud services using C# and SQL. Previously, he worked at Integra Micro Systems as a Senior Engineer. He has expertise in .NET, WCF, XML, SQL Server, and agile methodologies. He holds an MTech from Birla Institute of Technology and Science and a BE from KLECET Belgaum under VTU.
This document provides a summary of Bikrama K.L's career experience and qualifications. He has over 12 years of experience in telecommunication product engineering including mobility management, call processing, SIP gateways, IP PBX, real-time analytics, virtualization, IMS, RCS and security. Currently working as a Solutions Architect, he has experience providing solutions to complex, large-scale product development and managing high-quality product deliveries. His experience in both technical and management domains allows him to oversee the full software delivery process from conceptualization to deployment.
Achhar Kalia has nearly 5 years of experience in application development, production support, and system integration. He has expertise in Linux/Unix administration, virtualization, databases, and networking. Some of his key skills include OpenStack, Oracle, DB2, networking protocols, and Ericsson products. He has worked on projects for clients such as Ericsson, Tata Consultancy Services, and Telstra involving the development, support and enhancement of various applications.
This document is a curriculum vitae for Anastasios Fakas. It provides his contact information, work experience, education, and skills. Fakas has over 20 years of experience as a software engineer and technical architect working with technologies like Java, Spring, Oracle, and Docker. His roles have included designing solutions, overseeing development teams, and ensuring best practices. He has worked on projects in industries such as telecom, banking, utilities, and manufacturing.
How to bring innovation to your organization by streamlining the deployment process ?
IaaS, PaaS or Docker containers are all valid methods that can be tailored for your needs. They each come with advantages and drawbacks, and are opposed each day by vendors and providers along. Should we really impose a standard for every team ?
Palladio Optimization Suite: QoS optimization for component-based Cloud appli...Michele Ciavotta, PH. D.
Presentation slides for the 9th EAI International Conference on Performance Evaluation Methodologies and Tools (VALUETOOS 2015) December 14–16, 2015 | Berlin, Germany.
The crux of the talk is the presentation of Palladio Optimization Suite.
Kumar Reddy Yenreddy is seeking a position utilizing his 4+ years of experience in embedded systems. He has experience in automotive and marine domains developing hardware and software, and testing embedded systems using tools like LabCar, CANoe and UDE. He is proficient in C, Perl, and tools like ORCAD and Keil, and has expertise in microcontrollers, CAN protocol, and analog/digital circuits. He holds a diploma in embedded systems from CDAC and a B.Tech in electronics from Vitam College of Engineering.
Nagesh Kalal has over 8 years of experience in software testing, including automation testing on Nutanix storage clusters, Cisco Nexus switches, and embedded software. He has expertise in test planning, execution, defect tracking, and automation using tools like Selenium, Python, and TCL scripting. Currently he is leading a team performing automation testing on Cisco Nexus switches using the PyATS framework.
Minh Doan Tien has over 5 years of experience as a Senior Automation Quality Engineer, specializing in test automation for web, telecommunications, and networking applications using languages like Python, Perl, and Bash shell. He has led and contributed to several automation test projects for companies like Harvey Nash and Alcatel-Lucent, ensuring high software quality through tasks like test planning, script development, and regression execution. His skills include test frameworks like Selenium and BDD, as well as protocols like TCP/IP, UMTS, and LTE.
Ray Ransdell has over 20 years of experience in information technology with expertise in Mac OS, Windows, Linux, networking, security, and productivity software. He has held senior technical roles at Seagate Technology and Invisible IT providing desktop support, security solutions, imaging and deployment, and training. Ransdell has also owned his own IT consulting firm and has extensive experience in project management, system design/integration, and mass deployment of hardware and software.
For the full video of this presentation, please visit: https://www.edge-ai-vision.com/2023/06/accelerating-newer-ml-models-using-the-qualcomm-ai-stack-a-presentation-from-qualcomm/
Vinesh Sukumar, Senior Director and Head of AI/ML Product Management at Qualcomm Technologies, presents the “Accelerating Newer ML Models Using the Qualcomm AI Stack” tutorial at the May 2023 Embedded Vision Summit.
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Dr. Bernd GRAHLMANN and NXP automating testing with Telelogic DOORS @ NXP presentation for Telelogic UGC France 20081126
1. Automating Testing with
Telelogic Doors @ NXP
Dr. Bernd GRAHLMANN – (www.grahlmann.net / bernd@grahlmann.net)
Requirements Engineering / Management / Development & Telelogic DOORS Expert / Trainer / Consultant
Joint work with MIFARE Plus Team (NXP Semiconductors, Caen & Gratkorn & Hamburg)
Business Line Identification, Business Unit Automotive and Identification
Telelogic User Conference 2008 – France (November 26, 2008)