Basically a summary attempt of "Data Movement Instructions" , chapter#4 of the book entitled "The Intel Microprocessors: Architecture, Programming, and Interfacing" by Barry B. Brey.

1. Data Movement
Instructions
Ref: The Intel Microprocessors |
Architecture, Programming, and Interfacing | Eighth
Edition | Barry B. Brey

2. OBJECTIVE
● Machine language introduction
● Instructions modes
● Assembly instructions breakdown
● Assembly instruction to machine code conversion

3. MOV Revisited
● used earlier to explain addressing modes
● will be now used to demonstrate machine language
instructions

4. Machine Language
● native (binary) code that microprocessor understands
● instructions for the 8086 through the Core2 may vary in
length from 1 to as many as 13 bytes
● no complete list of these variations
● as many as 100,000 variations of instructions

5. INSTRUCTION MODES
● 16-bit mode(DOS mode):
○ 8086 through the 80286 uses this form
○ compatible in upper versions(80386 and upper) as well if they are
programmed to do so
● 32-bit mode:
○ but needs to be prefixed as below:

6. INSTRUCTION MODES(cntnd)
● 80386 and above assume that all instructions are 16-bit
mode when operated in real mode
● in protected mode D-bit selects in between (16 or 32)
D = 0, instructions are 16-bit instructions
16-bit offset addresses and register
D = 1, 32 bit instructions, 32 bit offset, registers

7. INSTRUCTION MODES(cntnd)
● first two bytes are called Override Prefixes
● Address size(67H): modifies the size of the operand
address
● Register/Operand size(66H): modifies register size

8. INSTRUCTION MODES(cntnd)
● By default:
○ l6-bit instruction mode uses 8- and l6-bit registers and addressing
modes
○ 32-bit instruction mode uses 8- and 32-bit registers and addressing
modes
● prefixes basically overrides these defaults so that a
32-bit register can be used in the l6-bit mode and vice
versa
● selecting mode-of-operation depends on application
○ 32-bit mode: if 8 or 32 bit data dominates the app
○ 16-bit mode: if 8 or 16 bit data dominates the app
● mode selection is done by OS

9. INSTRUCTION MODES(cntnd)
● Example (32-bit mode):
○ mov <mem>, <reg>
○ possible combinations:
■ default:
● moves 32 bits from a 32 bit register to memory using 32 bit
address
■ if preceded by operand-size prefix
● moves 16 bits from a 16 bit register to memory using 32 bit
address
■ if preceded by address-size prefix
● moves 32 bits from a 32 bit register to memory using 16 bit
address
■ if preceded by both operand-size and address-size prefix
● moves 16 bits from a 16 bit register to memory using 16 bit
address

10. INSTRUCTION MODES(cntnd)
● Example (16-bit mode):
○ mov <mem>, <reg>
○ possible combinations:
■ default:
● moves 16 bits from a 16 bit register to memory using 16 bit
address
■ if preceded by operand-size prefix
● moves 32 bits from a 32 bit register to memory using 16 bit
address
■ if preceded by address-size prefix
● moves 16 bits from a 16 bit register to memory using 32 bit
address
■ if preceded by both operand-size and address-size prefix
● moves 32 bits from a 32 bit register to memory using 32 bit
address

11. OPCODE
● selects the operation to be executed(add, sub, etc)
● 1 or 2 bytes long
● first 6 bits of the first byte is binary opcode
● D represents direction (appears mainly in mov and
mov-alike operations)
● W represents Word (appears in all instructions)

12. OPCODE(cntnd)
● List of some opcodes*
Instruction opcode
ADD 000000dw
AND 001000dw
DAA 00100111
DAS 00101111
DIV 1111011w
JMP(short) 11101011
JMP(near) 11101001
JMP(far) 11101010
MOV 100010dw
*
see Appendix-B for full list

13. OPCODE(contnd)
● If D == 0, data flows to the R/M field from the REG field
● If D == 1, data flows to the REG field from the R/M field
REG R/M
R/M REG

14. OPCODE(contnd)
● If W == 0, data size is always a byte
● If W == 1, data size is WORD/DOUBLE-WORD
○ recall that how register-size prefix determines it

15. MOD
● specifies the addressing mode
● MOD → mode, REG → register, R/M → register/memory
● MOD selects the type of addressing and whether a
displacement is present with that type

16. MOD(CNTND)
16-bit
instruction
mode
32-bit
instruction
mode

17. MOD(16-bit instructions)
● 11 → register-addressing mode, R/M is literally a
register then
● {00, 01, 10} → memory-addressing mode,
○ 00 → MOV AL, [DI]
○ 01 → MOV AL, [DI + 2]
○ 10 → MOV AL, [DI + 1000H]

18. MOD(16-bit instructions)
● 8-bit displacements are sign-extended into 16-bit
displacements
● i.e.:
○ 00H–7FH (positive) → 0000H–007FH
○ 80H–FFH (negative) → FF80-FFFFH

19. MOD(32-bit instructions)
● gets selected by address-size override prefix or
operating mode of OS
● 8-bit displacements are sign-extended into 32-bit
displacements
● i.e.:
○ 00–7FH (positive) → 00000000–0000007FH
○ 80–FFH (negative) → FFFFFF80-FFFFFFFFH

20. Register Assignments
● recall that double-word are only available to the
80386-Core2
● this table is accountable for REG (in any case) and for
R/M (only when it stands for register i.e: MOD = 11)

21. R/M Memory Assignments
● this table is accountable for REG (in any case) and for
R/M (only when it stands for memory i.e: MOD = 00 | 01 |
10),
* see exercise-4 for special addressing
16-bit addressing mode 32-bit addressing mode

22. Example_1:2-Byte Instruction
● 8BECH:
○ let’s take it as a 16-bit instruction mode
○ not prefixed by 66H or 67H
○ so, first byte 8B is opcode
● Opcode := 100010 ⇒ MOV
● D := 1 ⇒ R/M → REG
● W := 1 ⇒ WORD
OPCODE D W
1 0 0 0 1 0 1 1

23. Example_1:2-Byte Instruction(cntnd)
● 8BECH:
○ second byte, EC
● MOD := 11 ⇒ R/M is register
○ i.e.: register to register addressing
● REG := 101 ⇒ BP(destination)
● R/M := 100 ⇒ SP(source)
MOD REG R/M
1 1 1 0 1 1 0 0

24. Example_1:2-Byte Instruction(cntnd)
● Let’s put it all together:
○ the instruction(8BECH):= MOVes a word from SP to BP
○ i.e.: MOV BP, SP
● self:
○ figure out the instruction if it was operated in 32-bit instruction
mode and match your answer with the given one after going through
each step:
○ Answer: MOV EBP, ESP

25. Example_2:3-Byte Instruction
● 668BE8H:
○ let’s take it as a 16-bit instruction mode
○ prefixed by 66H(register-size override prefix)
■ so, 32 bit register operand
○ so, second byte 8B is opcode
● Opcode := 100010 ⇒ MOV
● D := 1 ⇒ R/M → REG
● W := 1 ⇒ DOUBLE-WORD
OPCODE D W
1 0 0 0 1 0 1 1

26. Example_2:3-Byte Instruction(cntnd)
● 668BE8H:
○ third byte, E8
● MOD := 11 ⇒ R/M is register
○ i.e.: register to register addressing
● REG := 101 ⇒ EBP(destination)
● R/M := 000 ⇒ EAX(source)
MOD REG R/M
1 1 1 0 1 0 0 0

27. Example_2:3-Byte Instruction(cntnd)
● Let’s put it all together:
○ the instruction(668BE8H):= MOVes a double-word from EAX to EBP
○ i.e.: MOV EBP, EAX
● self:
○ figure out the instruction if it was operated in 32-bit instruction
mode and match your answer with the given one after going through
each step:
○ Answer: MOV BP, AX

28. Example_3:2-Byte Instruction
● 8A15H:
○ let’s take it as a 16-bit instruction mode
○ not prefixed by 66H or 67H
○ so, first byte 8A is opcode
● Opcode := 100010 ⇒ MOV
● D := 1 ⇒ R/M → REG
● W := 0 ⇒ BYTE
OPCODE D W
1 0 0 0 1 0 1 0

29. Example_3:2-Byte Instruction(cntnd)
● 8A15H:
○ second byte, 15
● MOD := 00 ⇒ R/M is memory with no displacement
○ i.e.: memory to register addressing
● REG := 010 ⇒ DL(destination)
● R/M := 101 ⇒ DS:[DI](source)
MOD REG R/M
0 0 0 1 0 1 0 1

30. Example_3:2-Byte Instruction(cntnd)
● Let’s put it all together:
○ the instruction(8A15H):= MOVes a byte from memory addressed by
DS:[DI] to DL
○ i.e.: MOV DL, DS:[DI]

31. Example_4:Special Addressing
● if an instruction has only a displacement
○ MOD field contains 00 and R/M contains 110(DS:[BP])

32. Example_4:Special Addressing(cntnd)
● 88160010H:
○ let’s take it as a 16-bit instruction mode
○ not prefixed by 66H or 67H
○ so, first byte 88 is opcode
● Opcode := 100010 ⇒ MOV
● D := 0 ⇒ R/M ← REG
● W := 0 ⇒ BYTE
OPCODE D W
1 0 0 0 1 0 0 0

33. Example_4:Special Addressing(cntnd)
● 88160010H:
○ second byte, 16
● MOD := 00 ⇒ R/M is memory
○ invalid: with no displacement
○ Valid: with displacement to data
segment
MOD REG R/M
0 0 0 1 0 1 1 0

34. Example_4:Special Addressing(cntnd)
● 88160010H:
○ second byte, 16
● REG := 010 ⇒ DL(destination)
● R/M := 110 ⇒ DS:[BP](source)
MOD REG R/M
0 0 0 1 0 1 1 0

35. Example_4:Special Addressing(cntnd)
● 88160010H:
○ third and fourth byte, 0010(little endian)
● Displacement := 1000H
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 0

36. Example_4:Special Addressing(cntnd)
● Let’s put it all together:
○ the instruction(88160010H):= MOVes a byte from register DL into data
segment memory location 1000H
○ i.e.: MOV [1000H], DL

37. Example_5:Special Addressing
● if an instruction has BP addressing mode(i.e: contains
R/M code 110)
○ there will always be a displacement
○ adds 0 if no displacement is specified
○ example: MOV [BP], DL turns into MOV [BP + 0], DL

38. Example_5:Special Addressing(cntnd)
● 885600H:
○ let’s take it as a 16-bit instruction mode
○ not prefixed by 66H or 67H
○ so, first byte 88 is opcode
● Opcode := 100010 ⇒ MOV
● D := 0 ⇒ R/M ← REG
● W := 0 ⇒ BYTE
OPCODE D W
1 0 0 0 1 0 0 0

39. Example_5:Special Addressing(cntnd)
● 885600H:
○ second byte, 56
● MOD := 01 ⇒ R/M is memory
○ 8 bit displacement
● REG := 010 ⇒ DL(destination)
● R/M := 110 ⇒ DS:[BP](source)
MOD REG R/M
0 1 0 1 0 1 1 0

40. Example_5:Special Addressing(cntnd)
● 885600H:
○ third byte, 00(little endian)
● Displacement := 00H
0 0 0 0 0 0 0 0

41. Example_5:Special Addressing(cntnd)
● Let’s put it all together:
○ the instruction(885600H):= MOVes a byte from register DL into data
segment memory location pointed by BP plus displacement 00H
○ i.e.: MOV [BP], DL
○ i.e: MOV [BP + 0], DL

42. Exercise
● Convert the following machine codes into assembly
instruction(consider both 16 and 32-bit instruction
mode):
○ 8B07H
○ 8B9E004CH
○ 8A5501H
○ 8A750010H
○ 88160010H
○ 885600H

43. Exercise
● Write down the corresponding machine code for the
instructions given below(both in 16 and 32-bit
instruction mode):
○ mov ah, dh
○ MOV SI,[BX+2]
○ MOV ESI,[EAX]
○ MOV DL, [DI+1000H]
○ MOV DL, [DI+1H]
○ MOV [1000H],DL
○ MOV [BP],DL