Model checking in the cloud --
Cloud computing where computing is provided as a utility is finally a reality. This new paradigm is shaping the way hardware and software is designed. One of the main attractions of the cloud is its elasticity. This empowers users with the ability to dynamically change their hardware requirements by paying for resource usage by the hour. Compute-intensive applications such as model checking can potentially benefit from such an infrastructure. In this panel, we will address the following questions:
- How can model checking leverage the advantages of distributed and multi-core systems in the cloud?
o Is this new paradigm suitable for model checking?
o What are possible solutions beyond an “embarrassingly parallel” approach of running a single property per core?
o Is there a specific subset of properties that might be more suitable to this form of analysis?
- What is needed from the research and engineering community to achieve adoption within the next 5 years?
- Would a drive to model checking in the cloud increase the industry’s adoption of formal technology?
- What issues need to be addressed for design houses to adopt this technology and will the current license model of EDA tools change to adapt to the new requirements?
High-Level Synthesis Skill Development Needs - IEDECJack Erickson
Presentation at the March 2013 IEDEC conference in Santa Clara, CA. Outlines the need for hardware design to move up in abstraction to SystemC and high-level synthesis, and the main barrier left preventing this - a rare combination of skills. The best place to address this skill set gap is in university curricula.
Cinemeccanica and Cisco have been able to face the Digital Cinema Market with the new WorldWide (DCS) Digital Cinema Solution that exactly matches the actual and future expectations
Model checking in the cloud --
Cloud computing where computing is provided as a utility is finally a reality. This new paradigm is shaping the way hardware and software is designed. One of the main attractions of the cloud is its elasticity. This empowers users with the ability to dynamically change their hardware requirements by paying for resource usage by the hour. Compute-intensive applications such as model checking can potentially benefit from such an infrastructure. In this panel, we will address the following questions:
- How can model checking leverage the advantages of distributed and multi-core systems in the cloud?
o Is this new paradigm suitable for model checking?
o What are possible solutions beyond an “embarrassingly parallel” approach of running a single property per core?
o Is there a specific subset of properties that might be more suitable to this form of analysis?
- What is needed from the research and engineering community to achieve adoption within the next 5 years?
- Would a drive to model checking in the cloud increase the industry’s adoption of formal technology?
- What issues need to be addressed for design houses to adopt this technology and will the current license model of EDA tools change to adapt to the new requirements?
High-Level Synthesis Skill Development Needs - IEDECJack Erickson
Presentation at the March 2013 IEDEC conference in Santa Clara, CA. Outlines the need for hardware design to move up in abstraction to SystemC and high-level synthesis, and the main barrier left preventing this - a rare combination of skills. The best place to address this skill set gap is in university curricula.
Cinemeccanica and Cisco have been able to face the Digital Cinema Market with the new WorldWide (DCS) Digital Cinema Solution that exactly matches the actual and future expectations
CWC-AE provides the most widely-installed FTI system in the world with more flight hours than any other. We lower risk by supplying COTS hardware that has been proven on every platform type in all environmental conditions and delivers data reliably every time thanks to its ‘works once, works always’ finite state machine construction. The COTS design results in short lead times ensuring the hardware is delivered quickly.
Get a Pretested, Validated Infrastructure
Cisco and NetApp have collaborated to create FlexPod, a prevalidated data center solution built on a flexible, shared infrastructure. This predesigned base configuration can:
Scale easily
Be optimized for a variety of mixed application workloads
Be configured for virtual desktop or server infrastructure, secure multi-tenancy, or cloud environments
Improved efficiency & reliability for servers using immersion cooling technologyASQ Reliability Division
Data centers have traditionally been high power consumers. In a “green” data center, instead of being air-cooled, servers are submerged in a non-toxic dielectric fluid that is 1200 times more effective at whisking away heat. By using state of the art liquid immersion cooling, the power required to run each server is reduced by up to 50% and the power required to cool a server room is reduced by up to 90%. For perspective, power costs represent from 25-40% of monthly data center operating expenses. Any energy expended other than that to drive the IT Load contributes to inefficiency.
Immersion technology largely eliminates the temperature swings that can lead to processor and electronics failures. Micro-arcing is also eliminated as a concern since there is no dust or oxygen in the oil environment. There is also a potential to further mitigate against tin whisker failures since the bath could break whiskers or coat them to prevent shorts. Risk of failure due to airborne contaminants like dust, debris, and corrosive gases is eliminated. The improved heat dissipation of immersion technology also allows comfortable operation of cutting-edge, higher powered servers. So, an immersion cooled data center draws much less power and consequently has a smaller carbon footprint than conventional data centers.
Preparing a server for immersion is fairly straightforward. Simply remove the fans, replace any thermal paste with foil, and encapsulate the boot disk or use a solid state drive ( SSD). Working on a server is equally straightforward. Pull the server out of the fluid and wait for it to drain. Keep a nearby paper towel for any drips.
Solace Systems The Evolution of Messaging The Rise of the ApplianceIosif Itkin
Solace Systems The Evolution of Messaging The Rise of the Appliance
Clive Andrews
Mat Hobbis
Obninsk, 2 March, 2013
LSE The focus beyond Low Latency
EXTENT Trading Technology Trends & Quality Assurance
Convert Altera Xilinx FPGA to BaySand mcFPGAEBBM, Inc.
Convert your existing FPGA to BaySand platform in less than 10 weeks! drop-in replacements for STratix, Cyclone, Arria, Virtex, Kintex, artix, and Spartan devices. One platform for all your FPGA, ASIC, and SOC needs
CWC-AE provides the most widely-installed FTI system in the world with more flight hours than any other. We lower risk by supplying COTS hardware that has been proven on every platform type in all environmental conditions and delivers data reliably every time thanks to its ‘works once, works always’ finite state machine construction. The COTS design results in short lead times ensuring the hardware is delivered quickly.
Get a Pretested, Validated Infrastructure
Cisco and NetApp have collaborated to create FlexPod, a prevalidated data center solution built on a flexible, shared infrastructure. This predesigned base configuration can:
Scale easily
Be optimized for a variety of mixed application workloads
Be configured for virtual desktop or server infrastructure, secure multi-tenancy, or cloud environments
Improved efficiency & reliability for servers using immersion cooling technologyASQ Reliability Division
Data centers have traditionally been high power consumers. In a “green” data center, instead of being air-cooled, servers are submerged in a non-toxic dielectric fluid that is 1200 times more effective at whisking away heat. By using state of the art liquid immersion cooling, the power required to run each server is reduced by up to 50% and the power required to cool a server room is reduced by up to 90%. For perspective, power costs represent from 25-40% of monthly data center operating expenses. Any energy expended other than that to drive the IT Load contributes to inefficiency.
Immersion technology largely eliminates the temperature swings that can lead to processor and electronics failures. Micro-arcing is also eliminated as a concern since there is no dust or oxygen in the oil environment. There is also a potential to further mitigate against tin whisker failures since the bath could break whiskers or coat them to prevent shorts. Risk of failure due to airborne contaminants like dust, debris, and corrosive gases is eliminated. The improved heat dissipation of immersion technology also allows comfortable operation of cutting-edge, higher powered servers. So, an immersion cooled data center draws much less power and consequently has a smaller carbon footprint than conventional data centers.
Preparing a server for immersion is fairly straightforward. Simply remove the fans, replace any thermal paste with foil, and encapsulate the boot disk or use a solid state drive ( SSD). Working on a server is equally straightforward. Pull the server out of the fluid and wait for it to drain. Keep a nearby paper towel for any drips.
Solace Systems The Evolution of Messaging The Rise of the ApplianceIosif Itkin
Solace Systems The Evolution of Messaging The Rise of the Appliance
Clive Andrews
Mat Hobbis
Obninsk, 2 March, 2013
LSE The focus beyond Low Latency
EXTENT Trading Technology Trends & Quality Assurance
Convert Altera Xilinx FPGA to BaySand mcFPGAEBBM, Inc.
Convert your existing FPGA to BaySand platform in less than 10 weeks! drop-in replacements for STratix, Cyclone, Arria, Virtex, Kintex, artix, and Spartan devices. One platform for all your FPGA, ASIC, and SOC needs
Triad Semiconductor Analog and Mixed Signal ASIC Company OverviewTriad Semiconductor
Triad Semiconductor, www.triadsemi.com, designs and manufactures analog and mixed-signal custom IC solutions. We support customers in consumer, automotive, industrial, medical and defense markets. Learn how to get your products to market quickly (we've gone from kickoff to working silicon in 60 days), how to fix problems quickly and inexpensively (we've fixed problems in hours that take others months), and how to ship cost effectively (our customers are shipping over 50-million devices per year using our Agile ASIC™ technology).
Cisco UCS Integrated Infrastructure for Big Data with CassandraDataStax Academy
With growing popularity of big data, it becomes imperative for enterprises to adopt the right platform for their workload, with efficient and user-friendly management of large scale clusters. In this session we will explore Cisco's revolutionary innovations that deliver leading-edge infrastructure, well suited for Cassandra like data base platforms, purpose built for performance and scalability. This enables our customers to unlock the intelligence in their data. Not only this provides a sustainable competitive advantage to their business, but also scales with their growing business needs.
System on Chip is a an IC that integrates all the components of an electronic system. This presentation is based on the current trends and challenges in the IP based SOC design.
Traditional vs. SoC FPGA Design Flow A Video Pipeline Case StudyAltera Corporation
This presentation compares the impact of traditional FPGA engineering design flow to one employed with an SoC FPGA. The two approaches will be contrasted in terms of their impacts on system architecture design, debugging, risk mitigation, system integration, bring-up, feature enhancements, design obsolescence, and engineering effort. A case study is presented that explores these impacts within a video pipeline development effort.
It’s hard to focus when there is an 800 lb. gorilla in the room, for supply chain executives the gorilla is the potential dearth of supply chain professionals. However, they may not have to worry as much as they thought. Read more:
Avnet Embedded helps customers optimize scarce engineering resources by providing a variety of coverage models for Level I, II and III call center support. This support allows companies to devote their engineering talent to higher value activities, such as intellectual property development and solution differentiation. At the same time, companies can be assured that their customers are receiving world-class support from fully-trained call center agents who are deeply familiar with the system or solution they are supporting.
This guide simplifies application design and accelerates time-to-market by defining basic, system-level Interconnect, Passive and Electromechanical (IP&E)building blocks. In addition, the guide provides a “who’s who” of IP&E technology manufacturers and demonstrates how Avnet can meet a full breadth of product requirements and, in the process, add exceptional value to our customers.
This issue of AXIOM is dedicated to processing and power and in these pages we bring together a team of industry experts to talk about what you need to know in these areas. Avnet’s advanced architechtures expert Jim Carver gets to the heart of the ARM processor cores – explaining the history of ARM’s first offering through the current ecosystem of products, as well as and their functionality. And because no one likes to be in the dark, Chris Ammann explains why it is so critical for FPGA designers to plan for their board power at the beginning of the design process. Doug Geisler looks at how industrial OEMs have started to act like consumer electronics companies, or the “consumerization” of the market, and outlines the benefits and challenges to this new experience.
Avnet Service Brief: Thermal Management
Many sophisticated silicon components cannot function properly without effective heat dissipation. Avnet offers custom assembly and modification for cooling fans and heat sinks. In fact, Avnet is one of the world’s largest producers of thermal management products, shipping millions of cooling fans, blowers and heat sinks each year through the Avnet Logistics Solution Center (LSC).
It’s been a year since Avnet introduced the ZedBoard, a community-oriented development kit for the Xilinx, Inc. Zynq™- 7000 Extensible Processing Platform. And what a year it’s been!
A white paper by Jim Beneke, VP, Global Technical Marketing, Avnet Electronics Marketing, that explains the challenges faced in creating an industrial PCAP touch display and the advantages that Avnet kits bring to the industrial design community.
Avnet Electronics Marketing ushers in the summer solstice with a white paper detailing the Fundamentals of Photovoltaic Solar Technology for Battery Powered Applications. Find more solar applications from Avnet at www.em.avnet.com/solar
Avnet's free, supply chain diagnostic tool enables customers to model the true cost savings they will experience by adding Avnet as their supply chain partner.
What You Can Expect
»»Full-day, multi-track technical seminars featuring:
--How-to training for FPGA, DSP, and embedded systems designers
--An array of 70-minute training courses
--Practical, real-world design examples
--In-depth training on design solutions for FPGA
circuitry and the surrounding components
--Specialized 7-Series and Zynq™ solutions training
»»Partner demonstrations and exhibits
COMING TO A CITY NEAR YOU!
From May through October 2012, Avnet and Xilinx will co-host
X-fest technical training events throughout Asia, Europe,
North America and Japan.
Learn more at www.em.avnet.com/xfest
Many common electronic devices rely on antennas to communicate
wirelessly. Antennas are transducers that convert electromagnetic waves
to electric current or vice versa. Antennas can be used in outer space,
underwater, rock, or soil. Most common applications use air as the typical
propagation medium.
While it takes many years to become an expert antenna designer, several
basic antenna specifications are described to enable a starting point for
antenna selection. Standard antenna solutions are also presented for several
common applications.
Avnet, Inc. 2010 Analyst Day & 50th Anniversary Celebration: Dec 15, 2010
Presenters included: Roy Vallee, chairman and chief executive officer; Rick Hamada, president and chief operating officer; Ray Sadowski, senior vice president and chief financial officer; Harley Feldberg, president, Electronics Marketing; and Phil Gallagher, president, Technology Solutions.
Following the analyst day event, Avnet commemorated its 50th anniversary on the New York Stock Exchange by ringing the closing bell.
Avnet, Inc. 2010 Analyst Day & 50th Anniversary Celebration: Dec 15, 2010
Presenters included: Roy Vallee, chairman and chief executive officer; Rick Hamada, president and chief operating officer; Ray Sadowski, senior vice president and chief financial officer; Harley Feldberg, president, Electronics Marketing; and Phil Gallagher, president, Technology Solutions.
Following the analyst day event, Avnet commemorated its 50th anniversary on the New York Stock Exchange by ringing the closing bell.
Avnet, Inc. 2010 Analyst Day & 50th Anniversary Celebration: Dec 15, 2010
Presenters included: Roy Vallee, chairman and chief executive officer; Rick Hamada, president and chief operating officer; Ray Sadowski, senior vice president and chief financial officer; Harley Feldberg, president, Electronics Marketing; and Phil Gallagher, president, Technology Solutions.
Following the analyst day event, Avnet commemorated its 50th anniversary on the New York Stock Exchange by ringing the closing bell.
Avnet, Inc. 2010 Analyst Day & 50th Anniversary Celebration: Dec 15, 2010
Presenters included: Roy Vallee, chairman and chief executive officer; Rick Hamada, president and chief operating officer; Ray Sadowski, senior vice president and chief financial officer; Harley Feldberg, president, Electronics Marketing; and Phil Gallagher, president, Technology Solutions.
Following the analyst day event, Avnet commemorated its 50th anniversary on the New York Stock Exchange by ringing the closing bell.
Avnet, Inc. 2010 Analyst Day & 50th Anniversary Celebration: Dec 15, 2010
Presenters included: Roy Vallee, chairman and chief executive officer; Rick Hamada, president and chief operating officer; Ray Sadowski, senior vice president and chief financial officer; Harley Feldberg, president, Electronics Marketing; and Phil Gallagher, president, Technology Solutions.
Following the analyst day event, Avnet commemorated its 50th anniversary on the New York Stock Exchange by ringing the closing bell.
Avnet Analyst Day 2010 Presentation 4 Technology Solutions
Avnet Secure Micro Solutions
1. Avnet Electronics Marketing, IBM and Endicott Interconnect (EI) are trusted and dependable supply sources
for electronics. US manufacturing facilities and logistics centers provide a highly secure solution, while DoMEStIC SuPPlIErS
delivering rapid turnaround on applications. IBM and EI products meet ISO, IPC and military specifications,
RoHS compliance, ITAR registration and are compatible with lead-free assembly processes.
Size, Weight and Power (SWaP) Challenges
Reducing system size, weight, and power (SWaP) is critical to the development of new applications for the
defense aerospace industry. By achieving reductions in the form factor and power consumption of today’s
military electronics, developers are able to improve mobility and extend operational life, enhancing the
overall viability of the product in the marketplace. Avnet Electronics Marketing, IBM and EI have partnered to
help customers leverage System-in-Package (SiP) technology to achieve SWaP goals; bring differentiated
products to market quickly and efficiently and to establish design and supply chain continuity.
Endicott Interconnect
EI is a leading developer of SiP products that integrate multiple IC, assembly and test technologies into modular IC packages. One such product optimized for
aerospace applications is the CoreEZ™. EI’s CoreEZ semiconductor package utilizes the HyperBGA® manufacturing platform to offer a thin core build-up flip chip
package with very dense core vias using a cost sensitive material set. The core via density provides 199 micron via-to-via core pitch resulting in an essentially
coreless structure, which can accommodate ASIC, FPGA and many other semiconductor solutions. EI also offers HyperBGA® packages that are composed of
materials that have passed NASA outgassing testing and are recommended for aerospace applications up to radiation tolerant.
IBM and Avnet
IBM and Avnet work closely together to implement IBM System-on-Chip (SoC) ASIC solutions. IBM’s proven ASIC design systems reduce chip count by combining
FPGAs and older ASICs on single chips. The integration and implementation of qualified sets of tools, libraries, cores and packages enable customers to predictably
design ASICs while closely managing risk. The IBM ASIC design system has been validated through ten generations of ASIC development and more than a thousand
designs, many done in collaboration with Avnet Engineering Services (AES).
Design & supply Chain expertise asiCs anD FounDry Custom paCkaging
»»Partnerships with IBM and others allow Avnet »»IBM’s leading-edge technologies, »»Proven high-quality, high-reliability and
to provide ASIC and FPGA solutions from including Si and SiGe, enable extremely high-performance ASIC/FPGA packaging
prototype to production through obsolescence high-performance, high-density designs
»»Turnkey SiP technical solutions
»»Avnet employs experienced engineers »» IBM IP portfolio includes
The
who expertly staff seven design centers high-speed serializer and deserializer (HSS)
»»Trusted design and packaging capability
across the United States to maximize cores, which feature ultra-low jitter generation »»Substrate & Module Design
efficiency and provide local support and enhanced jitter tolerance characteristics − Physical design
for significant performance advantages
»»Collaborations with customers have − High-speed, controlled impedance
yielded more than 2,000 ASIC and FPGA »»Trusted design and foundry capabilities − Mechanical layout for SiP (MCM)
designs and have helped Avnet establish − Electrical, mechanical and
a 100% first time right ASIC design
»»World-class design, implementation thermal modeling
and implementation track record and verification tools plus
industry-standard models »»Substrate Fabrication
»» every ASIC and FPGA design
With − 50 µm laser-drilled vias
engagement, customers are able to
»»Integrated design flow takes ASIC designs
from design entry and planning to the − 25/25 µm line width & space
leverage Avnet’s supply chain expertise − Embedded passive
silicon implementation of the design
»»Avnet has serviced the defense aerospace produced on IBM manufacturing lines − Cu/in/Cu cores
industry for more than 50+ years and »» Assembly
currently has supply chain solutions in
»»Established technology provider to the IC
place for many key, multi-generational defense aerospace industry through − Flip chip pitch down to 150 µm
Department of Defense (DoD) programs MPO and commercial engagements − Wirebond, 60 µm inline,
43 µm staggered
− Flip chip, wirebond, SMD on both sides
2. IBM ASICs and Foundry
IBM’s leading-edge technologies, including Si and SiGe, enable extremely high-performance, high-density designs. This technology portfolio is complemented by
Avnet Engineering Services’ design engineers and field application engineers (FAEs) who excel at explaining the strengths and challenges associated with myriad
custom logic architectures and are adept at taking customers through a variety of decision-making scenarios to explain the tradeoffs and benefits unique to each.
Together, Avnet and IBM are ready to help customers with diverse needs overcome specific SWaP challenges.
SA27E Cu11 Cu08 Cu65 Cu45
6th Generation 7th Generation 8th Generation 9th Generation 10th Generation
ASIC Design System ASIC Design System ASIC Design System ASIC Design System ASIC Design System
SiP Benefits & SWaP reductions
The push for miniaturization and lightweight, portable computing power has led to breakthroughs in
high-performance electronics packaging by companies such as EI.
»»
Organic substrates enable more functionality in »»
Reduction in trace length increases
smaller packages electrical performance
»»
Integration of multiple devices into a single package, »»
Reduction in signal path length between
including pre-packaged ICs, surface mount die lowers inductance
components, memory, passives and connectors,
increases reliability and reduces weight »» become less complex or can be
PCBs
eliminated entirely
30x rEDuCtIoN IN SIZE - 90% rEDuCtIoN IN WEIGHt
From original pCB 670 cm2
to redesigned sip 25 cm2
Top
Components: 2-sided assembly
»» flip chip bare die
5
»» memory
CSP 3-4-3 construction
»» Passives CoreeZ® substrate
»» components
SMT
»» connector
PGA Bottom
8 7 7 - A S I C 4 1 1 ( 2 7 4 - 2 4 1 1 )»
www.em.avnet.com
www.em.avnet.com/asic