Arbiters are electronic circuits that allocate access to shared resources such as buses or memories. There are two main arbitration disciplines: static priority, which prioritizes requests based on input port number, and round robin, which cycles through requests in order. Synchronous arbiters use a daisy chain of priority cells to grant the request of highest priority, while asynchronous arbiters prevent multiple operations from occurring simultaneously to avoid metastability. Round robin arbiters allow every requester to take turns in fixed time slots.

1. ARBITERS
Submitted By
ANJANA J S
S1 MTECH VLSI
AM.EN.P2VLD16004

2. INTRODUCTION
• Arbiters are electronic devices that allocate access to shared
resources.
• Typical shared resources are busses, memories and multipliers
• Arbiter circuits may be synchronous or asynchronous.
• There are two main arbitration disciplines:
1. Static Priority - based on input port number.
2. Round Robin - based on last user.

3. BUS ARBITER
• Used in a multi-master bus system to decide which bus master
will be allowed to control the bus for each bus cycle.
• The most common kind is the memory arbiter.
• Memory arbiter - Used to decide, for each memory cycle,
which CPU will be allowed to access the shared memory.

4. BUS ARBITER
•Device that wishes to use the bus sends a request to arbiter
•Arbiter selects one request and grants the bus to the
corresponding device

7. SYNCHRONOUS ARBITERS
• It is a simple circuit that consists of a “daisy chain” of arbiter
cells.
• The arbiter grants a resource to the requester of the highest
priority.
• Each arbiter cell receives a grant input signal from the next
higher priority cell.
• If this signal is active, and if the cell’s request signal is true,
the cell activates its ack output signal, and negates the grant
signal to the next lower priority cell.
• If the request signal is false, the cell passes the grant signal to
the next cell.

8. FIG: Simplified arbiter and single cell

9. ASYNCHRONOUS ARBITERS
• Used in asynchronous circuits.
• Used to select order of access to a shared resource among
asynchronous requests.
• Function: To prevent 2 operations from occurring at once
when they should not.

10. FIG: 2 bit input arbiter circuit

11. • This circuit works only two input (R1=0,and R2 =1) and (R1=1,and R2= 0)
and gives result in form of G1 and G2.
• For the condition of R1=0 and R2=1 it gives G2 =1 it means when request
(R2) is high than grant (G2=1) will be high and for condition of R2=0 and
R1=1 it gives output as G1=1,it means when request (R1) is high than grant
(G1=1)will be high .
• If both requests occur at the same time, the circuit becomes metastable, with
the outputs of both NAND gates being at halfway between the supply voltage
and ground. While these “undefined” values exist, the circuit will keep the
granting signals at logical ‘0’.
• Eventually, one of the metastable sides of the circuit will settle to a voltage
past the threshold voltage of the transistor, forcing one of the grant signals
high and the other grant signal low.
• Thus a “decision” is made as to which request to grant.

12. • If two requests arrive at an arbiter within a few
picoseconds of each other, the circuit may become meta-
stable before reaching one of its stable states.
METASTABILITY

13. PRIORITY ARBITERS
• Each bit cell has one grant output and one request input.
• The current request (lower priority) only will be served if the
previous request (higher priority) has not appeared or been
served already.

14. Design
module
arbiter(gnt3,gnt2,gnt1,gnt0,req3,req2,req1,req
0,clk,rst);
output reg gnt3,gnt2,gnt1,gnt0;
input req3,req2,req1,req0;
input clk,rst;
parameter idle=3'b000;
parameter GNT3=3'b001;
parameter GNT2=3'b010;
parameter GNT1=3'b011;
parameter GNT0=3'b100;
reg [2:0] state,next_state;

15. always @ (posedge clk)
begin
if(rst)
state=idle;
else
state=next_state;
end
always @ (state,req3,req2,req1,req0)
begin
next_state=3’b000;
case (state)
idle:begin
if(req0)
next_state=GNT0;
else if(req1)
next_state=GNT1;
else if(req2)

16. next_state=GNT2;
else if(req3)
next_state=GNT3;
else
next_state=idle;
end // case: idle
GNT0:begin
if(req0)
next_state=GNT0;
else
next_state=idle;
end
GNT1:begin
if(req1)
next_state=GNT1;
else
next_state=idle;
end

17. GNT2:begin
if(req2)
next_state=GNT2;
else
next_state=idle;
end
GNT3:begin
if(req3)
next_state=GNT3;
else
next_state=idle;
end
endcase // case (state)
end // always @ (state,req3,req2,req1,req0)

18. always @ (state)
begin
if(state==idle)
begin
gnt3=0;
gnt2=0;
gnt1=0;
gnt0=0;
end
else if(state==GNT0)
begin
gnt3=0;
gnt2=0;
gnt1=0;
gnt0=1;
end
else if(state==GNT1)
begin
gnt3=0;
gnt2=0;

19. gnt1=1;
gnt0=0;
end
else if(state==GNT2)
begin
gnt3=0;
gnt2=1;
gnt1=0;
gnt0=0;
end
else if(state==GNT3)
begin
gnt3=1;
gnt2=0;
gnt1=0;
gnt0=0;
end
end // always @ (state)
endmodule // arbiter

20. ROUND ROBIN ARBITERS
• Allows every requester to take a turn.
• It has fixed time slot per requestor.
• A request that was just served gets the lower priority.
• Thus maximum amount of time that a requester will wait is
limited by the number of requesters.

21. Implementation:

22. Wrap around process:
•http://rtlery.com/articles/how-design-round-robin-arbiter

23. APPLICATIONS
•Round robin arbiters are typically used for load balancing,
queuing system and resource allocation.
•Used in multiprocessor computers.

25. THANK YOU