1) The document describes the analysis and simulation of an interleaved buck converter for automotive dual voltage systems. An interleaved six-phase buck converter is modeled and simulated in Simulink.
2) The interleaved topology provides benefits like reduced output ripple, smaller filter requirements, and improved reliability compared to a single phase buck converter.
3) Components like inductors, capacitors, and MOSFET switches are selected based on specifications such as a 1kW power rating and 71A output current. Simulation results are used to verify the effectiveness of the converter design.
HARMONIC MITIGATION USING D STATCOM THROUGH A CURRENT CONTROL TECHNIQUEJournal For Research
The harmonic mitigation using shunt active filters are most widely used in industrial and commercial applications. In this paper a Multi-Level Inverter is considered as DSTATCOM to compensate harmonics. The mathematical modeling of the system and design of the controller using synchronous reference frame theory is also presented. The nonlinear load generally known as diode rectifier load and an unbalanced load is simulated with the system using MATLAB/SIMULINK.
Design of High-Speed Dynamic Double-Tail ComparatorIJERDJOURNAL
ABSTRACT:- The analog-to-digital converters which are of ultra low-power, area efficient, and high speed converters are made of dynamic regenerative comparators. These comparators can maximize speed and power efficiency. The delay and power dissipation of dynamic comparators are analyzed in this paper. The delays and tradeoff can be explored. The circuit of a conventional double tail comparator in this analysis is modified for fast operation even in different supply voltages. By using power gating technique and adding few transistors, the positive feedback during the regeneration is strengthened in the proposed comparator structure. The delay time can be reduced by providing positive feedback instead of adding few transistors. The analysis results are going to be confirmed on the basis of 0.25-µm CMOS technology. The power consumption and delay time can be significantly reduced based on this analysis. All the simulation are made using TANNER TOOLS, Generic 250nm. The schematic are drawn in the T-SPICE schematic editor.
This document analyzes the total harmonic distortion (THD) of 7, 9, and 11 level cascaded H-bridge multilevel inverters using multicarrier pulse width modulation. The analysis found that THD in the output voltage decreases and output voltage increases with more levels. Simulations in MATLAB/Simulink showed that an 11-level inverter had the lowest THD at 11.1%, while a 7-level inverter had the highest THD at 24.64%. More levels therefore better reduced the harmonic distortion.
Multi-level inverters (MLIs), have gained popularity in the last few years as a result of their low total harmonic distortions (THD) as well as their output waveform which is of high quality. The converter which considers more appropriate for applications of photovoltaic (PV)beyond the varying MLIs arrangementsis the Cascaded H-Bridge-(CHB) (MLI), meanwhile each PV panel may be served as an independent DC supply for any CHB unit. Through the use of MATLAB/Simulink, the efficiency of symmetrical single phase MLI in terms of the number of switches, harmonic content in addition to the stresses of voltage through theswitches that exist at photovoltaic cell by means of input source is enhanced; varying parameters like output current, voltage and power, and THD at 5-level 7-level and 9-level Cascaded MLI are observed. In this paper, attention is paid to a multi-level topologies which is flexible and based on cascaded MLI intended for PV grids connected system. An observation of the output voltage becomes closer to the sine wave as the levels increase, while the increase in the levels of Cascaded Multilevel Inverter causes the total harmonic distortion to decrease.
A Simulation Based Analysis of Lowering Dynamic Power in a CMOS Inverteridescitation
With the increase in demand of high fidelity
portable devices, there is more and more emphasis laying
down on the development of low power and high performance
systems. In the next generation processors, the low power
design has to be incorporated into fundamental computation
units, such as adder. CMOS circuit design plays a crucial role
in designing of these computation units (like adder and
multiplier) so if there is any optimal way to reduce the power
dissipation in CMOS circuits then it will directly lower down
the power dissipation of other circuits and logic gates as well.
In this paper we have studied and analyzed different
techniques to reduce the dynamic power of CMOS circuit
with the help of performing simulation on some significant
factors (i.e device characteristics) of respective circuitry
designs by using Cadence-Virtuoso tool.
Application of soft switching in DC-DC converter has achieved a remarkable success in power electronics technology in terms of reduction in switching losses, improve in power density, minimization of electromagnetic interference (EMI) and reduction in the volume of DC-DC converters. Quite a number of soft switching techniques had been reported in the past four decades. This paper aims at providing a review of various soft switching techniques, based on topology, the location of the resonant network, performance characteristics, and principles of operation. In addition, converters area of application, advantages as well as limitations are also highlighted.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
HARMONIC MITIGATION USING D STATCOM THROUGH A CURRENT CONTROL TECHNIQUEJournal For Research
The harmonic mitigation using shunt active filters are most widely used in industrial and commercial applications. In this paper a Multi-Level Inverter is considered as DSTATCOM to compensate harmonics. The mathematical modeling of the system and design of the controller using synchronous reference frame theory is also presented. The nonlinear load generally known as diode rectifier load and an unbalanced load is simulated with the system using MATLAB/SIMULINK.
Design of High-Speed Dynamic Double-Tail ComparatorIJERDJOURNAL
ABSTRACT:- The analog-to-digital converters which are of ultra low-power, area efficient, and high speed converters are made of dynamic regenerative comparators. These comparators can maximize speed and power efficiency. The delay and power dissipation of dynamic comparators are analyzed in this paper. The delays and tradeoff can be explored. The circuit of a conventional double tail comparator in this analysis is modified for fast operation even in different supply voltages. By using power gating technique and adding few transistors, the positive feedback during the regeneration is strengthened in the proposed comparator structure. The delay time can be reduced by providing positive feedback instead of adding few transistors. The analysis results are going to be confirmed on the basis of 0.25-µm CMOS technology. The power consumption and delay time can be significantly reduced based on this analysis. All the simulation are made using TANNER TOOLS, Generic 250nm. The schematic are drawn in the T-SPICE schematic editor.
This document analyzes the total harmonic distortion (THD) of 7, 9, and 11 level cascaded H-bridge multilevel inverters using multicarrier pulse width modulation. The analysis found that THD in the output voltage decreases and output voltage increases with more levels. Simulations in MATLAB/Simulink showed that an 11-level inverter had the lowest THD at 11.1%, while a 7-level inverter had the highest THD at 24.64%. More levels therefore better reduced the harmonic distortion.
Multi-level inverters (MLIs), have gained popularity in the last few years as a result of their low total harmonic distortions (THD) as well as their output waveform which is of high quality. The converter which considers more appropriate for applications of photovoltaic (PV)beyond the varying MLIs arrangementsis the Cascaded H-Bridge-(CHB) (MLI), meanwhile each PV panel may be served as an independent DC supply for any CHB unit. Through the use of MATLAB/Simulink, the efficiency of symmetrical single phase MLI in terms of the number of switches, harmonic content in addition to the stresses of voltage through theswitches that exist at photovoltaic cell by means of input source is enhanced; varying parameters like output current, voltage and power, and THD at 5-level 7-level and 9-level Cascaded MLI are observed. In this paper, attention is paid to a multi-level topologies which is flexible and based on cascaded MLI intended for PV grids connected system. An observation of the output voltage becomes closer to the sine wave as the levels increase, while the increase in the levels of Cascaded Multilevel Inverter causes the total harmonic distortion to decrease.
A Simulation Based Analysis of Lowering Dynamic Power in a CMOS Inverteridescitation
With the increase in demand of high fidelity
portable devices, there is more and more emphasis laying
down on the development of low power and high performance
systems. In the next generation processors, the low power
design has to be incorporated into fundamental computation
units, such as adder. CMOS circuit design plays a crucial role
in designing of these computation units (like adder and
multiplier) so if there is any optimal way to reduce the power
dissipation in CMOS circuits then it will directly lower down
the power dissipation of other circuits and logic gates as well.
In this paper we have studied and analyzed different
techniques to reduce the dynamic power of CMOS circuit
with the help of performing simulation on some significant
factors (i.e device characteristics) of respective circuitry
designs by using Cadence-Virtuoso tool.
Application of soft switching in DC-DC converter has achieved a remarkable success in power electronics technology in terms of reduction in switching losses, improve in power density, minimization of electromagnetic interference (EMI) and reduction in the volume of DC-DC converters. Quite a number of soft switching techniques had been reported in the past four decades. This paper aims at providing a review of various soft switching techniques, based on topology, the location of the resonant network, performance characteristics, and principles of operation. In addition, converters area of application, advantages as well as limitations are also highlighted.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
ENHANCEMENT OF FUNDAMENTAL RMS OUTPUT VOLTAGE OF 5-LEVEL CASCADED H-BRIDGE MU...IAEME Publication
Cascaded H-bridge Multilevel Inverter (CHBMLI) is the most suitable topology for the PV power converters. In this paper an effort has been made to increase the performance of CHBMLI by improving the fundamental Root Mean Square (RMS) value of the output voltage. This work proposes a Modified Multi Carrier PWM (MMCPWM) technique where, reference sine wave has been replaced by ellipse wave, resulting in enhanced performances on the fundamental rms output voltage and lower Total Harmonic Distortion (THD). Analysis of single phase 5-level CHBMLI with and without load are carried for the different Multi Carrier PWM (MCPWM) techniques.
The document describes a new load network configuration for class F power amplifiers. The proposed network consists of parallel open and short circuited λ/8 stubs and a T-section transformer. It is designed to control harmonic impedances for high efficiency. A 10W class F power amplifier at 500MHz was designed using GaN HEMT to demonstrate the approach, simulating 84% DC-RF efficiency with 11dB gain over a 100MHz bandwidth.
This document presents a comparative investigation of a 7-level cascaded multilevel inverter using different multicarrier pulse width modulation techniques. It discusses the classification, operation, and modulation strategies of multilevel inverters including diode clamped, flying capacitor, and cascaded H-bridge topologies. Simulation results in MATLAB/Simulink are presented to analyze the total harmonic distortion for a 7-level cascaded H-bridge multilevel inverter using phase disposition, alternate phase opposition disposition, and phase opposition disposition pulse width modulation techniques. The research aims to improve the output waveform quality and reduce switching losses of the 7-level inverter.
IRJET - Wireless Power Transfer System using Pulse Density Modulation based F...IRJET Journal
This document summarizes a wireless power transfer system that uses a pulse density modulation based full bridge converter. The converter employs a zero-voltage switching technique to provide soft switching and improve efficiency. The existing pulse density modulation strategy for the converter has limitations like large low frequency subharmonics, a narrow modulation range, and large modulation delay. The document proposes a new pulse density modulation strategy that allows for asymmetric zero-voltage switching currents to overcome these limitations. Simulation results show the proposed strategy reduces subharmonics, achieves a wider modulation range, and faster response compared to the existing strategy.
IRJET- A Novel Modified Switched Capacitor Nine Level Inverter Topology with ...IRJET Journal
The document proposes a new switched-capacitor multilevel inverter topology with reduced switch count that can produce a nine-level staircase output voltage from multiple DC sources. It utilizes asymmetric DC voltage sources from renewable energy farms to reduce the number of inverters needed. The topology inherently solves the capacitor voltage balancing problem and can step up the input voltage without a bulky transformer. It is intended for use in high frequency AC power distribution systems to achieve benefits like smaller component sizes and higher power density. The performance of the proposed topology is evaluated using MATLAB/Simulink.
Optimized Hybrid Phase Disposition PWM Control Method for Multilevel InverterIDES Editor
This paper presents a new variation of hybrid
phase disposition pulse width modulation technique suitable
for cascaded multilevel inverter. A hybrid PDPWM is
developed based on low frequency PWM and high
frequency Sinusoidal PWM. An optimized sequential
switching scheme introduced in this proposed method to
equalize electro static and electro magnetic stress among the
power devices. It is confirmed that the proposed technique
offers significantly lower switching losses and switching
transitions. Furthermore, the proposed hybrid PDPWM
offers better harmonic performance compared to its
conventional PWM counterpart. Simulation results are
included in this paper in order to confirm the effectiveness
of the proposed technique.
Distance Protection Scheme for Series Compensated Transmission LinesIJERA Editor
This document presents a new distance protection scheme for series compensated transmission lines based on mutual impedance between phases. Conventional distance protection using positive sequence impedance can cause maloperation in series compensated lines due to changes in fault impedance. The proposed scheme calculates mutual impedance between the relay and fault point using voltages and currents from both line ends. Simulation results approve the efficiency of this method for protecting series compensated lines against single and double phase faults. The mutual impedance is not affected by series compensation, providing reliable backup protection.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
This document summarizes a research paper on a new three phase seven level asymmetrical inverter with hybrid carrier and third harmonic reference. It proposes a novel carrier based pulse width modulation technique that uses a combination of an inverted sine carrier and triangular carrier (hybrid carrier) to produce switch pulses for the inverter. It investigates this hybrid carrier technique for a three phase cascaded multilevel inverter, evaluating performance based on total harmonic distortion, output voltage RMS value, and DC bus utilization. The document outlines different carrier-based PWM strategies like phase disposition, phase opposition disposition, and alternate phase opposition disposition that are evaluated in the research.
Compact low power high slew-rate cmos buffer amplifier with power gating tech...VLSICS Design
A qualitative analysis of different parameters such as Phase noise, Slew rate and tranconductance by using
power gating reduction technique is presented. The circuit achieves the large driving capability by
employing simple comparators to sense the transients of the input to turn on the output stages, which are
statically off in the stable state. The effect of the different number of transistors and their topologies on the
phase noise and Slew rate is analyzed. Good agreement between qualitative and quantitative measurements
is observed. Scope of reducing of Noise and avoidance of Leakage due to various sources is discussed.
MODELLING OF 200W LED DRIVER CIRCUIT DESIGN WITH LLC CONVERTERJournal For Research
LED is a recent technology, which has replaced all other conventional light sources in the past few years and since it is current controlled, accurate driver design is necessary. The LED driver should have the capability of providing constant current regardless of the LED forward voltage variations. The LLC converter is controlled to operate as a constant current mode LED driver. A 100 kHz, 200W LLC LED driver is designed and calculated to verify the proposed circuit and design method. This paper proposes mathematical model of 200W LED driver circuit design with LLC resonant converter. The proposed circuit uses a full bridge rectifier to convert AC to DC and increases the rectified output voltage using boost converter which is operated in continuous conduction mode and a quasi-half bridge resonant converter to drive the LED lamp load with coupling transformer. The LLC converter is designed such that solid state switches of quasi half bridge are working under zero switching scheme to reduce switching losses. The analysis, design and modelling of 200 W LED driver is carried out by mathematical model and stability analysis for universal AC mains.
I v characteristics and transconductance modeling for dual channel algangan m...eSAT Journals
Abstract This paper presents the design and practical implementation of a Boost-type power converter for Photovoltaic (PV) system for energy storage application based on Perturb and Observe Maximum Power Point Tracking (MPPT) algorithm. A Boost converter is used to regulate battery charging. The major drawbacks faced by the tracking algorithm in the conventional method of tracking is overcome by the strategic utilization of a properly controlled and programmed design of Peripheral Interface Controller which helps in achieving optimized output results of MPPT algorithm.. The system is controlled by a Peripheral Interface Controller (PIC) 16F877 controller by sensing the solar panel voltage and generating the Pulse Width Modulation (PWM) signal to control duty cycle of the boost converter. This type of microcontroller was chosen is best suited as it has the necessary features for the proposed design such as built-in Analog-to-Digital Converter (ADC), PWM outputs, low power consumption and low cost. Hardware results demonstrate the effectiveness and validity of the proposed system in order to attain satisfactory results from the method. This paper mainly focuses on the effective utilization of PIC controller in the implementation of the MPPT algorithm and its constructional features which help gain the appropriate and accurate results. Keywords: Photovoltaic system, Analog-to-Digital Converter, Peripheral Interface Controller, Maximum Power Point Tracking, Pulse Width Modulation, Boost-type power converter, Duty Cycle.
This document presents a new topology for a cascaded multilevel inverter powered by a photovoltaic system. The proposed system uses a high frequency transformer to generate the DC bus voltage for an auxiliary inverter from the main inverter's DC bus. This reduces the number of isolated DC sources needed by half, lowering costs. A natural balancing of voltages between the main and auxiliary inverters is achieved through the transformer turns ratio, simplifying control. The system was simulated using static loads to validate the control scheme.
A RAIL-TO-RAIL HIGH SPEED CLASS-AB CMOS BUFFER WITH LOW POWER AND ENHANCED SL...VLSICS Design
This document summarizes a research paper that proposes a new rail-to-rail class-AB CMOS buffer circuit designed to drive large capacitive loads at high speed with low power dissipation. The proposed circuit uses a new leakage current reduction technique called LECTOR that adds leakage control transistors to reduce sub-threshold leakage current. Simulation results show the circuit operates at 3V with a propagation delay of 292.1×10-12 seconds and leakage current of 118.4μA, representing improvements over prior designs. The settling time is also improved to 41.12×10-9 seconds. In conclusion, the proposed buffer circuit achieves both high speed and low power operation suitable for driving large capacitive loads.
Optimal Body Biasing Technique for CMOS Tapered Buffer IJEEE
This paper represents Fixed Body Biased CMOS Tapered Buffer which is designed to minimize the average power dissipation across large capacitive load. The implementation of Reverse Body Bias (RBB) in the proposed Buffer chain is to vary Vth value of NMOS in the first stage. And with the increase in Vth /sub-threshold leakage current and power has been reduced. The technology constraints on the threshold voltage does not allow designer to set high threshold voltage for MOS devices. Hence, this was found that in proposed circuit that when optimal Reverse Body Bias value is set within (0.2 VDD to 0.4 VDD) range, the average power dissipation across capacitive load reduces to 82.2 % at very less penalty in delay. Thus CMOS buffer designers can use the proposed method to vary Vth while keeping VDD constant, which could improve the performance parameters of Tapered Buffer. The proposed analysis is verified by simulating the 3-stage tapered buffer schematics using standard 180nm CMOS technology in Cadence environment.
Fuzzy Logic Controller based Bridgeless (BL) Isolated Interleaved Zeta Conver...IJPEDS-IAES
In recent times, high-brightness light emitting diodes (HB-LEDs) are
developing rapidly and it is confirmed to be the future development in
lighting not only because of their high efficiency and high reliability,
however also because of their other exceptional features: chromatic variety,
shock and vibration resistance, etc. In this paper, a bridgeless (BL) Isolated
Interleaved Zeta Converter is proposed for the purpose of reducing the diode
failures or losses; the value of output ripples also gets decreased. The
proposed BL isolated interleaved zeta converter operating in discontinuous
conduction mode (DCM) is used for controlling the brightness of LED
Driver with inherent PFC at ac mains using single voltage sensor. The fuzzy
logic controller (FLC) is used to adjust the Modulation Index of the voltage
controller in order to improve the dynamic response of LED Lamp driver.
Based on the error of converter output voltage, FLC is designed to select the
optimum Modulation Index of the voltage controller. The proposed LED
driver is simulated to achieve a unity power factor at ac mains for a wide
range of voltage control and supply voltage fluctuations.
novel design of current dierencing transconductance amplier with high
2 transconductance gain and enhanced bandwidth
Shireesh Kumar RAI1 , Rishikesh PANDEY1 , Bharat GARG1 , Sujit Kumar PATEL1
1Electronics and Communication Engineering, Thapar Institute of Engineering and Technology, Patiala, Punjab, India
Multilevel Inverters are getting popular and have become more attractive to researchers in the recent times for high power applications due to their better power quality and higher efficiency as compared to two level inverters. This research work presents a detailed comparative analysis of various multicarrier sinusoidal PWM schemes such as In Phase Disposition, Phase Opposition Disposition and Alternate Phase Opposite Disposition implemented on five level conventional and modified cascaded h-bridge inverters in MATLAB/SIMULINK software. Conventional five level topology uses eight switches and suffers from increased switching complexity while modified five level topology uses only five switches and is recommended to reduce switching complexity and switching losses. It also ensures less number of components, reduced size and overall cost of the system. The effect of modulation index (Ma) on the output harmonic contents in various PWM techniques is also analyzed.
Design of a low-power compact CMOS variable gain amplifier for modern RF rece...journalBEEI
This document describes the design of a low-power compact CMOS variable gain amplifier (VGA) for modern RF receivers. A two-stage class AB VGA design is presented, with each stage comprising a direct transconductance amplifier and a linear transimpedance amplifier. Post-layout simulation results show the VGA achieves a bandwidth of over 200MHz and a gain range from -33dB to 32dB, while dissipating only 2mW from a 1.2V supply. The core chip area is 0.026mm2, smaller than recent VGA designs. Performance comparisons show the proposed VGA has the widest bandwidth and smallest die area compared to other designs.
This document discusses the design and analysis of a multi-level D-STATCOM to improve power quality. A D-STATCOM is a shunt connected custom power device that can regulate voltage and compensate for reactive power and current harmonics. The paper proposes using a cascaded H-bridge multilevel inverter for the D-STATCOM due to its advantages of low harmonic distortion and reduced switching losses. Simulation results using Matlab/Simulink show that the D-STATCOM is able to regulate the voltage and compensate for reactive power drawn by a non-linear diode rectifier load, improving the power factor and eliminating total harmonic distortion.
This document summarizes research on a single-phase five-level diode-clamped multilevel inverter (DCMLI). It first describes the conventional DCMLI topology using four capacitors and eight switches to achieve five voltage levels. It then introduces the topology studied in the paper, which uses only two capacitors and eight switches by incorporating two H-bridge legs. Simulation results are presented comparing the performance of the inverter under different pulse width modulation techniques, evaluating metrics like total harmonic distortion, voltage waveform quality factors, and efficiency of utilizing the DC bus voltage. Sinusoidal pulse width modulation with phase opposition and disposition modulation is found to provide the lowest output voltage distortion.
Comparative performance of modular with cascaded H-bridge three level invertersIJECEIAES
This document compares the modular multilevel inverter (MMC) and cascaded H-bridge (CHB) multilevel inverters for induction motor drive applications. It discusses the configuration, operation, advantages, and disadvantages of each inverter. Simulation results using MATLAB/Simulink are provided for the output voltage waveform, total harmonic distortion, and current drawn by the inverters under different load torques on the induction motor. The MMC and CHB inverters are simulated at three voltage levels to evaluate their performance for driving the induction motor.
ENHANCEMENT OF FUNDAMENTAL RMS OUTPUT VOLTAGE OF 5-LEVEL CASCADED H-BRIDGE MU...IAEME Publication
Cascaded H-bridge Multilevel Inverter (CHBMLI) is the most suitable topology for the PV power converters. In this paper an effort has been made to increase the performance of CHBMLI by improving the fundamental Root Mean Square (RMS) value of the output voltage. This work proposes a Modified Multi Carrier PWM (MMCPWM) technique where, reference sine wave has been replaced by ellipse wave, resulting in enhanced performances on the fundamental rms output voltage and lower Total Harmonic Distortion (THD). Analysis of single phase 5-level CHBMLI with and without load are carried for the different Multi Carrier PWM (MCPWM) techniques.
The document describes a new load network configuration for class F power amplifiers. The proposed network consists of parallel open and short circuited λ/8 stubs and a T-section transformer. It is designed to control harmonic impedances for high efficiency. A 10W class F power amplifier at 500MHz was designed using GaN HEMT to demonstrate the approach, simulating 84% DC-RF efficiency with 11dB gain over a 100MHz bandwidth.
This document presents a comparative investigation of a 7-level cascaded multilevel inverter using different multicarrier pulse width modulation techniques. It discusses the classification, operation, and modulation strategies of multilevel inverters including diode clamped, flying capacitor, and cascaded H-bridge topologies. Simulation results in MATLAB/Simulink are presented to analyze the total harmonic distortion for a 7-level cascaded H-bridge multilevel inverter using phase disposition, alternate phase opposition disposition, and phase opposition disposition pulse width modulation techniques. The research aims to improve the output waveform quality and reduce switching losses of the 7-level inverter.
IRJET - Wireless Power Transfer System using Pulse Density Modulation based F...IRJET Journal
This document summarizes a wireless power transfer system that uses a pulse density modulation based full bridge converter. The converter employs a zero-voltage switching technique to provide soft switching and improve efficiency. The existing pulse density modulation strategy for the converter has limitations like large low frequency subharmonics, a narrow modulation range, and large modulation delay. The document proposes a new pulse density modulation strategy that allows for asymmetric zero-voltage switching currents to overcome these limitations. Simulation results show the proposed strategy reduces subharmonics, achieves a wider modulation range, and faster response compared to the existing strategy.
IRJET- A Novel Modified Switched Capacitor Nine Level Inverter Topology with ...IRJET Journal
The document proposes a new switched-capacitor multilevel inverter topology with reduced switch count that can produce a nine-level staircase output voltage from multiple DC sources. It utilizes asymmetric DC voltage sources from renewable energy farms to reduce the number of inverters needed. The topology inherently solves the capacitor voltage balancing problem and can step up the input voltage without a bulky transformer. It is intended for use in high frequency AC power distribution systems to achieve benefits like smaller component sizes and higher power density. The performance of the proposed topology is evaluated using MATLAB/Simulink.
Optimized Hybrid Phase Disposition PWM Control Method for Multilevel InverterIDES Editor
This paper presents a new variation of hybrid
phase disposition pulse width modulation technique suitable
for cascaded multilevel inverter. A hybrid PDPWM is
developed based on low frequency PWM and high
frequency Sinusoidal PWM. An optimized sequential
switching scheme introduced in this proposed method to
equalize electro static and electro magnetic stress among the
power devices. It is confirmed that the proposed technique
offers significantly lower switching losses and switching
transitions. Furthermore, the proposed hybrid PDPWM
offers better harmonic performance compared to its
conventional PWM counterpart. Simulation results are
included in this paper in order to confirm the effectiveness
of the proposed technique.
Distance Protection Scheme for Series Compensated Transmission LinesIJERA Editor
This document presents a new distance protection scheme for series compensated transmission lines based on mutual impedance between phases. Conventional distance protection using positive sequence impedance can cause maloperation in series compensated lines due to changes in fault impedance. The proposed scheme calculates mutual impedance between the relay and fault point using voltages and currents from both line ends. Simulation results approve the efficiency of this method for protecting series compensated lines against single and double phase faults. The mutual impedance is not affected by series compensation, providing reliable backup protection.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
This document summarizes a research paper on a new three phase seven level asymmetrical inverter with hybrid carrier and third harmonic reference. It proposes a novel carrier based pulse width modulation technique that uses a combination of an inverted sine carrier and triangular carrier (hybrid carrier) to produce switch pulses for the inverter. It investigates this hybrid carrier technique for a three phase cascaded multilevel inverter, evaluating performance based on total harmonic distortion, output voltage RMS value, and DC bus utilization. The document outlines different carrier-based PWM strategies like phase disposition, phase opposition disposition, and alternate phase opposition disposition that are evaluated in the research.
Compact low power high slew-rate cmos buffer amplifier with power gating tech...VLSICS Design
A qualitative analysis of different parameters such as Phase noise, Slew rate and tranconductance by using
power gating reduction technique is presented. The circuit achieves the large driving capability by
employing simple comparators to sense the transients of the input to turn on the output stages, which are
statically off in the stable state. The effect of the different number of transistors and their topologies on the
phase noise and Slew rate is analyzed. Good agreement between qualitative and quantitative measurements
is observed. Scope of reducing of Noise and avoidance of Leakage due to various sources is discussed.
MODELLING OF 200W LED DRIVER CIRCUIT DESIGN WITH LLC CONVERTERJournal For Research
LED is a recent technology, which has replaced all other conventional light sources in the past few years and since it is current controlled, accurate driver design is necessary. The LED driver should have the capability of providing constant current regardless of the LED forward voltage variations. The LLC converter is controlled to operate as a constant current mode LED driver. A 100 kHz, 200W LLC LED driver is designed and calculated to verify the proposed circuit and design method. This paper proposes mathematical model of 200W LED driver circuit design with LLC resonant converter. The proposed circuit uses a full bridge rectifier to convert AC to DC and increases the rectified output voltage using boost converter which is operated in continuous conduction mode and a quasi-half bridge resonant converter to drive the LED lamp load with coupling transformer. The LLC converter is designed such that solid state switches of quasi half bridge are working under zero switching scheme to reduce switching losses. The analysis, design and modelling of 200 W LED driver is carried out by mathematical model and stability analysis for universal AC mains.
I v characteristics and transconductance modeling for dual channel algangan m...eSAT Journals
Abstract This paper presents the design and practical implementation of a Boost-type power converter for Photovoltaic (PV) system for energy storage application based on Perturb and Observe Maximum Power Point Tracking (MPPT) algorithm. A Boost converter is used to regulate battery charging. The major drawbacks faced by the tracking algorithm in the conventional method of tracking is overcome by the strategic utilization of a properly controlled and programmed design of Peripheral Interface Controller which helps in achieving optimized output results of MPPT algorithm.. The system is controlled by a Peripheral Interface Controller (PIC) 16F877 controller by sensing the solar panel voltage and generating the Pulse Width Modulation (PWM) signal to control duty cycle of the boost converter. This type of microcontroller was chosen is best suited as it has the necessary features for the proposed design such as built-in Analog-to-Digital Converter (ADC), PWM outputs, low power consumption and low cost. Hardware results demonstrate the effectiveness and validity of the proposed system in order to attain satisfactory results from the method. This paper mainly focuses on the effective utilization of PIC controller in the implementation of the MPPT algorithm and its constructional features which help gain the appropriate and accurate results. Keywords: Photovoltaic system, Analog-to-Digital Converter, Peripheral Interface Controller, Maximum Power Point Tracking, Pulse Width Modulation, Boost-type power converter, Duty Cycle.
This document presents a new topology for a cascaded multilevel inverter powered by a photovoltaic system. The proposed system uses a high frequency transformer to generate the DC bus voltage for an auxiliary inverter from the main inverter's DC bus. This reduces the number of isolated DC sources needed by half, lowering costs. A natural balancing of voltages between the main and auxiliary inverters is achieved through the transformer turns ratio, simplifying control. The system was simulated using static loads to validate the control scheme.
A RAIL-TO-RAIL HIGH SPEED CLASS-AB CMOS BUFFER WITH LOW POWER AND ENHANCED SL...VLSICS Design
This document summarizes a research paper that proposes a new rail-to-rail class-AB CMOS buffer circuit designed to drive large capacitive loads at high speed with low power dissipation. The proposed circuit uses a new leakage current reduction technique called LECTOR that adds leakage control transistors to reduce sub-threshold leakage current. Simulation results show the circuit operates at 3V with a propagation delay of 292.1×10-12 seconds and leakage current of 118.4μA, representing improvements over prior designs. The settling time is also improved to 41.12×10-9 seconds. In conclusion, the proposed buffer circuit achieves both high speed and low power operation suitable for driving large capacitive loads.
Optimal Body Biasing Technique for CMOS Tapered Buffer IJEEE
This paper represents Fixed Body Biased CMOS Tapered Buffer which is designed to minimize the average power dissipation across large capacitive load. The implementation of Reverse Body Bias (RBB) in the proposed Buffer chain is to vary Vth value of NMOS in the first stage. And with the increase in Vth /sub-threshold leakage current and power has been reduced. The technology constraints on the threshold voltage does not allow designer to set high threshold voltage for MOS devices. Hence, this was found that in proposed circuit that when optimal Reverse Body Bias value is set within (0.2 VDD to 0.4 VDD) range, the average power dissipation across capacitive load reduces to 82.2 % at very less penalty in delay. Thus CMOS buffer designers can use the proposed method to vary Vth while keeping VDD constant, which could improve the performance parameters of Tapered Buffer. The proposed analysis is verified by simulating the 3-stage tapered buffer schematics using standard 180nm CMOS technology in Cadence environment.
Fuzzy Logic Controller based Bridgeless (BL) Isolated Interleaved Zeta Conver...IJPEDS-IAES
In recent times, high-brightness light emitting diodes (HB-LEDs) are
developing rapidly and it is confirmed to be the future development in
lighting not only because of their high efficiency and high reliability,
however also because of their other exceptional features: chromatic variety,
shock and vibration resistance, etc. In this paper, a bridgeless (BL) Isolated
Interleaved Zeta Converter is proposed for the purpose of reducing the diode
failures or losses; the value of output ripples also gets decreased. The
proposed BL isolated interleaved zeta converter operating in discontinuous
conduction mode (DCM) is used for controlling the brightness of LED
Driver with inherent PFC at ac mains using single voltage sensor. The fuzzy
logic controller (FLC) is used to adjust the Modulation Index of the voltage
controller in order to improve the dynamic response of LED Lamp driver.
Based on the error of converter output voltage, FLC is designed to select the
optimum Modulation Index of the voltage controller. The proposed LED
driver is simulated to achieve a unity power factor at ac mains for a wide
range of voltage control and supply voltage fluctuations.
novel design of current dierencing transconductance amplier with high
2 transconductance gain and enhanced bandwidth
Shireesh Kumar RAI1 , Rishikesh PANDEY1 , Bharat GARG1 , Sujit Kumar PATEL1
1Electronics and Communication Engineering, Thapar Institute of Engineering and Technology, Patiala, Punjab, India
Multilevel Inverters are getting popular and have become more attractive to researchers in the recent times for high power applications due to their better power quality and higher efficiency as compared to two level inverters. This research work presents a detailed comparative analysis of various multicarrier sinusoidal PWM schemes such as In Phase Disposition, Phase Opposition Disposition and Alternate Phase Opposite Disposition implemented on five level conventional and modified cascaded h-bridge inverters in MATLAB/SIMULINK software. Conventional five level topology uses eight switches and suffers from increased switching complexity while modified five level topology uses only five switches and is recommended to reduce switching complexity and switching losses. It also ensures less number of components, reduced size and overall cost of the system. The effect of modulation index (Ma) on the output harmonic contents in various PWM techniques is also analyzed.
Design of a low-power compact CMOS variable gain amplifier for modern RF rece...journalBEEI
This document describes the design of a low-power compact CMOS variable gain amplifier (VGA) for modern RF receivers. A two-stage class AB VGA design is presented, with each stage comprising a direct transconductance amplifier and a linear transimpedance amplifier. Post-layout simulation results show the VGA achieves a bandwidth of over 200MHz and a gain range from -33dB to 32dB, while dissipating only 2mW from a 1.2V supply. The core chip area is 0.026mm2, smaller than recent VGA designs. Performance comparisons show the proposed VGA has the widest bandwidth and smallest die area compared to other designs.
This document discusses the design and analysis of a multi-level D-STATCOM to improve power quality. A D-STATCOM is a shunt connected custom power device that can regulate voltage and compensate for reactive power and current harmonics. The paper proposes using a cascaded H-bridge multilevel inverter for the D-STATCOM due to its advantages of low harmonic distortion and reduced switching losses. Simulation results using Matlab/Simulink show that the D-STATCOM is able to regulate the voltage and compensate for reactive power drawn by a non-linear diode rectifier load, improving the power factor and eliminating total harmonic distortion.
This document summarizes research on a single-phase five-level diode-clamped multilevel inverter (DCMLI). It first describes the conventional DCMLI topology using four capacitors and eight switches to achieve five voltage levels. It then introduces the topology studied in the paper, which uses only two capacitors and eight switches by incorporating two H-bridge legs. Simulation results are presented comparing the performance of the inverter under different pulse width modulation techniques, evaluating metrics like total harmonic distortion, voltage waveform quality factors, and efficiency of utilizing the DC bus voltage. Sinusoidal pulse width modulation with phase opposition and disposition modulation is found to provide the lowest output voltage distortion.
Comparative performance of modular with cascaded H-bridge three level invertersIJECEIAES
This document compares the modular multilevel inverter (MMC) and cascaded H-bridge (CHB) multilevel inverters for induction motor drive applications. It discusses the configuration, operation, advantages, and disadvantages of each inverter. Simulation results using MATLAB/Simulink are provided for the output voltage waveform, total harmonic distortion, and current drawn by the inverters under different load torques on the induction motor. The MMC and CHB inverters are simulated at three voltage levels to evaluate their performance for driving the induction motor.
A Novel Integrated AC-DC Five Level Converter Strategy for Power Factor Corre...IJMTST Journal
Multilevel configuration has the advantage of its simplicity and modularity over the configurations of the other converters. With the application of multilevel converter in the high voltage and large power occasions in recent years, its modulation strategy has become a research hot point in the field of power electronics. The proposed power-factor-correction circuit can achieve unity power factor and ripple-free input current using a coupled inductor. The proposed rectifier can also produce input currents that do not have dead band regions and an output current that is continuous for all load conditions. The features of this converter are that it has lower input section peak current stresses and a better harmonic content than similar converter with a non-interleaved output, the output current is continuous for all load ranges, and the dc bus voltage is less than 450 for all line and load conditions. In this paper, the operation of the new converter is explained, its steady-state characteristics are determined by analysis, and these characteristics are used to develop a procedure for the design of the converter. Hence the simulation results are obtained using MATLAB/SIMULINK software. The proposed system provides a closed loop control for variable output voltage. The SSPFC AC/DC converter can operate with lower peak voltage stresses across the switches and the DC bus capacitors as it is a three-level converter. The proposed concept can be implemented with 5-level for efficient output voltage.
Application of PWM Control Strategy on Z-Source Isolated Dual active bridge D...IJMER
This project presents a Z-source with bidirectional dc–dc converter. The switching count is
reduced by adding a passive element. Thus, we are improving the output voltage level. The voltage
regulation range of proposed converter is better than that of the traditional bidirectional dc–dc
converter. The fully bridge symmetrical circuit configuration, is neither a high-voltage side nor a lowvoltage
side in the circuit structure, and the sources connected to the dc side of each H-bridge circuit
with voltage sources and current sources. This method can reduce current stress and improves the
system efficiency.
In this paper we are presenting a dual active bridge (DAB) dc–dc converter is also known as
Bidirectional DC-DC converter. Both simulation results are shown by using MATLAB software.
This document summarizes a research paper on using a multilevel converter topology for AC-DC harmonic immunity in VSC HVDC transmission. Key points:
- Voltage-source converter (VSC) based HVDC systems use multilevel converters to achieve high voltage switching capabilities. Cascaded H-bridge converters allow utilization of different DC voltages on individual cells.
- Selective harmonic elimination pulse-width modulation (SHE-PWM) techniques offer the lowest possible number of switching transitions and losses for VSC HVDC. The paper discusses optimized modulation patterns providing controlled harmonic immunity between AC and DC sides for a two-level converter with a rippled DC link voltage.
- Simulation and experimental results presented confirm the
A Novel Multi Port Dc/Dc Converter Topology Using Zero Voltage Switching For...IJMER
This paper proposes a novel four-port DC/DC converter topology that can interface two renewable energy sources, a bidirectional battery storage port, and an isolated load port. The topology is derived from a traditional half-bridge converter with the addition of two switches and diodes. All four main switches can achieve zero-voltage switching, reducing switching losses. MATLAB simulations and experimental results validate the circuit operation and regulation of the multiple power ports via independent duty cycle control. The proposed topology is suitable for applications integrating hybrid photovoltaic and wind energy systems with battery storage.
High-Power Bidirectional Dual Active Bridge and Double Dual Active Bridge DC-...IRJET Journal
The document summarizes a high-power bidirectional dual active bridge DC-DC converter. It discusses how dual active bridge converters use two full-bridge circuits connected by a transformer and inductor to enable bidirectional power flow and control power transfer between two DC sources by phase shifting square wave voltages generated by each bridge. Zero-voltage switching is enabled through resonance of the inductor and snubber capacitor, improving efficiency. The dual active bridge converter is well-suited for applications requiring high power density and bidirectional power flow such as balancing energy storage systems in aircraft.
Simulation based approach for Fixing Optimum number of Stages for a MMCIJERA Editor
Modular multi level converters (MMC) are gaining importance day by day due to their inherent advantages of
bidirectional capability, reduced switching loss. MMCs have become one of the best choices for electric vehicles
(EV) and storage based electric vehicles as these converters have the ability of conduction in both the directions
with bidirectional switches. One of the major issues of concern of an EV is that the storage of energy, as these
vehicles battery storage with large capacity and these batteries required to be charged continuously. This feature
of EV makes usage of MMCs as an attractive solution. The output available across a MMC is stepped sine wave.
As the number of steps increases nearness of output voltage with a sine wave is increased, but this is not true.
The authors feel that it is not true in case of a Sinusoidal Pulse Width Modulated Inverter. As the number of
levels are increased the Total Harmonic Distortion (THD) in a voltage waveform decreases to a minimum value
and then increases. MMC configuration proposed in [1] taken into consideration and simulation studies are
conducted using Sinusoidal Pulse Width Modulation control scheme with the help of MATLAB / SIMULINK.
The THD levels in the phase voltages and load currents are presented. With the help of simulation studies the
optimum number of an inverter are identified.
IRJET- Comparative Study of Carrier-Based Pwm Techniques for Control of Doubl...IRJET Journal
This document compares carrier-based PWM techniques for controlling a double-star modular multilevel converter (M2C) using half-bridge cells. It analyzes the total harmonic distortion of the output voltage and current for different PWM techniques. It also examines the influence of arm inductances on current and voltage THD and the allowable range of the modulation index for different techniques. The goal is to determine the most effective technique for capacitor balancing and lowest output distortion. Simulations in Matlab/Simulink will be used to compare the performance of different carrier-based PWM control methods for the M2C converter.
This document summarizes a research paper that proposes a dual inverter topology for open-ended winding induction motor drives. The topology uses a single DC source and a floating capacitor bank to achieve multi-level output voltages. Switching combinations are used to control the voltage of the floating capacitor bank and charge it to half the main DC link voltage. Simulation and experimental results demonstrate the motor drive operating with open-loop V/f control and closed-loop field oriented control.
Fuzzy Logic Controller Based on Voltage Source Converter-HVDC with MMC TopologyIJMTST Journal
This paper presents Modular Multi Level Converters (MMC) are used for high voltage high power DC to AC conversion. The MMCs with increased number of levels offer close to sine wave operation with reduced THD on the AC side. This is a new type of voltage source converter (VSC) topology. The use of this converter in a high-voltage direct current (HVDC) system is called by a MMC-HVDC system. The MMC-HVDC has the advantage in terms of scalability, performance, and efficiency over two-and three-level VSC-HVDC. The proposed HVDC system offers the operational flexibility of VSC based systems in terms of active and reactive power control, in addition to improved ac fault ride-through capability and the unique feature of current-limiting capability during dc side faults. The proposed VSC-HVDC system, in this project assesses its dynamic performance during steady-state and network alternations, including its response to AC and DC side faults. In this project using a fuzzy controller and the proposed topology is implemented in MATLAB/SIMULINK environment and the simulation results are observed.
DG FED MULTILEVEL INVERTER BASED D-STATCOM FOR VARIOUS LOADING CONDITIONSIJCI JOURNAL
During the past few decades, power industries have proved that the adverse impacts on the PQ can be
mitigated or avoided by conventional means, and that technique using fast controlled force commutated
power electronics (PE) are even more effective. PQ compensators can be categorized into two main types.
One is shunt connected compensation device that effectively eliminates harmonics. The other is the series
connected device, which has an edge over the shunt type for correcting the distorted system side voltages
and voltage sags caused by power transmission system faults. The STATCOM used in distribution systems
is called DSTACOM (Distribution-STACOM) and its configuration is the same, but with small
modifications. Recent advances in the power-handling capabilities of static switch devices such as 3.3kV,
4.5kV, and 6.5kV Insulated Gate Bipolar Transistors (IGBTs) with voltage rating commercially available,
have made the use of the voltage source inverters (VSI) feasible for high-power applications. High power
and high-voltage conversion systems have become very important issues for the power electronic industry
handling the large ac drive and electrical power applications at both the transmission and distribution
levels. For these reasons, new families of multilevel inverters have emerged as the solution for working
with higher voltage levels. Multilevel inverters (MLI) include an array of power semiconductors and
capacitor voltage sources, the output of which generate voltages with stepped waveforms. These converter
topologies can generate high-quality voltage waveforms with power semiconductor switches operating at a
frequency near the fundamental. It significantly reduces the harmonics problem with reduced voltage stress
across the switch. This research work is mainly focusing on application of multilevel DSTATCOM for
power quality improvement in distribution system with integration of RES. Matlab/Simulink based model is
developed and simulation results are presented.
The power electronics device which converts DC power to AC power at required output voltage and frequency level is known as inverter. Multilevel inverter is to synthesize a near sinusoidal voltage from several levels of dc voltages. In order to maintain the different voltage levels at appropriate intervals, the conduction time intervals of MOSFETS have been maintained by controlling the pulse width of gating pulses. In this paper single phase to three phase power conversion using PWM technique. The simulation is carried out in MATLAB/Simulink environment which demonstrate the feasibility of proposed scheme.
Performance Evaluation of Nine Level Modified CHB Multilevel Inverter for Var...IJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
Simulation and analysis of multilevel inverter with reduced number of switchesIAEME Publication
This document summarizes a research paper that proposes a new multilevel inverter topology with reduced number of switches compared to conventional cascaded H-bridge multilevel inverters. The proposed topology is a five-level inverter that requires only six switches compared to eight switches in a conventional design. Simulation results show the performance of the new topology is validated using MATLAB/Simulink software. The paper also describes the operating modes and switching techniques used in the new multilevel inverter design, including phase disposition, alternative phase opposition disposition, and phase opposition disposition pulse width modulation strategies.
COMPREHENSIVE ANALYSIS AND SIMULATION OF MULTILEVEL POWER CONVERTERS TO CURTA...ecij
Present day industrial applications require higher power apparatus for power conversion. At medium voltage grid, to connect only one power semiconductor switch directly is a not practically successful concept. To overcome this multilevel power converter structure has been introduced and studied as an alternative in high power and medium voltage applications. Renewable energy sources like photovoltaic, wind, fuel cells can be conveniently interfaced to a multilevel converter system for high power applications. In this study it is discussed in detail for different levels of the multilevel converters using pulse width
modulation technique (PWM) the harmonics contents decreases gradually. The simulated results are presented and compared thereafter. Total harmonic distortion decreases as the number of levels increased are tabulated accordingly. All the simulation results are carried out under MATLAB/Simulink environment.
COMPREHENSIVE ANALYSIS AND SIMULATION OF MULTILEVEL POWER CONVERTERS TO CURTA...ecij
Present day industrial applications require higher power apparatus for power conversion. At medium
voltage grid, to connect only one power semiconductor switch directly is a not practically successful
concept. To overcome this multilevel power converter structure has been introduced and studied as an
alternative in high power and medium voltage applications. Renewable energy sources like photovoltaic,
wind, fuel cells can be conveniently interfaced to a multilevel converter system for high power applications.
In this study it is discussed in detail for different levels of the multilevel converters using pulse width
modulation technique (PWM) the harmonics contents decreases gradually. The simulated results are
presented and compared thereafter. Total harmonic distortion decreases as the number of levels increased
are tabulated accordingly. All the simulation results are carried out under MATLAB/Simulink environment.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Grid connected pv system using 9 level flying capacitor multilevel inverterIAEME Publication
This document summarizes a research paper that proposes using a 9-level flying capacitor multilevel inverter to integrate a photovoltaic system into a power grid. A 9-level flying capacitor multilevel inverter can reduce harmonics and total harmonic distortion compared to conventional inverters. The system was simulated in Matlab/Simulink and includes a PV array, boost converter to increase the voltage, and the 9-level flying capacitor multilevel inverter connected to the grid. Key advantages of multilevel inverters are their ability to handle high power applications with reduced switching losses and lower output distortion.
IRJET - A Zero Voltage Switching Pulse Width Modulated Multilevel Buck ConverterIRJET Journal
This document presents a new five-level zero voltage switching pulse width modulated multilevel buck converter. The proposed converter uses a multilevel topology to reduce voltage stresses on switches without adding extra voltage. It achieves zero voltage switching for all switches by utilizing active clamping and circulating reactive energy throughout the converter. Simulations in MATLAB were used to verify the performance of the proposed converter. The converter design and operating principles are explained, including modes of operation, component sizing equations, and simulation details.
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The document compares three flexible manufacturing system installations in terms of their technical features and impact on workers. It finds that while the technology aims to enhance productivity and quality, it also reduces autonomy and skills for many operators. Management styles and training programs can help address some worker issues but may also introduce new problems.
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1. World Academy of Science, Engineering and Technology 39 2010
Analysis and Simulation of Automotive
Interleaved Buck Converter
Mohamed. A. Shrud, Ahmad H. Kharaz, Ahmed. S. Ashur, Ahmed Faris and Mustafa Benamar
[6]. The philosophy behind dual battery system architecture is
Abstract—This paper will focus on modeling, analysis and that the starting function should be isolated from the storage
simulation of a 42V/14V dc/dc converter based architecture. This function required for the key-off loads [7].
architecture is considered to be technically a viable solution for
automotive dual-voltage power system for passenger car in the near
further. An interleaved dc/dc converter system is chosen for the
automotive converter topology due to its advantages regarding filter
reduction, dynamic response, and power management. Presented
herein, is a model based on one kilowatt interleaved six-phase buck
converter designed to operate in a Discontinuous Conduction Mode
(DCM). The control strategy of the converter is based on a voltage-
mode-controlled Pulse Width Modulation (PWM) with a
Proportional-Integral-Derivative (PID). The effectiveness of the
interleaved step-down converter is verified through simulation results
using control-oriented simulator, MatLab/Simulink.
Keywords—Automotive, dc-to-dc power modules, design,
interleaved, MatlabSimulink and PID control.
I. INTRODUCTION
A switching converter is an electronic power system which
transforms an input voltage level into another for a given
load by switching action of semiconductor devices. A high
Fig. 1 The 42V/14Vsystem architecture
power efficient dc-dc converter is strongly desired and has
found widespread applications. Examples include aerospace
[1], sea and undersea vehicles [2], electric vehicles (EV), For automotive application where volume, weight, and cost
Hybrid Electric Vehicle (HEV) [3], portable electronic devices are particularly important, the preferred choice is the single
like pagers [4], and microprocessor voltage regulation [5]. battery 42V/14V system architecture with centralized system
In dual-voltage vehicular electrical systems, the dc-to-dc structure. Furthermore, the removal of the 12V battery does
converter is required to step-down the high-voltage to provide not alter the dynamics of operation of the power converter. But
back up compatibility for the existing low-power devices such the power from the converter must cover the power
as lamps, small electric motors, control units and key-off load requirement of all the 14V power loads (approximately1kW)
(clock, security system). A schematic of the 42V/14V dc-to-dc under the worst-case scenario.
converter architecture is shown in Fig.1, with the possibility of In addition, the non-isolated dc/dc converter topology is
either single or a dual battery (12V and 36V). The aim of the the most appropriate architecture because isolation between
42V/14V architecture of Fig.1 is to reduce the cost, weight and 42V and 14V buses is not required in automotive power net
packaging space created by the additional 12V energy storage and has the advantage over the transformer-isolation types in
battery. Ideally, the power management system should be terms of the easy-to-design circuit configuration, low volume,
smart enough to manage the key-off loads from depleting the weight and cost.
high voltage battery to the point that the car cannot be started An important portion of the integrated circuit industries
such as (Linear Technology Corporation and Texas
M. A. Shrud is with High Institute of Electronic Professions, Tripoli, Instrument) are focusing their efforts in developing more
Libya (mshrud@hotmail.com). efficient and reliable step-down (Buck) converters. In
A. H. Kharaz is with the School of Technology, University of Derby, academic, research studies into analysis, modeling and
Derby, UK (e-mail: a.kharaz@derby.ac.uk).
A. S. Ashur is with Alfateh University, Tripoli, Libya (e-mail: simulation of 42V/14V dc/dc converters have made progress
a.ashur@hotmail.co.uk) . in various disciplines, including thermal, electrical and
A. Faris is with the University of Derby, Derby, UK (e-mail: mechanical analysis.
a.faris@derby.ac.uk). A strategic methodology to the design power of electronic
M. Benamar is with Libyan Civil Aviation, Air Navigation
Department,Tripoli-Libya (e-mail: benammar11@hotmailcom). equipments is presented in [8]. Investigation of computer-
aided design (CAD) tool to calculate the number of phases to
10
2. World Academy of Science, Engineering and Technology 39 2010
optimize cost, size, and weight is offered in [9]. The power V
I max = L × D × T (3)
losses in a 500W converter as a function of the number of L
phases are explained in [10]. The effect of number of cells on Where:- T = 1 / fs , fs is the converter switching frequency and
the passive component using software tool called PExprt is D is switching duty cycle for the MOSFET switch, defined
carried out in [11]. A comparison between multi-phase by t on / T . Equation 3 can be rewritten in the form of,
converters with a conventional single-switch buck converter is
carried out in [12]. State of the art engineering for multi-phase (V − Vo )
I max = i
f L
(4)
dc/dc converter may range from three, four to five paralleled s
buck stages [9,12]or even as many as 16 and 32 phases
[13,14]. Upon inspection of figure 2(b), I max is twice the phase
Taking one step further in this direction, a model based on averaged current, therefore, the average value of inductor
one kilowatt interleaved six-phase dc-to-dc buck converter current is described by the following relationship:
designed to operate in a Discontinuous Conduction Mode
(DCM) controlled by voltage-mode-controlled Pulse Width
(5) I avg =
(Vi − Vo ) Vi D 2
Modulation (PWM) with a Proportional Integral Derivative 2 L f s Vo
(PID) is presented. The effectiveness of the interleaved step-
This equation states that, the output current is characterized by
down converter system is verified through simulation results the bus voltages, inductance and the switching frequency. At
using control-oriented simulators, MatLab/Simulink. the end of turn-on period, as soon as the switch is
turned OFF and the diode is ON to keeps inductor current
flowing. The rate of fall in the inductor current during the
ІІ. DC-TO-DC POWER MODULE freewheeling period is;
A single step-down converter system typically involve
switching circuits composed of semiconductor switches such ∆I V
=− o (6)
as, MOSFETs and diodes, along with passive elements such as ∆t L
inductors, capacitors, and resistors as shown in Fig. 2a. The
main switching waveforms of the inductor voltage and current The above procedure could be repeated easily during the
under steady-state conditions are sketched in figure 2b for OFF interval, (1 − D ) T to determine the same state variable
Critical Discontinuous Conduction Mode (CDCM) and in equation of the average value of inductor current I avg .
figure 2c for Discontinuous Conduction Mode (DCM) of
operation. The gating signal, q (t) ε [0, 1] is the control As can be seen from Fig 2(c), the value of the inductance
variable that models the MOSFET switch. When the value of needed to ensure that the converter remains in Discontinuous
the control variable q (t) =1, the MOSFET is ON , and zero Conduction Mode (DCM) of operation i.e. the inductor current
when the MOSFET is OFF . is zero during part of the switching period and both
Assuming that the converter is operating under CDCM of semiconductor devices are OFF during some part of each cycle
operation as shown in Fig 2(b), the operation of this circuit can must be less than L critical , which can be determined as follow.
be explained as follows; the operation of this circuit can be
explained as follows; Vi D 2 V − Vo
Lcritical = × i (7)
2 f s I max Vo
• During the turn-on period of the high-side switch,
the input voltage is connected to the inductor and
the diode is OFF . According to Lenz's law, the Where: L < Lcirtical
voltage across a coil is equal to the instantaneous
rate of change in current multiplied by the self
However, the standard dc/dc converter with single structure
inductance of the coil. Therefore, the mathematic
is not feasible due to the low voltage (14V) high current
equations for this interval is given by:
(71A), and high operating temperature characteristics of the
converter specification. Therefore, most of the power stage of
the converter would have to be built in parallel for practical
(1) V L = L × ∆I implementation. A common approach in technical literature
∆t
and industry practice is to use interleaved multi-phase
Rearranging equation (1) becomes; technique instead of a single larger converter [15,16]. This
approach is an attractive solution and its benefits will be
V
∆I = L × ∆t (2) discussed in the next section.
L
The maximum inductor current is given by;
11
3. World Academy of Science, Engineering and Technology 39 2010
III. MULTIPHASE SWITCHING OF DC-TO-DC
CONVERTERS
Fig. 2 (a) A single-buck converter topology, (b) Typical
CDCM excitation and (c) A DCM excitation current
waveforms
To realize power conversion by a simple system
configuration, a multi-cells buck converter topology designed
Fig. 3 Simulink implementation of the interleaved six phase buck
for DCM of operation is employed. Fig. 3 shows the
converter circuit with PID controller
developed Simulink diagram of six- cells interleaved buck
converter with PID Controller.
The ripple reduction helps to reduce the filtration
The six-cell interleaved buck converter is connected in
requirements needed to contain any EMI the converter
parallel to a common output capacitor and sharing a common
produces and thereby decrease the constraints on the
load with associated control system. The low-voltage side is
electronics components connected to the low-voltage bus.
connected to the 14V automotive electrical loads while the
Furthermore, due to the equal sharing of the load current
high-voltage side to the on-board power generator (alternator)
between cells, the stress on the semiconductor switches is
with nominal input voltage of 42V, and range between 30V
reduced and thereby reliability is improved. Another
and 50V during normal operation.
advantage is the ability to operate the converter when a failure
In this interleaved six-cell dc/dc converter architecture, the
occurs in one cell as well as the possibility to add new cells to
cells are switched with the same duty ratio, but with a relative
the converter with minimum effort.
phase shift or time interleaved of 60° introduced between each
To design this converter, the following automotive
cell in order to reduce the magnitude of the output ripple at the
specifications for dual-voltage automotive electrical systems
output port of the converter. The overall output current is
must be fulfilled and are tabulated in table 1[8, 9, 17]. The
achieved by the summation of the output currents of the cells.
specifications of the converter should meet the demand of the
With the phase shift of 60°, the output of the converter is
14V electrical loads of 71A, operating temperature range -
found to be continuous.
40°C to 90°C and the tight EMI requirements to prevent the
converter from interfering with other equipment in the car.
Adding to this, the converter should provide high performance
and high reliability at low cost.
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TABLE 1 TABLE II
DESIGN SPECIFICATIONS FOR A POWER CONVERTER IN A DUAL-VOLTAGE CAPACITOR VALUE VERSUS VOLTAGE /CURRENT RIPPLE
AUTOMOTIVE ELECTRICAL SYSTEM
Capacitor value Output voltage ripple Output current ripple
Description Parameter Value 100µF 6mV 30mA
Operation input voltage Vi 30V<42V<50V
150µF 4mV 20mA
Operation output voltage Vo 11V<14V<16V
200µF 3mV 16mA
Power rating Po 1kW
250µF 2.5mV 12mA
Operation temperature range T -40C<T<90C
Output ripple voltage ∆Vo 300mV 300µF 2mv 10mA
Output ripple current ∆I o 1A 350µF 1.5mV 9mA
400µF 1mV 7mA
IV. COMPONENT SELECTION
For low voltage/high current power converter, the usage of Fig. 4 Ripple voltage versus capacitor values
MOSFETs switching devices with low on-resistance is
required for more efficient and practical power conversion.
The inductors and capacitors play important roles in the design
of the power converter. Inductor is an energy storage element
while the capacitor is the main buffer for absorbing the ripple
current generated by the switching action of the power stage.
The switching frequency of the power electronics used in
automotive industry ranges from 82 kHz to 200 kHz with 100
kHz as a typical value used for most operation of dc/dc
converters.
Based on the switching frequency, input/output voltages and with a Proportional-Integral-Derivative (PID) which takes its
the duty ratio, the inductance value to guarantee that the control signal from the output voltage of the switching
converter cells would run in the discontinuous conduction converter instead of current-mode (or current-injected) PWM,
mode DCM over the entire operating range can be calculated which utilizes both the output voltage information and the
using the following equation current information from the inductor to determine the desired
duty cycle. A Simulink model for the internal structure of the
Vi D 2 V − Vo PID used to control the converter is shown in Fig. 5.
Lcritical = × i (8)
2 f s I max Vo
Since this is a six-phase interleaving converter, the power
stage inductance of each phase is therefore equal to 2.4µH.
The output capacitor is another important element, which may
reduce the system cost in multi-phase converter system and is
needed to keep the output voltage ripple ∆ Vo within allowable
output voltage range. To meet these constraints of the design
specifications, the capacitor value does not necessarily need to
be very large to smooth the output voltage. Table 2 shows the
capacitor variation from 100µF to 400µF along with the value
of voltage/current ripple while figure 4 shows the plot of Fig. 5 A PID controller represented by a Simulink block diagram
output ripple voltage versus capacitor value from the
simulation analysis obtained. To meet the constraint of the The aim is to regulate the output voltage of the converter Vo
design requirements concerning the voltage ripple of the across the load resistance RL to mach a precise stable reference
converter system, a capacitor value of 300µF is sufficient. voltage Vref . This is achieved by subtracting the desired
reference voltage Vref from the sensed output Voltage Vo of the
V. CONTROL DESIGN STRATEGIES converter. The voltage-error thus obtained is passed through a
Feedback is used in control systems to change the dynamic PID controller to obtain the desired signal. The function of the
behavior of the system, whether mechanical, electrical, or PID controller is to take the input signal, compute its
biological, and to maintain their stability. The control strategy derivative and integral, and then compute the output as a
of the proposed converter is based on a voltage-mode- combination of input signal, derivative and integral. The
controlled Pulse Width Modulation (PWM) individual effects of P, I, and D tuning on the closed-loop
response are summarized in table 3[18].
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TABLE III
EFFECT OF INDEPENDENT P, I, AND D DURING THE TUNING PROCESS
Closed-Loop Rise Overshot Settling Steady Stability
response time time state error
Increasing P Decrease Increase Small Decrease Degrade
increase
Increasing I Small Increase Increase Large Degrade
decrease decrease
Increasing D Small Decrease Decrease Minor Improve
decrease decrease
The desired output generated signal of the PID controller is
fed to the Pulse Width Modulation (PWM) unit, where it is
compared with a constant frequency saw tooth voltage V pwm .
The frequency of saw tooth voltage is the switching Fig.7 Six phases of interleaving in Simulink
frequency f s of the converter which is100 kHz. The output
signal from the PWM is the switching control signal, which
represents a sequence of pulses that drives the semiconductor
switch, as shown in fig 6.
Fig. 8 Six-phase control signals in Simulink
VI. MATLAB/SIMULINK SIMULATIONS AND
RESULTS
The ability to model and simulate engineering design of a
complete power electronic converter system is essential before
proceeding to the engineering experimental phase. Hence,
Fig. 6 Implementation of Pulse Width Modulation in Simulink. simulations are important for design validations and cost-
effectiveness as the power-conversion product development.
The proposed converter necessitates a phase-shift of 60° The complete model of the Simulink implementation of the
between the cells to generate the six-switching control signal internal structure of the interleaved six-phase buck converter
which are used to drive the six active MOSFET switching system is shown in Fig.9. The converter system is divided into
devices of the converter system. Figure 7 and 8 shows the three main parts; the six-cell buck converter, the voltage-
implementation of the six-phase interleaving circuit in mode-controlled PWM with a PID controller and the phase
Simulink and the six phase control signal waveforms shift interleaving circuit. The multi-phase converter has been
respectively. simulated to obtain the necessary waveforms that describe
converter system operation under steady-state and transient
conditions, using the design parameters tabulated in table 4.
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Fig. 9 Simulink schematic diagram illustrating the implementation of
interleaved six-phase buck converter circuit with a PID controller
TABLE IV
THE CONVERTER MAIN CIRCUIT PARAMETERS
Fig. 10 Current and voltage output ripples
Parameter Name Symbol Value Units
Input voltage Vi 42 V
Output voltage Vo 14 V
Fig.11 shows the steady-state waveforms of the individual
Number of phases N 6 -
cell currents, the total output inductor current and the output
Inductor value L 2.4 µH
voltage. The simulated results show that the curves of the
individual cell currents are balanced and the time interleaved
Capacitor value C 300 µF
of the cells is apparent from the relative time delay of each
Load resistance RL 0.196
cell's inductor current. The inductor current in each cell rises
Switching frequency fs 100 kHz
to 30A during each switching period and goes through an
interval in the discontinuous conduction mode.
A. Ripple Cancellation
The first step in the analysis of the multi-phase
interleaved converter system is to investigate the effectiveness
of ripple-cancellation related to the variation of current and
voltage as a function of the number of cells. Table 5 shows a
summary of results generated by Simulink during the
simulation of four interleaved converter with the same control
design strategies.
TABLE V
OUTPUT VOLTAGE AND CURRENT RIPPLES VERSUS THE NUMBER OF CELLS
Number of phases 4 6 8 10
Output voltage ripple 8.7m 2 mV 1.1m 0.5m
V V V
Output current ripple 45mA 9mA 6mA 3.2m
A
From the results it can be observed that the converter
achieves a very good current and voltage ripple cancellation
for four-cells and above. Though, eight or ten-cells produce a
better ripple-cancellation, however, the cost outweigh the
gains in accuracy. The results also show that the EMI filter is
not needed to reduce the peak to peak voltage ripple on the
14V terminal. This may lead to the elimination or redesign of
the protection circuitry connected to the 14V bus. It also can
be seen from Fig 10 that the ripple of the output voltage and
the total inductor current of the power converter system are
better than the desired specified limits indicated in table 1.
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7. World Academy of Science, Engineering and Technology 39 2010
Fig .11 Top trace is the individual cell currents then total output Fig. 12 Transient response of the output voltage to step change in
current and bottom trace is the output voltage of the converter system load
The sum of the individual cell currents result in a total It can be seen that the output voltage undershoot varies
current of 71A with a ripple current of around 9mA which is from 13.12V to 13.28V while the overshoot from 14.74V to
less than the individual cell ripple current. The simulated 14.89V, when the load at the output of the converter system
results indicate that, the operation of the power converter was suddenly changed from 50% to 75% and to full-load
system is stable and accurate. The converter is able to respond (1kW). The results show that the performance of the system is
and produce the desired stable output voltage and deliver the stable and well behaved under load variations (disturbances)
required total output current to the load with very low ripple. and the output voltage remains within the desired specified
As a result, no negative effect on the connected loads, such as limits presented earlier in table 1.
small motors, lights and accessories.
C. Input Voltage Variation
B. Transient Simulation for Load Variation In real conditions, the alternator output voltage ranges from
The interleaved dc/dc buck converters are used as power 30V to 50V during normal operation, with nominal voltage of
source to resistive and dynamic loads (motors) in passenger 42V. To study this line of variation, a step change in the input
car and these loads could be categorized into; voltage from 33V to 50V is applied to the model. Fig.13
shows a transient response of the output voltage behaviour
• Small motors (2 to 8A @12V). waveform due to sudden changes in the input voltage of the
• Very small motors ( less than 2A @12V ) power converter system.
• Lighting system: internal lights, external lights, At the beginning of the cycle, at time t=0.004s, the input
head lights. voltage suddenly rises from nominal system voltage of 42V to
• ECU and Key-off loads. 50V. The maximum output voltage (bottom trace) transient is
15.09V, but after a short period of time this error is leveled out
The electrical loads demand varies and depends upon the in approximately 200ms with a maximum overshot of 1.09V.
weather and the driving conditions. A full load condition is At instant time of t=0.01s, when the input voltage suddenly
rarely present for a prolonged period of time and most of the reduces from 50V to 33V, the output maximum transient
devices run at light loads (stand-by-mode) for most of the voltage is 11.704V. The settling time to return to 14V is
time. To study the effect of the load variation on the dynamic approximately 0.4ms with maximum overshot of 2.296V.
behavior of the converter system, the load at the output of the Finally, at time t=0.016s, when the input voltage suddenly
converter system is suddenly changed from 50% to 75% and to increases from, 33V to the nominal system voltage, the
100% and than back from 100% to 75% and 50% of the full maximum output transient voltage is 5.85V. The settling time
load at time t=0.002, 0.004 and 0.006s respectively. The for this is approximately 0.4ms with a maximum overshot of
simulated results are shown in Fig.12. 1.85V. The simulation results illustrate that the converter
system has a strong immunity against line voltage disturbances
even with the 12V energy storage battery being absent.
Fig. 13 Output voltage due to step line voltage disturbance.
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8. World Academy of Science, Engineering and Technology 39 2010
D. Load and Supply Voltage Variations ACKNOWLEDGMENT
The combinations of both the supply-voltage and load The authors would like to thanks Mr. Salah Deen Kalifa,
variations that occur in the converter system have been Director of Higher Institute of Electronic Professions, Libya
simulated and the outputs are presented in Fig.14. for the friendship and overall support.
It can be observed that the designed system has a low-
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