Analysis and Optimization of Quantum circuits

•

0 likes•33 views

The aim of this novel work is to fill a gap that has appeared in the reversible computing, emerging domain of Futuristic Quantum Information Science. Themes in Quantum Information Science have been an emerging domain. This work targets the basic level void by terminology coverage of quantum circuit synthesis. Chapters introduce the synthesis approach of reversible adders, comparator, code converters, and median filter. This book then covers decomposition, mapping and optimization tools in quantum logic circuits. The flow of the work is organized to understand the synthesis of a quantum circuit that begins using quantum gates and then move into physical implementation on nano-computing technology.

Engineering

Neeraj Misra
Bandan Kumar Bhoi
Analysis and Optimization
of Quantum circuits
The aim of this novel work is to fill a gap that has appeared in the
reversible computing, emerging domain of Futuristic Quantum Information
Science. Themes in Quantum Information Science have been an emerging
domain. This work targets the basic level void by terminology coverage of
quantum circuit synthesis. Chapters introduce the synthesis approach of
reversible adders, comparator, code converters, and median filter. This
book then covers decomposition, mapping and optimization tools in
quantum logic circuits. The flow of the work is organized to understand
the synthesis of a quantum circuit that begins using quantum gates and
then move into physical implementation on nano-computing technology.
Neeraj Kumar Misra is Associate Professor and
Academic In-charge in the Department of Electronics
and Communication Engineering at Bharat Institute
of Engineering & Technology (BIET), Hyderabad.
Bandan Kumar Bhoi is an AP in the Department of
Electronics and Tele-communication Engineering at
Veer Surendra Sai University of Technology, Burla
Odisha
978-613-9-91317-6

Artificial neural networks have already shown their success in face recognition and similar complex pattern recognition tasks. However, a major disadvantage of the technique is that it is extremely slow during training for larger classes and hence not suitable for real-time complex problems such as pattern recognition. This is an attempt to develop a parallel framework for the training algorithm of a perceptron. In this paper, two general architectures for a Multilayer Perceptron (MLP) have been demonstrated. The first architecture is All-Class-in-One-Network (ACON) where all the classes are placed in a single network and the second one is One-Class-in-One-Network (OCON) where an individual single network is responsible for each and every class. Capabilities of these two architectures were compared and verified in solving human face recognition, which is a complex pattern recognition task where several factors affect the recognition performance like pose variations, facial expression changes, occlusions, and most importantly illumination changes. Experimental results show that the proposed OCON structure performs better than the conventional ACON in terms of network training convergence speed and which can be easily exercised in a parallel environment.

Abstract matsumuraharmonylab

GUI based handwritten digit recognition using CNN

Abhishek Tiwari

2 cd M.TECH ( PDF FILE )

rajasthan technical university kota

This Research paper discusses the study and analysis conducted during this research on various techniques in biometric domain. A close glance on biometric enhancement techniques and their limitations are presented in this research paper. This process would enable researcher to understand the research contributions in the area of DCT and DFT based recognition and security, locate some crucial limitations of these notable research. This paper having summary about the different research papers that applicable to our topic of research which mentioned above. Biometric Recognition and security is a most important subject of research in this area of image processing.

CVधीरेन्द्र शर्मा

Formulation of modularity factor for community detection applyingIAEME Publication

T L Singal's Optical_Fiber_Communications_leafletT. L. Singal

Dp33701704

IJERA Editor

Design and Testability of Diverse Reversible Error Control Circuits

VIT-AP University

The authors of this work realized a need for a conservative reversible nanocircuit which can involve quantum computing to researchers and other having a requirement for a cognizance of the emerging field, and the work attempts to meet that need. The book beginnings with a basic to the topic of quantum computing. Followed by one supporting chapters on quantum computing and testing. Nanocircuit design for the low-cost nano-communication framework is addressed in two chapters; one on error control, decoder and the other on testing reversible logic circuit. This leads to another contribution of this work in that synthesis, optimization, testing of reversible circuits, quantum circuit, and logic around quantumdot cellular automata build through the chapters. A Verilog code describes the algorithm of the HDLQ model components including all elements for the reversible gate is available for the readers. We hope that researchers and instructors find this book useful in their basic learning resource.

Novel conservative reversible error control circuits based on molecular QCA

VIT-AP University

Quantum-dot cellular automata are a prominent part of the nanoscale regime. They use a quantum cellular based architecture which enables rapid information process with high device density. This paper targets the two kinds of novel error control circuits such as Hamming code, parity generator and checker. To design the HG-PP (HG = Hamming gate, PP = parity preserving), NG-PP (NG = new gate) are proposed for optimising the circuits. Based on the proposed gates and a few existing gates, the Hamming code and parity generator and checker circuits are constructed. The proposed gates have been framed and verified in QCA. The simulation outcomes signify that their framed circuits are faultless. In addition to verification, physical reversible is done. The reversible major metrics such as gate count, quantum cost, unit delay, and garbage outputs, uses best optimisation results compared to counterparts. They can be utilised as a low power error control circuit applied in future communication systems.

What's hot

2 cd M.TECH ( M S WORD FILE )

rajasthan technical university kota

(Dc a-3) 1834902148,jinnat naher hira

Hira Moni

Presentation parallelsystem(1.1)cegonsoft1999

Rajat CV

RajatNagpal22

Resume

Vikrant kumar

Mahesh kendre CV NEWMahshkendre

Stress, strain and orientation fields in deformed FCC polycrystals

Srihari Sundar

Mohamad Aziz ResumeMohamad Aziz

A Guide to Academic Research - new book being released this month

Prof. Mohandas K P

Basic Structural Modeling

AMITJain879

Learning to learn with meta learning

ShreeGowriRadhakrish

Icacci presentation-isi-text categorization

vinaykumar R

Cs 2022

SurenderKumarJha

Take-Home Exam Questions on Brain and Computation'butest

Similarity validation based nonlocal means image denoising

Projectsatbangalore

DCT AND DFT BASED BIOMETRIC RECOGNITION AND MULTIMODAL BIOMETRIC SECURITY

IAEME Publication

CVधीरेन्द्र शर्मा

Formulation of modularity factor for community detection applyingIAEME Publication

T L Singal's Optical_Fiber_Communications_leafletT. L. Singal

Dp33701704

IJERA Editor

What's hot (20)

2 cd M.TECH ( M S WORD FILE )

(Dc a-3) 1834902148,jinnat naher hira

Presentation parallelsystem(1.1)

Rajat CV

Resume

Mahesh kendre CV NEW

Stress, strain and orientation fields in deformed FCC polycrystals

Mohamad Aziz Resume

A Guide to Academic Research - new book being released this month

Basic Structural Modeling

Learning to learn with meta learning

Icacci presentation-isi-text categorization

Cs 2022

Take-Home Exam Questions on Brain and Computation'

Similarity validation based nonlocal means image denoising

DCT AND DFT BASED BIOMETRIC RECOGNITION AND MULTIMODAL BIOMETRIC SECURITY

Formulation of modularity factor for community detection applying

T L Singal's Optical_Fiber_Communications_leaflet

Dp33701704

Similar to Analysis and Optimization of Quantum circuits

Design and Testability of Diverse Reversible Error Control Circuits

VIT-AP University

Novel conservative reversible error control circuits based on molecular QCA

VIT-AP University

15UEC804_Project work_second Review.pptx

balum34

M.tech Term paper report | Cognitive Radio Network

Shashank Narayan

Project Presentation(Phase II) DRAFT-1.pptx

KaliLinux64

Mohamad Aziz Resume

Mohamad Aziz

5.local community detection algorithm based on minimal cluster

Venkat Projects

Shreyan cv4apr2020 (1)

ShreyanDatta

Introduction of Wireless Sensor Network

Muhammad Kaife Uddin

Ameliorate the performance using soft computing approaches in wireless networks

IJECEIAES

Wireless sensor networks are an innovative and rapidly advanced network occupying the broad spectrum of wireless networks. It works on the principle of “use with less expense, effort and with more comfort.” In these networks, routing provides efficient and effective data transmission between different sources to access points using the clustering technique. This work addresses the low-energy adaptive clustering hierarchy (LEACH) protocol’s main backdrop of choosing head nodes based on a random value. In this, the soft computing methods are used, namely the fuzzy approach, to overcome this barrier in LEACH. Our approach’s primary goal is to extend the network lifetime with efficient energy consumption and by choosing the appropriate head node in each cluster based on the fuzzy parameters. The proposed clustering algorithm focused on two fuzzy inference structures, namely Mamdani and Sugeno fuzzy logic models in two scenarios, respectively. We compared our approach with four existing works, the conventional LEACH, LEACH using the fuzzy method, multicriteria cluster head delegation, and fuzzy-based energy efficient clustering approach (FEECA) in wireless sensor network. The proposed scenario based fuzzy LEACH protocol approaches are better than the four existing methods regarding stability, network survivability, and energy consumption.

Fast and accurate primary user detection with machine learning techniques for...

nooriasukmaningtyas

Spectrum decision is an important and crucial task for the secondary user to avail the unlicensed spectrum for transmission. Managing the spectrum is an efficient one for spectrum sensing. Determining the primary user presence in the spectrum is an essential work for using the licensed spectrum of primary user. The information which lacks in managing the spectrum are the information about the primary user presence, accuracy in determining the existence of user in the spectrum, the cost for computation and difficult in finding the user in low signal-to noise ratio (SNR) values. The proposed system overcomes the above limitations. In the proposed system, the various techniques of machine learning like decision tree, support vector machines, naive bayes, ensemble based trees, nearest neighbour’s and logistic regression are used for testing the algorithm. As a first step, the spectrum sensing is done in two stages with orthogonal frequency division multiplexing and energy detection algorithm at the various values of SNR. The results generated from the above algorithm is used for database generation. Next, the different machine learning techniques are trained and compared for the results produced by different algorithms with the characteristics like speed, time taken for training and accuracy in prediction. The accuracy and finding the presence of the user in the spectrum at low SNR values are achieved by all the algorithms. The computation cost of the algorithm differs from each other. Among the tested techniques, k-nearest neighbour (KNN) algorithm produces the better performance in a minimized time.

Performance analysis of ml and mmse decoding using

eSAT Publishing House

IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology

Based on pause time comparative analysis made among bee ant colony optimized ...Alexander Decker

Y4502158163

IJERA Editor

International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.

Resume

Vivek Pahwa

Ieee projects 2011 ns 2 SBGC ( Trichy, Madurai, Chennai, Dindigul, Natham, Pu...

SBGC

IEEE Projects 2011 NS-2 Chennai, IEEE Projects 2011 NS-2 Trichy, IEEE Projects 2011 NS-2 Thanjavur, IEEE Projects 2011 NS-2 Pudukkottai, IEEE Projects 2011 NS-2 Perambalur, IEEE Projects 2011 NS-2 Karur, IEEE Projects 2011 NS-2 Namakkal, IEEE Projects 2011 NS-2 Bangalore, IEEE Projects 2011 NS-2 Hyderabad, IEEE Projects 2011 NS-2 Cochin, IEEE Projects 2011 NS-2 Ernakulam, IEEE Projects 2011 NS-2 Thiruvananthapuram, IEEE Projects 2011 NS-2 Vellore, IEEE Projects 2011 NS-2 Madurai, IEEE Projects 2011 NS-2 Salem, IEEE Projects 2011 NS-2 Ariyalur, IEEE Projects 2011 NS-2 Erode, IEEE Projects 2011 NS-2 Coimbatore, IEEE Projects 2011 NS-2 Dindigul, IEEE Projects 2011 NS-2 Manapparai, IEEE Projects 2011 NS-2 Kakinada, IEEE Projects 2011 NS-2 Nellore, IEEE Projects 2011 NS-2 Chittoor, IEEE Projects 2011 NS-2 Tirupati, IEEE Projects 2011 NS-2 Tirunelveli, IEEE Projects 2011 NS-2 Mumbai, IEEE Projects 2011 NS-2 Pune, IEEE Projects 2011 NS-2 Nagpur

Recent articles published in VLSI design & Communication Systems

VLSICS Design

International Journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas. Authors are solicited to contribute to this journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the VLSI design & Communications.

Resume

Vivek Pahwa

drc 3-2.pptx

Ersandeepkanaujia

load balancing[Plag Report].pdf

PrinceSingh130849

Similar to Analysis and Optimization of Quantum circuits (20)

Design and Testability of Diverse Reversible Error Control Circuits

Novel conservative reversible error control circuits based on molecular QCA

15UEC804_Project work_second Review.pptx

M.tech Term paper report | Cognitive Radio Network

Project Presentation(Phase II) DRAFT-1.pptx

Mohamad Aziz Resume

5.local community detection algorithm based on minimal cluster

Shreyan cv4apr2020 (1)

Introduction of Wireless Sensor Network

Ameliorate the performance using soft computing approaches in wireless networks

Fast and accurate primary user detection with machine learning techniques for...

Performance analysis of ml and mmse decoding using

Based on pause time comparative analysis made among bee ant colony optimized ...

Y4502158163

Resume

Ieee projects 2011 ns 2 SBGC ( Trichy, Madurai, Chennai, Dindigul, Natham, Pu...

Recent articles published in VLSI design & Communication Systems

Resume

drc 3-2.pptx

load balancing[Plag Report].pdf

More from VIT-AP University

Quantum Computing

VIT-AP University

The impact of quantum computing has been widely recognised in the engineering domain. The age of quantum computing has arrived, and with it comes the ability to easily solve exponential problems. This book is written by me to meet current academic demands. The book is designed to address the most important aspects of the subject of Quantum Computing. The publication of the book "Quantum Computing" is the culmination of numerous years of research and teaching in academia. It is given in a way that is straightforward to comprehend. The undergraduates, and graduate students may all benefit from reading this book. We have given our very best effort to bring you accurate book material. The book explains the fundamentals of this topic in simple, straightforward language. The most efficient approach to go through this book is to grasp the underlying fundamental as well as mathematical concepts. The chapters are meant to stand on their own. This book is not intended to be theoretical; rather, it will serve to familiarise you with the fundamental of quantum computing, like applications, multiple-qubit systems, quantum state transformations, quantum gates and quantum circuits, tools for quantum computing, bell states, quantum Parallelism, quantum Algorithms: Shor’s Algorithm, Grover’s Algorithm, Quantum Hardware and software, Quantum Cryptography and Security, Quantum Error Rates and Quantum Noise, Quantum Fourier Transform, Quantum Machine Learning and so on. The model questions and multiple-choice questions that are provided at the end of the book have been chosen to improve readers' understanding, as well as their performance in exams and key employment. We warmly welcome and would be very appreciative of any comments or recommendations, that will help us enhance the overall quality of the book.

Cost-effective architecture of decoder circuits and futuristic scope in the e...

VIT-AP University

The goal of Very Large Scale Integration (VLSI) over the past several decades has been the miniaturisation of chip size, along with increased computing speed and decreased power consumption. Miniaturization of size, high computing speed, and low power consumption does not appear to be able to meet the demand of consumers at this time. Quantum dot cellular automata is a more promising methodology that has the potential to optimise power, speed, and area at the nano-computing scale. In the field of nanocomputing, combinational circuit design has seen a significant amount of research and development effort. This article presents a comprehensive review as well as a proposed design of a decoder that has an accurate clocking mechanism and the best design. In terms of cell count, total area, cell area, area coverage, latency, QCA cost, and quantum cost, the novel 2-to-4 decoder achieves values of 87, 0.10, 0.0281, 28.1, 2.5, 0.625, 0.25, which is better than the prior work. Comparing the 2-to-4 decoder design to a standard design, the improvement is 72.64 %, 80 %, 72.71 %, 28.1 %, 64.28 %, 97,44 and 92.85 % in cell count, total area, cell area, area coverage, latency, QCA cost, and Quantum cost, respectively.

Information Theory and Coding

VIT-AP University

Efficient architecture for arithmetic designs using perpendicular NanoMagneti...

VIT-AP University

As the process of scaling down continues at a rapid pace, there is a growing need for an alternative semiconductor device to replace CMOS. One of the alternatives that attracted a lot of attention is called nanomagnetic logic (NML). This is because NML delivers a high device density in addition to a non-volatility of stored information, beyond-CMOS technologies, and device work at room temperature. It is necessary to lower the circuit density and increase the speed of circuits like adders. Using emerging NML logic, we created a full-adder, and ripple carry adder (RCA) with a minimum area. As a result, the invented multilayer-based decimal design makes use of RCA, and full-adder, for innovative 3D topology. We used an NML framework built with perpendicular nanomagnetic (pNML) layers to simulate the characteristics of these devices. With the adder designs that have been offered the latency values are relatively low while performing exhaustive testing. Using pNML technology, a decimal adder has been constructed for the first time in the literature. In addition, simulations are carried out with the help of the Modelsim simulator. During the process of nanomagnetic designing consideration is given to both of these aspects as latency and area. To create an NML circuit, the tool MagCAD is employed. Results are better using the pNML environment-based full adder, RCA and decimal adder.

An in-depth study of the electrical characterization of supercapacitors for r...

VIT-AP University

The Energy Storage System (ESS) is geared toward sophisticated systems with increased operating time for a variety of real-time applications such as an electric vehicle, a WSN (Wireless Sensor Network), a Capa bus, and so on. Its primary focus is on supplying these kinds of systems with additional capacity in recent development, and this will continue to be its primary focus. Because of their exceptionally high specific power, rapid charging, and low ESR (Effective Series Resistance), electric double-layer (EDLC) capacitors or supercapacitors are encouraged for use because they can be integrated more easily with battery technology that can be used in electric vehicles and other electronic devices. The supercapacitor calls for a precise and accurate characterization in order to facilitate the development of improved applications and more effective energy storage devices and technologies. In this article, we studied various supercapacitor electrode components, electrolytic solutions, analogous circuit models, electrical energy storage properties, and some real-time supercapacitor applications in the automotive, manufacturing, construction, and consumer electronics industries. In addition, we have discussed on hybrid material that was just recently developed with the goal of enhancing the conductivity and effectiveness of supercapacitors. Aside from this, we have discussed about the behaviour of supercapacitors in terms of how their behaviour is dependent on current and voltage with detailed analysis.

Algorithm of Reading Scientific Research Article

VIT-AP University

Agenda 1. Algorithm of Reading Scientific Research Article 2. Importance of ORCID ID 3. Benefit of ORCiD 4. Process of Connecting Scopus database to ORCiD iD 5. Registration of ORCiD iD Account 6. Scopus Database connected to ORCiD iD 7. BibTeX Entry to add all the publication at the same time in ORCiD iD 8. Process of importing BibTex into ORCiD Database 9. Using Bibtex include all the research article in one time

How to Calculate the H-index and Effective Response of Reviewer

VIT-AP University

Importance of ORCHID ID

VIT-AP University

Writing and Good Abstract to Improve Your Article Quality

VIT-AP University

Fundamental of Electrical and Electronics Engineering.pdf

VIT-AP University

Content Addressable Memory Design in 3D pNML for Energy-Aware Sustainable Com...

VIT-AP University

As the semiconductor industry strives for downsizing and high speed, it is confronted with increasing scaling uncertainty as devices decrease to the nanoscale. Nano-magnetic logic (NML) is an alternative approach to synthesize the digital logic circuits with high-density and lowpower consumption. We introduced an optimal design of content addressable memory (CAM) memory based on perpendicular nano-magnetic logic (pNML). The main aim of this implementation is to synthesize CAM memory in terms of latency and other design parameters. The implementation of the design is a multilayer approach, which is optimal. The synthesis approach and optimization are perfectly scalable across layout construction of designs. Here a new logic gate in pNML technology is designed which is mainly used for matching of two input numbers. According to insight, both memory unit and a matching unit in the pNML are introduced in the state-of-the-artwork for the ¯rst time to synthesize design in high-speed pNML application. MAGCAD tool is used for the design of all the proposed pNML layouts.

Performance Evaluation & Design Methodologies for Automated 32 Bit CRC Checki...

VIT-AP University

For design methodology of CRC or cyclic redundancy check is very used technique for error checking and shows the transmission reliability we are using the HDLC block. HDLC block is very useful in data communication these block operated in data link layer. For design methodology of CRC is to generate the CRC polynomial using XOR’s gate and shift register these polynomial are implement on software Xilinx Plan Ahead 13.1 and verify for simulation result for random testing of CRC bit on receiver side same result are obtained to show that it is more reliable.

Sensor Energy Optimization Using Fuzzy Logic in Wireless Sensor Networking

VIT-AP University

Wireless sensor networks is challenging in that it requires an enormous breadth of knowledge from an enormous variety of disciplines. A lot of study has been done to minimize the energy used in routing and number of protocols has been developed. These protocols can be classified as - Hierarchical, data centric, location based and Network flow protocols. In this paper, we are particularly focusing on hierarchical protocols. In such types of protocols, the energy efficient clusters are formed with a hierarchy of cluster heads. Each cluster has its representative cluster head which is responsible for collecting and aggregating the data from its respective cluster and then transmitting this data to the Base Station either directly or through the hierarchy of other cluster heads. Fuzzy logic has been successfully applied in various areas including communication and has shown promising results. However, the potentials of fuzzy logic in wireless sensor networks still need to be explored. Optimization of wireless sensor networks involve various tradeoffs, for example, lower transmission power vs. longer transmission duration, multi-hop vs. direct communication, computation vs. communication etc. Fuzzy logic is well suited for application having conflicting requirements. Moreover, in WSN, as the energy metrics vary widely with the type of sensor node implementation platform, using fuzzy logic has the advantage of being easily adaptable to such changes.

Approach to design a high performance fault-tolerant reversible ALU

VIT-AP University

In the digital circuit design, the primary factors are low power and a high packing density. The reversible logic circuit in quantum-dot cellular automata (QCA) framework is hoped to be effective in addressing the factor of power consumption at nanoscale regime. Fault tolerant circuits are suited of interruption of errors at the outputs. This manuscript focuses the design of ALU in QCA-based and propose new parity preserving gate. It has been introduced that new reversible gate, namely, universal parity preserving gate (UPPG), to optimise the ALU circuits. An algorithm and lemmas are shown in designing ALU. The ALU generates a number of arithmetic and logical function with using only less architectural complexity. Most importantly circuit design focuses on optimising the gate count and quantum cost. In addition to optimisation, the workability of UPPG gate is tested by QCA and the simulation result obtained ensures the correctness of the design.

A modular approach for testable conservative reversible multiplexer circuit f...

VIT-AP University

Quantum technology has an attractive application nowadays for its minimizing the energy dissipation, which is a prominent part of any system-level design. In this article, the significant module of a multiplexer, an extended to n:1 is framed with prominent application in the control unit of the processor. The proposed multiplexer modules are framed by the algorithm, which is extended perspective based. Further, quantum cost and gate count are less to ensure the efficient quantum computing framed. In addition, the QCA computing framework is an attempt to synthesize the optimal primitives in conservative reversible multiplexer in nano-electronic confine application. The developed lemmas is framed to prove the optimal parameters in the reversible circuit. Compared with existing state-of-art-works, the proposed modular multiplexer, the gate count, quantum cost and unit delay are optimal.

Analysis on Fault Mapping of Reversible Gates with Extended Hardware Descript...

VIT-AP University

Quantum-dot cellular automata is a modern computing paradigm, conceived in feature of nanometer scale with high integration density, and significant low power. For the QCA technology, making these high-density design means an increase in the complexity which in turn leads to growth in the number of faults. The defect model presented in this paper categorized into two types, which include single missing and additional cell considering for QCA fault. Proposed gates have been designed in the QCA and verified. The proposed Fredkin gate design has been compared with an existing design, and 43% and 70% improvement in cell count and area respectively are revealed. Also, the Toffoli design in QCA which achieve some parameters such as cell complexity of 39, and the average fault tolerance of 53.5%. The polarization value for both single cells missing an addition cell missing has been studied to explain the logic signal strength effect physically. A QCA framework for the 3-input Ex-OR, 2:1 multiplexer, Fredkin, and Toffoli gate for the fault problem in which reliability analysis based on Hardware description language for QCA devices (HDLQ) is discussed and verified on the fault pattern look-up table.

A Novel and Efficient Design for Squaring Units by Quantum-Dot Cellular Automata

VIT-AP University

Quantum cell automata (QCA) are the best possible alternative to the conventional CMOS technology due to its low power consumption, less area and high-speed operation. This paper describes synthesizable QCA implementation of squaring. Vedic sutras used for squaring are defined over algorithm construction. Based on the concept of the Vedic sutra, this paper has carried out 2-bit square and 4-bit square, projective to affine logic gates construction. Importantly for miniaturization of devices, the QCA based square is the operation on which the area of circuits relies on. This means that significantly lower QCA parameters can be used in the square than in other competitive square circuits such as Wallace, Dadda, serial parallel, and Baugh-Wooley.

A Redundant Adder Architecture in Ternary Quantum-Dot Cellular Automata

VIT-AP University

Now researchers are moving toward emerging technologies to replace the conventional CMOS technology. Quantum-dot cellular automata (QCA) are one of them for high-performance computing circuits. Ternary QCA is one of the finest research areas in this domain for replacement of binary logic. In this paper, we proposed a new redundant adder architecture using Ternary QCA technology. Our proposed architecture has 233 numbers of cells with an area of 0.35 μm2. All the proposed ternary logic layouts are implemented in TQCA designer tool.

Implementation of Non-restoring Reversible Divider Using a Quantum-Dot Cellul...

VIT-AP University

The CMOS-based integrated circuit may scale down to nanometer range. The primary challenge is to further downscale the device and high-energy dissipation. Reversible logic does not dissipate energy and no information loss. In this way, the state-of-the-art technology such as QCA was forced toward high-speed computing with negligible energy dissipation in the physical foreground. This work targets the design of non-restoring reversible divider circuit and its implementation in QCA. We have utilized few 2 × 2 FG and 4 × 4 HNG gates as the block construction and also show the QCA implementation having cost-efficient approach. Further, the divider circuit has synthesized with FG and HNG gates and QCA implementation. This divider circuit inherits many benefits such as fewer garbage outputs, reduce quantum cost are achieved, and also reduced QCA primitives can be improved by using efficient QCA layout scheme. Simulation investigations have been verified by QCA Designer. The proposed non-restoring divider also compares the reversible metrics results with some of other existing works.

An Explicit Cell-Based Nesting Robust Architecture and Analysis of Full Adder

VIT-AP University

Moving towards micrometre scale to nanometre scale device shrinks down emerging nanometre technology such as quantum-dot cellular automata as a nesting success. The introduced architecture is robust where the explicit design of full adder and full subtraction uses for Ex-OR design. A new architecture of Ex-OR based on one majority gate is proposed, which its most optimized architecture and its placement of cells from the novel design. The analysis based on simulation showed that the introduced Ex-OR and full adder makes only 11 and 46 cells count, respectively. In proposed Ex-OR design, first output is received with no any latency which can be a suitable design for implementation of the high-speed full adder design. In addition, power estimation results are obtained after simulation of proposed designs in QCAPro tool. Therefore, the novel designs improve the energy dissipation parameters such as mean leakage energy dissipation, mean switching energy dissipation and total energy dissipation 75, 11.28 and 82.19% in comparison with the most robust design in existing.

More from VIT-AP University (20)