This document discusses different types of addressing modes used in instruction sets. It describes op-codes, which specify operations like addition, and operands, which are the data being operated on. Instructions contain an op-code and an address field specifying the location of operands. Addressing modes include three-address, two-address, one-address, one-and-a-half address, and zero address. Three-address uses three operands, two-address uses two, one-address implicitly uses an accumulator, one-and-a-half uses a register and memory, and zero-address uses a stack.

1. ADDRESSING MODE:
If we talk about instruction set. Instruction set main contain op-code and operand.
OP-CODE:
Op-code means operation like addition, subtraction,division ,multiplication etc.
OPERAND:
Operand mean data which specifies what data is to be operated.
Any instruction issued by the processor must carry at least two types of information.
 OP-CODE
 ADDRESS FIELD
OP-CODE OPERAND

2. …CONTINUED
OP-CODE
Which specifies the operation to be performed like addition
ADDRESS FIELD
Which contain the location of operands i.e register or memory location.
Instruction may be classified on the no of operands as: three address, two address, one and half address, one address
and zero address.
It should be noted that in presenting these we would use convention operation, source, destination, to express any
instruction.
Convention operation.
In that convention operation represent the operation to be performed, for example, add, subtract, write
or read.

3. …CONTINUED
Source.
The source field represent the operand. The source operand can be a constant, a value stored in a register, or a
value stored in a memory.
Destination.
The destination field represent the place where the result of the operation is to be stored.for example, a
register or a memory location.
Three address instruction.
OPERATION.
ADD -1, ADD-2, ADD-3
In this form, each of add-1 add-2 add-3 refers to a register or to a memory location.
For example
ADD R1,R2.R3

4. …CONTINUED
OPERATION: addition.
It indicates that the value to be stored are those in register R1 and R2 that result should be stored in
register R3
R1+R2----------R3
TWO ADDRESS INSTRUCTION.
OPERATION.
ADD -1, ADD-2
In this form , each of add-1 add-2 refers to a register or to a memory location.
For example
ADD R1,R2

5. …CONTINUED
OPERATION: addition.
This instruction add the content of register R1 to the content of register R2 and store the
result in register R2
R1+R2---------R2
The operation performed by the three address instruction ADD A,B,C can be performed by the two
address instruction MOVE B,C and ADD A,C . This is because the first instruction moves the contents
of location B into location C and second instruction add the contents of location A to those of
location C.
ONE ADDRESS INSTRUCTION.

6. …CONTINUED:
OPERATION.
ADD R1
ACCUMULATOR.
In this case the instruction implicity refers to a register called accumulator Racc, such that the contents of the
accumulator is added to the contents of the register R1 and the result are stored back in to the accumulator.
ONE-AND-HALF ADDRESS INSTRUCTION.
Between the two and the one address instruction , there can be a one-and-half instruction. The
instruction uses two types of addressing , that is, a register and a memory location , it is called a one-and-half-address
instruction.
For example.
ADD B,R1
In this case, the instruction add the content of register R1 to the content of memory location B and store the result in
register R1.

7. …CONTINUED
ZERO ADDRESS INSTRUCTION.
These are the instruction that we use stack operation.
STACK OPERATION.
A stack is an abstract data type that serves as a collection of elements, with two main
principle operation push, which adds an element to the collection, and. Pop, which removes the most
recently added element that was not yet removed.
EXAMPLE
ADD (SP)+,(SP).
The instruction adds the contents of the stack location pointed to by the SP to those pointed to by the
SP+1 and stores the result on the stack in the location pointed to by the current value of the SP.