1. 2009 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS 2009) December 7-9, 2009
TP2-A-2
978-1-4244-5016-9/09/$25.00 c 2009 IEEE – 397 –
A Wide-Range Frequency Synthesizer Using a Compensated
Phase-Rotating Technique for Digital TV Tuners
Ching-Yuan Yang, Hsin-Ming Wu, Jun-Hong Weng and Ping-Heng Wu
Department of Electrical Engineering, National Chung Hsing University
250, Kuo-Kuang Road, Taichung, Taiwan 40254
Email: ycy@nchu.edu.tw
ABSTRACT
Fabricated in a 0.18-μm CMOS technology, a
wide-range fractional-N frequency synthesizer with a
phase-compensated technique is presented. While using a
630-960 MHz LC-type VCO, the synthesizer can provide
the range of 55 to 960 MHz with a band-selecting struc-
ture to satisfy the ATSC applications. Using the
phase-rotating concept, the synthesizer can achieve the
fractional functionality, instead of the conventional ΔΣ
interpolation. The measured results show phase noise is
−123 dBc/Hz at 1-MHz offset. The lock time is below 6
μs from 640 MHz to 930 MHz.
I. INTRODUCTION
As the TV broadcasting technology is moving from
analog to digital era, nowadays the Digital TV (DTV)
has surged for the demand of high performance solutions
in the DTV tuners. The frequency synthesizer is a key
component in the DTV tuner, which requires wide fre-
quency range, low phase noise and small channel space
(6 MHz). For ATSC specifications, the required fre-
quency range is around from several teen to nine hundred
MHz and the phase noise needs to be smaller than −100
dBc/Hz at 1-MHz offset [1]. In order to overcome such
wide frequency range and low phase noise at the same
time, the LC-type voltage-controlled oscillator (VCO)
and band-selector circuits are employed in this work [2].
In addition, the fractional-N architecture can conquer the
issue of channel space at a higher reference frequency.
There are many kind of architecture of fractional-N
topology. Using divisor average technique is very popu-
lar. However, this technique may introduce fractional
spur, which is caused by the phase error exhibiting in the
PLL. The traditional method to suppress the spurs is us-
ing a DAC to compensate the error on control voltage of
the VCO. Unfortunately, this principle shorting is the
imprecise result due to mismatching effects. Using ΔΣ
modulation can provide a general solution to reduce the
fractional spurs, at the cost the hardware complexity and
more power consumption.
In this paper, we propose a simple implementation of
a fractional-N synthesizer by using a phase-rotating
technique with phase compensation to achieve factional
operation [3] [4]. The main motive of this architecture is
to achieve a “really” divisor instead of an “average” di-
visor. Moreover, the higher reference frequency can get a
wider loop bandwidth and faster settling time, and even
the quantization noise can be attenuated by the filtering
characteristic.
II. SYSTEM AND CIRCUIT IMPLEMENTATION
The block diagrams of the proposed frequency syn-
thesizer are shown in Fig. 1, which consists of a phase
frequency detector (PFD), a charge pump (CP), a
second-order loop filter (LPF), a VCO, a band selector
(BS), and a fractional frequency divider. The fractional
divider is made of a delay-lock loop (DLL), a phase se-
lector (PS) and an accumulator (ACC). The ACC is a
3-bit digital circuit. By clocking the ACC, the overall
fine-fractional division is created which has more resolu-
tion than the basic division by divide-by-N divider in the
PLL. An expression applicable to the fractional synthesis
in the frequency synthesizer is the following:
8
fra
div int
N
N N= + (1)
where Ndiv is the resulting divisor. While using a 630-960
MHz LC-type VCO, the PLL synthesizer can provide its
output to cover the range of ATSC specifications with a
band-selecting structure. Since the channel space is 6
MHz in ASTC application and the reference frequency is
designed to 48 MHz, the divisor can be represented as
(1), where Nint is from 13 to 20 and Nfra is from 0 to 7.
PFD CP
LPF
VCO BS
BS
DLL
outf
÷ NPS
ACC
fraN intN
reff
(Fractional input) (Integral input)
55 - 960 MHz
Adder
Overflow
Fractional divider
Fig.1 Proposed system architecture.
A. Voltage Control Oscillator
The generic LC-type VCO scheme is adopted in
this work, as shown in Fig. 2, which is a push-pull LCψ
oscillator. The double cross-connection of an NMOS
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2. 2009 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS 2009) December 7-9, 2009
– 398 –
and a PMOS differential pairs in positive feedback
generates a negative resistance to compensate the
parasitic parallel resistance of the LCψtank for os-
cillation to occur. The MOS varactor is used for fre-
quency tuning. Compared with the ring topologies,
the LC-type VCO has better phase-noise behavior
and frequency stability at high frequency, but at the
cost of narrow tuning range. In this work, we utilize a
band selection technique to extend the tuning range.
+
−
outV
CV
Fig. 2 LC-type VCO
B. Band Selector
Since this basic LC VCO has the inherent drawback
in tuning range less than 40%, a band selector circuit is
employed to achieve a very wider frequency range for
ATSC, 90% at least. Fig.3 depicts this circuit which is
composed of a cascade divide-by-1/1.5 cell [5] and di-
vide-by-2 chains. The outputs of divide-by-1 and di-
vide-by-1.5 cells are needed to prevent non-overlap. For
example, if the designed VCO has a tuning range of 630
to 960 MHz, then the band selector can provide conti-
nuous frequencies from 55 to 960 MHz. The frequency
bands are shown in Table I and the simulated
tuned-frequency characteristic is shown in Fig.4, which
provides eight bands to fully cover the required range.
1
÷1.5
vcof
630 - 960
÷2
÷2
÷2
÷2
÷2
÷2
Mux
#1
#2 #4 #6
#3 #5
#7
#8
outf
55 - 960
MHzMHz
BS
Fig. 3 Band selector
TABLE I BAND SELECT V.S. OUTPUT FREQUENCY
Band Frequency range (MHz)
#1 630 − 960
#2 420 − 640
#3 315 − 480
#4 210 − 320
#5 158 − 240
#6 105 − 160
#7 79 − 120
#8 55 − 80
Control Voltage (V)
OutputFrequency(Hz)
Fig. 4 Simulated tuned-frequency characteristic
C. Fractional Divider with Phase Compensation
The fractional divider is illustrated in Fig. 5, which
has 5 bits of integer and 3 bits of fraction to decide the
divisor. The eight delay cells are introduced to form a
delay line in the DLL. A DLL is a circuit which synchro-
nizes f3 and f4 using the PD to function phase locking.
The inputs, f3 and f1, are fed into both PD and VCDL
and the output f4 is a delayed version of f1. Through the
feedback operation, the closed loop tends to insert a de-
lay time of one clock of the VCO, i.e., Tvco, between two
inputs for clock synchronization. The DLL is used to
generate eight-phase sequences.
The f1 and f2 are synchronized by DFF1 and DFF2,
and f3 and f4 have a difference of a VCO clock cycle by
DFF3 and DLL. f5 is used to delay a VCO clock that can
prevent glitch while triggering accumulator. As the frac-
tional input is 0, the phase selector will pick one of eight
phases, and resulting output frequency is equal to di-
vide-by-N; otherwise, the fractional operation is done.
While the fraction operation is working, the phase
error accumulation appears. Thus, a phase-compensated
regime is required. For an example of Nfra = 1, the output
period of the fractional divider is given by
1
( )
8
div vcoT T N= ⋅ + (2)
The instantaneous timing error due to the divide-by-N
operation is calculated by
1
8
N vco div vcot NT T TΔ = − = − (3)
Likewise, the instantaneous timing error due to the di-
vide-by-(N+1) operation is determined by
1
7
( 1)
8
N vco div vcot N T T T+Δ = + − = (4)
Therefore, the timing error sequence is {…, −Tvco/8,
−Tvco/8, −Tvco/8, −Tvco/8, −Tvco/8, −Tvco/8, −Tvco/8,
7Tvco/8, …} for divisor of N+1/8. Since the phase error
can be easily predicted, a phase compensated regime
operates through a digital control circuit. The detailed
diagram regarding the phase compensation is shown in
Fig. 6. Similarly, the other divisor’s timing error se-
quence can be predicted as well. Even for the worst case,
if the divisor is N+7/8, the sequence of timing error is
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3. 2009 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS 2009) December 7-9, 2009
– 399 –
{…, −7Tvco/8, Tvco/8, Tvco/8, Tvco/8, Tvco/8, Tvco/8, Tvco/8,
Tvco/8, …}. From above timing error sequence, the tim-
ing error can be predicted by 3-bit fractional input, i.e.,
the accumulator input. Using the compensated technique
to correctly change divided ratio of N and N+1, the tim-
ing error can be calibrated by an opposite timing error.
As a result, a real fractional divider can be effectively
implemented, unlike the traditional averaging technique
on the dual-modulus divider.
÷N/N+1
vcof
D Q
Clk
D Q
Clk
DFF1
DFF2
Phase Selector
PD CP
Delay -LockedLoop
ACC
D Q
Clk
DFF3
DQ
Clk
DFF4
divf
vcof
fraN
(Fractionalinput)
intN
(Integral input)
Adder
Overflow
f1
f2 f3
f4
f5
Fig. 5 Programmable fractional divider
divf
Content
of ACC
Outputs
of DLL
Divide -by
N/N+1
vcof
vcoT
vcoN T⋅ ( 1) vcoN T+ ⋅
N÷ ( 1)N÷ + N÷
( 1/8) vcoN T+ ⋅ ( 1/8) vcoN T+ ⋅
7/8 8/8
1/8
Fig. 6 Timing diagram of phase compensation
III. EXPERIMENTAL RESULTS
The fractional-N frequency synthesizer for ATSC
specifications was fabricated in a 0.18-ȝm 1P6M CMOS
technology. The chip micro photo of this work is shown
in Fig. 7 with the die area of 1.2¯1.2 mm2
including I/O
pads. The loop filter of the PLL is external, due to large
capacitance in this design. Operating under 1.8-V supply
voltage, the synthesizer employs the reference frequency
of 48 MHz and the designed loop bandwidth is about 300
kHz. The VCO provides the frequency range of 630
MHz to 960 MHz to support the PLL to provide the fre-
quency range of 55 MHz to 960 MHz. Fig. The fast set-
tling time is below 6 μs, as shown in Fig. 8, which hops
from 10 mV to 1.6 V with the operating frequencies
hopping from 640 MHz to 930 MHz. Next, the minimum
channel space of 6 MHz is illustrated in Fig.9, while
switching the fractional LSB. The output frequency
changes from 636 MHz to 642 MHz precisely with a
channel step. Fig. 10 shows the phase noise measurement
which is −123 dBc/Hz at 1-MHz offset. The overall spe-
cifications of the frequency synthesizer with several prior
works are given in Table II [2] [6] [7]. These three de-
sign challenge is conquered in this work.
IV. CONCLUSION
In this paper, the fractional-PLL-based frequency
synthesizer applying in ATSC DTV-tuners under
0.18-μm CMOS technology is presented. The wide fre-
quency range of 55 to 960 MHz can be covered, and the
phase noise is −123 dBc/Hz at 1-MHz offset. A narrow
channel space can be easy to achieve due to phase com-
pensation technique, and is verified by the measurement.
Moreover, the fast settling time due to employing higher
reference frequency is also verified in this work. The
measured results show that the proposed architecture
does achieve the low-noise wide-range function as
expected.
Fig. 7 Chip microphotograph
6us
Fig. 8 Measured waveform of settling time
ACKNOWLEDGMENT
The authors would like to thank the National
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4. 2009 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS 2009) December 7-9, 2009
– 400 –
Science Council, Taiwan, for the financial support and
the National Chip Implementation Center (CIC), Taiwan,
for the infrastructure support. This work was sponsored
by NSC95-2220-E-005-003.
Fig. 9 Channel space verification
Fig. 10 Measured phase noise: −123dBc/Hz @ 1-MHz
offset
REFERENCES
[1] ATSC Digital Television Standards, A/53 Part 1~6, Jan.
3, 2007.
[2] Y-C Yang, F-T. Lee, and S.-S. Lu, “A single-VCO frac-
tional-N frequency synthesizer for digital TV tuners,”
in IEEE Int. Microw. Sym., Jun. 2007, pp. 1545-1548.
[3] W. Rhee and A. Ali, “An on-chip phase compensation
technique in fractional-N frequency synthesis,” in IEEE
Int. Sym. Circuits & Syst., May 1999, pp. 363-366.
[4] C.-Y. Yang, J.-W. Chen, and M.-T. Tsai, “A
high-frequency phase-compensation fraction-N fre-
quency synthesizer,” in IEEE Int. Sym. Circuits & Syst.,
May 2005, pp. 5901-5904.
[5] Y.-C Yang, S.-A. Yu, T. Wang, S.-S. Lu, “A dual-mode
truly modular programmable fractional divider based on
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[6] M. Marutani, H. Anbutsu, M. Kondo, N. Shirai, H. Ya-
mazaki, Y. Watanabe, “An 18mW 90 to 770MHz syn-
thesizer with agile auto-tuning for digital TV-tuners”, in
IEEE ISSCC Dig. Tech. Papers, Feb. 2006, pp. 681-
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[7] E.-Y. Sung, K.-S. Lee, D.-H. Baek, Y.-J. Kim, B.-H.
Park, “A wideband 0.18-ȝm CMOS ǻȈ fractional-N
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in IEEE Asian Solid-State Circuits Conf., Nov. 2005, pp.
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TABLE II COMPARISON OF PERFORMANCE WITH PRIOR WORKS
References
Technology
(ȝm)
Specification
Tuning Range
(MHz)
Phase noise
(dBc/Hz)
Settling
Time
Power
Consumption
This work 0.18 CMOS ATSC 55 − 960 −123 @1MHz 6 ȝs 40 mW
[2] 0.18 CMOS
DVB-T
ISDB-T
2300 − 3500 <−130 @1MHz <70 ȝs 154 mW
[6] 0.11 CMOS
ISDB-T
ISDB-TBS
90 − 770
−100 @100KHz
−150 @1MHz
80ȝs 18 mW
[7] 0.18 CMOS DVB-T 900 − 1730 −136 @1.25MHz <300ȝs 28 mW
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