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Introduction to Microprocessors
                                                         Yuri Baida
                                                  yuri.baida@gmail.com
                                                yuriy.v.baida@intel.com

                                                   October 2, 2010


MDSP Project | Intel Lab
Moscow Institute of Physics and Technology
Agenda

     • Background and History
           – What is a microprocessor?
           – What is the history of the development of the microprocessor?
           – How does transistor scaling affect processor design?
     • PC Components
           – What are the major PC components and their functions?
           – What is memory hierarchy and how has it changed?
     • Processor Architecture
           – What are processor architecture and microarchitecture?
           – How does microarchitecture affect performance?
           – How is performance measured?



MDSP Project | Intel Lab
Moscow Institute of Physics and Technology                                   2
Background and History




MDSP Project | Intel Lab
Moscow Institute of Physics and Technology                    3
What is a Microprocessor?

     • Microprocessor is a computer Central Processing Unit (CPU)
       on a single chip.
     • It contains millions of transistors connected by wires




                  Core i7 die                Core i7 in package
                    Picture: Intel              Picture: Ebbesen

MDSP Project | Intel Lab
Moscow Institute of Physics and Technology                          4
Electrical Numerical Integrator and Calculator

     • Designed for the U.S. Army's Ballistic Research Laboratory
     • Built out of
           – 17,468 vacuum tubes
           – 7,200 crystal diodes
           – 1,500 relays
           – 70,000 resistors
           – 10,000 capacitors
     •   Consumed 150 kW of power
     •   Took up 72 m2
     •   Weighted 27 tons
     •   Suffered a failure on average every 6 hours


MDSP Project | Intel Lab
Moscow Institute of Physics and Technology                          5
Electrical Numerical Integrator and Calculator




                                 Glen Beck and Betty Snyder program the ENIAC
                                       in BRL building 328. (Picture: U.S. Army)

MDSP Project | Intel Lab
Moscow Institute of Physics and Technology                                         6
The First Transistor was Created in 1947

                                             • Used germanium
                                             • Created by a team lead
                                               by William Shockley at Bell Labs
                                             • Shockley later shared the Noble
                                               prize in physics
                                             • Shockley semiconductors
                                               was founded in Palo Alto in 1955
                                             • In 1957 Bob Noyce, Gordon Moore,
                                               and 6 others (“Traitorous Eight”)
                                               leave to found Fairchild
                                               semiconductor


MDSP Project | Intel Lab
Moscow Institute of Physics and Technology                                         7
The First Integrated Circuit was Created
     in 1959
    • Proposed independently by Bob Noyce at Fairchild
      and Jack Kilby at Texas Instruments
    • In 1968 Noyce and Moore leave Fairchild to found Intel
    • Contained a single transistor and supporting components




                                             The first working integrated
                                             circuit (1.6 × 11.1 mm)
                                             Picture: TI

MDSP Project | Intel Lab
Moscow Institute of Physics and Technology                                  8
Intel Created the First Commercial
     Microprocessor
     • Introduced the 4004 in 1971, contained 2,300 transistors
     • Had roughly the same processing power as ENIAC




                        Intel 4004           Intel founders (circa 1978)
                          Picture: Intel              Picture: Intel

MDSP Project | Intel Lab
Moscow Institute of Physics and Technology                                 9
IBM Introduced its Original PC in 1981

     • Used the Intel 8088 processor containing 29,000 transistors
     • Used operating system (MS-DOS) designed by Microsoft




                                IBM PC          Intel 8088
                               Picture: Intel    Picture: Intel

MDSP Project | Intel Lab
Moscow Institute of Physics and Technology                           10
Microprocessor Evolution

     • 4004 transistors were 10 µm across
     • Pentium 4 transistors are 0.13 µm across
     • Human hair is about 100 µm across

     • Smaller transistors allow
           – More transistors per chip
           – More processing per clock cycle
           – Faster clock rates
           – Smaller/cheaper chips




MDSP Project | Intel Lab
Moscow Institute of Physics and Technology        11
Microprocessor Evolution




                Picture: Intel


MDSP Project | Intel Lab
Moscow Institute of Physics and Technology   12
Moore’s Law
     • "The number of transistors incorporated in a chip
       will approximately double every 24 months.“ (1965)




                       Picture: Intel
MDSP Project | Intel Lab
Moscow Institute of Physics and Technology                  13
Computer Components




MDSP Project | Intel Lab
Moscow Institute of Physics and Technology                   14
PC Components

     • Microprocessor — performs all computations
     • Cache — fast memory which holds current data and program
     • Main memory — larger DRAM memory contains more data
     • Chipset — controls communication between components
     • Motherboard — circuit board which holds all the above
       components
     • Peripheral cards — controls added computer accessories




MDSP Project | Intel Lab
Moscow Institute of Physics and Technology                        15
Memory Hierarchy


                    ~1kB                     Register File      ~1ns

                ~100kB                       Level 1 Cache      ~5ns

                   ~1MB                      Level 2 Cache     ~10ns

                 ~10MB                       Level 3 Cache     ~20ns

                  ~10GB                      Main Memory       ~100ns

                   ~1TB                       Hard Drive       ~10ms

                Capacity                                     Access Time

MDSP Project | Intel Lab
Moscow Institute of Physics and Technology                                 16
Processor-Memory Performance Gap

                  1000                                                                      CPU
                                                            60% per year
                                                            (Doubles every 1.5 year)

                    100
                                                                                   Performance gap
      Relative                                                                     (Grows 50% per year)
    performance
                      10
                                                        9% per year
                                                        (Doubles every 10 year)             DRAM


                         1



                                                            Years
                     Source: David Patterson, UC Berkeley

MDSP Project | Intel Lab
Moscow Institute of Physics and Technology                                                           17
Memory Hierarchy Evolution


              CPU                              CPU                         CPU

                                                L1                     I     D

                              Cache                           L2                  L2


            Chipset               DRAM        Chipset         DRAM     Chipset    DRAM




                       386                              486                 Pentium
            No on-die cache.                 Level 1 cache on-die.   Separate Instruction
             Level 1 cache                      Level 2 cache          and Data Caches
            on motherboard                     on motherboard

MDSP Project | Intel Lab
Moscow Institute of Physics and Technology                                                  18
Memory Hierarchy Evolution


                CPU                               CPU                   CPU


               I     D              L2        I        D            I         D
                                                  L2                    L2
                                                                        L3
             Chipset             DRAM
                                             Chipset       DRAM
                                                                   Chipset        DRAM



                   Pentium II                     Pentium III           Core i7
          Separate bus to L2                 L2 cache on-die      L3 cache on-die
            cache in same
               package

MDSP Project | Intel Lab
Moscow Institute of Physics and Technology                                               19
Microprocessor Architecture




MDSP Project | Intel Lab
Moscow Institute of Physics and Technology                  20
What is Architecture?

     • Computer architecture is defined by the instructions
       a processor can execute
     • Programs written for one processor can run
       on any other processor of the same architecture
     • Current architectures include:
           – IA32 (x86)
           – IA64
           – ARM
           – PowerPC
           – SPARC




MDSP Project | Intel Lab
Moscow Institute of Physics and Technology                    21
What are Instructions?

     • Instructions are the most basic actions the processor can
       take:
           – ADD AX, BX                      — Add value AX to BX and store in AX
           – CMP AX, 5                       — Compare value in AX to 5
           – JE 16                           — Jump ahead 16 bytes if comparison was equal
     • High level programming languages (C, C++, Java) allow many
       processor instructions to be written simply:
           – if (A + B = 5) then… — Jump if sum of A and B is 5
     • Every program must be converted to the processor
       instructions of the computer it will be run on




MDSP Project | Intel Lab
Moscow Institute of Physics and Technology                                                   22
What is Microarchitecture?

     • Microarchitecture is the steps a processor takes
       to execute a particular set of instructions
     • Processors of the same architecture have the same
       instructions but may carry them out in different ways
     • Microarchitecture Features:
           – Cache memory
           – Pipelining
           – Out-of-Order Execution
           – Superscalar Issue




MDSP Project | Intel Lab
Moscow Institute of Physics and Technology                     23
Simplified Microprocessor
                                                                  Fetch Unit gets
                                    Decode                        the next instruction from the cache.
               Fetch

                                   Floating          Multimedia   Decode Unit determines
                                     Point              Unit      type of instruction.
                                      Unit
                                                                  Instruction and data sent to
                                     Write                        Execution Unit.
            L2 Cache
                                                                  Write Unit stores result.
                                             Integer Unit




       Instruction                           Fetch     Decode Execute   Write




MDSP Project | Intel Lab
Moscow Institute of Physics and Technology                                                               24
Sequential Processing (386)
         Cycle            1              2    3       4       5        6       7       8       9

         Instr1        Fetch        Decode Execute   Write

         Instr2                                              Fetch   Decode Execute   Write

         Instr3                                                                               Fetch

     • Sequential processing works on one instruction at a time




MDSP Project | Intel Lab
Moscow Institute of Physics and Technology                                                            25
Pipelined Processing (486)
         Cycle            1              2      3       4        5       6        7       8       9

         Instr1        Fetch        Decode Execute    Write

         Instr2                       Fetch   Decode Execute   Write

         Instr3                               Fetch   Decode Execute   Write

         Instr4                                       Fetch    Decode Execute   Write

         Instr5                                                Fetch   Decode Execute   Write

         Instr6                                                        Fetch    Decode Execute   Write

     • Latency — elapsed time from start to completion of a particular task
     • Throughput — how many tasks can be completed per unit of time
     • Pipelining only improves throughput
           – Each job still takes 4 cycles to complete
     • Real life analogy: Henry Ford’s automobile assembly line

MDSP Project | Intel Lab
Moscow Institute of Physics and Technology                                                               26
In-Order Pipeline (486)
         Cycle            1              2      3        4          5          6          7          8          9

         Instr1        Fetch        Decode             Execute             Write

         Instr2                       Fetch   Decode         Wait         Execute     Write

         Instr3                               Fetch    Decode           Wait         Execute     Write

         Instr4                                         Fetch    Decode            Wait         Execute     Write

         Instr5                                                  Fetch     Decode             Wait         Execute

         Instr6                                                            Fetch      Decode             Wait


     • In-Order execution requires instructions to be executed
       in the original program order




MDSP Project | Intel Lab
Moscow Institute of Physics and Technology                                                                           27
Out-of-Order Execution (Pentium II)
         Cycle            1              2      3        4          5       6         7        8       9

         Instr1        Fetch        Decode             Execute             Write

         Instr2                       Fetch   Decode         Wait         Execute    Write

         Instr3                               Fetch    Decode Execute      Write

         Instr4                                         Fetch    Decode    Wait     Execute   Write

         Instr5                                                  Fetch    Decode Execute      Write

         Instr6                                                            Fetch    Decode Execute    Write

     • Program Order vs Dataflow Order
     • Dataflow: data-driven scheduling of events
           – The start of an event should be enabled by the availability of its required input
             (data dependency)
     • Real life analogy: taking tests — work on the questions you know first

MDSP Project | Intel Lab
Moscow Institute of Physics and Technology                                                                    28
Superscalar Issue (Pentium)
         Cycle            1              2      3        4         5       6         7        8      9

         Instr1        Fetch        Decode             Execute            Write

         Instr2        Fetch        Decode              Wait             Execute    Write

         Instr3                       Fetch   Decode Execute     Write

         Instr4                       Fetch   Decode              Wait             Execute   Write

         Instr5                               Fetch    Decode Execute     Write

         Instr6                               Fetch    Decode Execute     Write

         Instr7                                         Fetch    Decode Execute     Write

         Instr8                                         Fetch    Decode Execute     Write


     • Superscalar issue allows multiple instructions to be issued
       at the same time

MDSP Project | Intel Lab
Moscow Institute of Physics and Technology                                                               29
Microarchitecture and Performance

     • Performance is measured by how long a processor takes to
       run a program
     • Time is reduced by increasing Instructions Per Cycle (IPC) and
       clock rate
     • Microarchitecture affects IPC and clock rate:
           – More pipe stages
                  – Less work in each cycle means better clock rate
                  – More dependencies means worse IPC
           – Superscalar Issue and Out-of-Order Execution
                  – Parallel work means better IPC
                  – More complexity can mean worse clock rate




MDSP Project | Intel Lab
Moscow Institute of Physics and Technology                              30
Measuring Processor Performance

     • Clock Rate
           – Simplest but not especially accurate
     • Instructions Per Cycle (IPC)
           – Not meaningful without clock rate
           – Varies from program to program
     • SPEC Performance
           – Standard Performance Evaluation Corporation
           – Tests PCs using benchmark suite of programs
                  – SPECint: Integer intensive programs
                  – SPECfp: Floating point intensive programs
     • TPC Performance
           – Transaction Performance Council
           – Tests servers and workstations

MDSP Project | Intel Lab
Moscow Institute of Physics and Technology                      31
Acknowledgements

     • These slides contain material developed and copyright by:
           – Grant McFarland (Intel)
           – Mark Louis (Intel)
           – Arvind (MIT)
           – Joel Emer (Intel/MIT)




MDSP Project | Intel Lab
Moscow Institute of Physics and Technology                         32
[2010 10-02] intro to microprocessors[1]

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[2010 10-02] intro to microprocessors[1]

  • 1. Introduction to Microprocessors Yuri Baida yuri.baida@gmail.com yuriy.v.baida@intel.com October 2, 2010 MDSP Project | Intel Lab Moscow Institute of Physics and Technology
  • 2. Agenda • Background and History – What is a microprocessor? – What is the history of the development of the microprocessor? – How does transistor scaling affect processor design? • PC Components – What are the major PC components and their functions? – What is memory hierarchy and how has it changed? • Processor Architecture – What are processor architecture and microarchitecture? – How does microarchitecture affect performance? – How is performance measured? MDSP Project | Intel Lab Moscow Institute of Physics and Technology 2
  • 3. Background and History MDSP Project | Intel Lab Moscow Institute of Physics and Technology 3
  • 4. What is a Microprocessor? • Microprocessor is a computer Central Processing Unit (CPU) on a single chip. • It contains millions of transistors connected by wires Core i7 die Core i7 in package Picture: Intel Picture: Ebbesen MDSP Project | Intel Lab Moscow Institute of Physics and Technology 4
  • 5. Electrical Numerical Integrator and Calculator • Designed for the U.S. Army's Ballistic Research Laboratory • Built out of – 17,468 vacuum tubes – 7,200 crystal diodes – 1,500 relays – 70,000 resistors – 10,000 capacitors • Consumed 150 kW of power • Took up 72 m2 • Weighted 27 tons • Suffered a failure on average every 6 hours MDSP Project | Intel Lab Moscow Institute of Physics and Technology 5
  • 6. Electrical Numerical Integrator and Calculator Glen Beck and Betty Snyder program the ENIAC in BRL building 328. (Picture: U.S. Army) MDSP Project | Intel Lab Moscow Institute of Physics and Technology 6
  • 7. The First Transistor was Created in 1947 • Used germanium • Created by a team lead by William Shockley at Bell Labs • Shockley later shared the Noble prize in physics • Shockley semiconductors was founded in Palo Alto in 1955 • In 1957 Bob Noyce, Gordon Moore, and 6 others (“Traitorous Eight”) leave to found Fairchild semiconductor MDSP Project | Intel Lab Moscow Institute of Physics and Technology 7
  • 8. The First Integrated Circuit was Created in 1959 • Proposed independently by Bob Noyce at Fairchild and Jack Kilby at Texas Instruments • In 1968 Noyce and Moore leave Fairchild to found Intel • Contained a single transistor and supporting components The first working integrated circuit (1.6 × 11.1 mm) Picture: TI MDSP Project | Intel Lab Moscow Institute of Physics and Technology 8
  • 9. Intel Created the First Commercial Microprocessor • Introduced the 4004 in 1971, contained 2,300 transistors • Had roughly the same processing power as ENIAC Intel 4004 Intel founders (circa 1978) Picture: Intel Picture: Intel MDSP Project | Intel Lab Moscow Institute of Physics and Technology 9
  • 10. IBM Introduced its Original PC in 1981 • Used the Intel 8088 processor containing 29,000 transistors • Used operating system (MS-DOS) designed by Microsoft IBM PC Intel 8088 Picture: Intel Picture: Intel MDSP Project | Intel Lab Moscow Institute of Physics and Technology 10
  • 11. Microprocessor Evolution • 4004 transistors were 10 µm across • Pentium 4 transistors are 0.13 µm across • Human hair is about 100 µm across • Smaller transistors allow – More transistors per chip – More processing per clock cycle – Faster clock rates – Smaller/cheaper chips MDSP Project | Intel Lab Moscow Institute of Physics and Technology 11
  • 12. Microprocessor Evolution Picture: Intel MDSP Project | Intel Lab Moscow Institute of Physics and Technology 12
  • 13. Moore’s Law • "The number of transistors incorporated in a chip will approximately double every 24 months.“ (1965) Picture: Intel MDSP Project | Intel Lab Moscow Institute of Physics and Technology 13
  • 14. Computer Components MDSP Project | Intel Lab Moscow Institute of Physics and Technology 14
  • 15. PC Components • Microprocessor — performs all computations • Cache — fast memory which holds current data and program • Main memory — larger DRAM memory contains more data • Chipset — controls communication between components • Motherboard — circuit board which holds all the above components • Peripheral cards — controls added computer accessories MDSP Project | Intel Lab Moscow Institute of Physics and Technology 15
  • 16. Memory Hierarchy ~1kB Register File ~1ns ~100kB Level 1 Cache ~5ns ~1MB Level 2 Cache ~10ns ~10MB Level 3 Cache ~20ns ~10GB Main Memory ~100ns ~1TB Hard Drive ~10ms Capacity Access Time MDSP Project | Intel Lab Moscow Institute of Physics and Technology 16
  • 17. Processor-Memory Performance Gap 1000 CPU 60% per year (Doubles every 1.5 year) 100 Performance gap Relative (Grows 50% per year) performance 10 9% per year (Doubles every 10 year) DRAM 1 Years Source: David Patterson, UC Berkeley MDSP Project | Intel Lab Moscow Institute of Physics and Technology 17
  • 18. Memory Hierarchy Evolution CPU CPU CPU L1 I D Cache L2 L2 Chipset DRAM Chipset DRAM Chipset DRAM 386 486 Pentium No on-die cache. Level 1 cache on-die. Separate Instruction Level 1 cache Level 2 cache and Data Caches on motherboard on motherboard MDSP Project | Intel Lab Moscow Institute of Physics and Technology 18
  • 19. Memory Hierarchy Evolution CPU CPU CPU I D L2 I D I D L2 L2 L3 Chipset DRAM Chipset DRAM Chipset DRAM Pentium II Pentium III Core i7 Separate bus to L2 L2 cache on-die L3 cache on-die cache in same package MDSP Project | Intel Lab Moscow Institute of Physics and Technology 19
  • 20. Microprocessor Architecture MDSP Project | Intel Lab Moscow Institute of Physics and Technology 20
  • 21. What is Architecture? • Computer architecture is defined by the instructions a processor can execute • Programs written for one processor can run on any other processor of the same architecture • Current architectures include: – IA32 (x86) – IA64 – ARM – PowerPC – SPARC MDSP Project | Intel Lab Moscow Institute of Physics and Technology 21
  • 22. What are Instructions? • Instructions are the most basic actions the processor can take: – ADD AX, BX — Add value AX to BX and store in AX – CMP AX, 5 — Compare value in AX to 5 – JE 16 — Jump ahead 16 bytes if comparison was equal • High level programming languages (C, C++, Java) allow many processor instructions to be written simply: – if (A + B = 5) then… — Jump if sum of A and B is 5 • Every program must be converted to the processor instructions of the computer it will be run on MDSP Project | Intel Lab Moscow Institute of Physics and Technology 22
  • 23. What is Microarchitecture? • Microarchitecture is the steps a processor takes to execute a particular set of instructions • Processors of the same architecture have the same instructions but may carry them out in different ways • Microarchitecture Features: – Cache memory – Pipelining – Out-of-Order Execution – Superscalar Issue MDSP Project | Intel Lab Moscow Institute of Physics and Technology 23
  • 24. Simplified Microprocessor Fetch Unit gets Decode the next instruction from the cache. Fetch Floating Multimedia Decode Unit determines Point Unit type of instruction. Unit Instruction and data sent to Write Execution Unit. L2 Cache Write Unit stores result. Integer Unit Instruction Fetch Decode Execute Write MDSP Project | Intel Lab Moscow Institute of Physics and Technology 24
  • 25. Sequential Processing (386) Cycle 1 2 3 4 5 6 7 8 9 Instr1 Fetch Decode Execute Write Instr2 Fetch Decode Execute Write Instr3 Fetch • Sequential processing works on one instruction at a time MDSP Project | Intel Lab Moscow Institute of Physics and Technology 25
  • 26. Pipelined Processing (486) Cycle 1 2 3 4 5 6 7 8 9 Instr1 Fetch Decode Execute Write Instr2 Fetch Decode Execute Write Instr3 Fetch Decode Execute Write Instr4 Fetch Decode Execute Write Instr5 Fetch Decode Execute Write Instr6 Fetch Decode Execute Write • Latency — elapsed time from start to completion of a particular task • Throughput — how many tasks can be completed per unit of time • Pipelining only improves throughput – Each job still takes 4 cycles to complete • Real life analogy: Henry Ford’s automobile assembly line MDSP Project | Intel Lab Moscow Institute of Physics and Technology 26
  • 27. In-Order Pipeline (486) Cycle 1 2 3 4 5 6 7 8 9 Instr1 Fetch Decode Execute Write Instr2 Fetch Decode Wait Execute Write Instr3 Fetch Decode Wait Execute Write Instr4 Fetch Decode Wait Execute Write Instr5 Fetch Decode Wait Execute Instr6 Fetch Decode Wait • In-Order execution requires instructions to be executed in the original program order MDSP Project | Intel Lab Moscow Institute of Physics and Technology 27
  • 28. Out-of-Order Execution (Pentium II) Cycle 1 2 3 4 5 6 7 8 9 Instr1 Fetch Decode Execute Write Instr2 Fetch Decode Wait Execute Write Instr3 Fetch Decode Execute Write Instr4 Fetch Decode Wait Execute Write Instr5 Fetch Decode Execute Write Instr6 Fetch Decode Execute Write • Program Order vs Dataflow Order • Dataflow: data-driven scheduling of events – The start of an event should be enabled by the availability of its required input (data dependency) • Real life analogy: taking tests — work on the questions you know first MDSP Project | Intel Lab Moscow Institute of Physics and Technology 28
  • 29. Superscalar Issue (Pentium) Cycle 1 2 3 4 5 6 7 8 9 Instr1 Fetch Decode Execute Write Instr2 Fetch Decode Wait Execute Write Instr3 Fetch Decode Execute Write Instr4 Fetch Decode Wait Execute Write Instr5 Fetch Decode Execute Write Instr6 Fetch Decode Execute Write Instr7 Fetch Decode Execute Write Instr8 Fetch Decode Execute Write • Superscalar issue allows multiple instructions to be issued at the same time MDSP Project | Intel Lab Moscow Institute of Physics and Technology 29
  • 30. Microarchitecture and Performance • Performance is measured by how long a processor takes to run a program • Time is reduced by increasing Instructions Per Cycle (IPC) and clock rate • Microarchitecture affects IPC and clock rate: – More pipe stages – Less work in each cycle means better clock rate – More dependencies means worse IPC – Superscalar Issue and Out-of-Order Execution – Parallel work means better IPC – More complexity can mean worse clock rate MDSP Project | Intel Lab Moscow Institute of Physics and Technology 30
  • 31. Measuring Processor Performance • Clock Rate – Simplest but not especially accurate • Instructions Per Cycle (IPC) – Not meaningful without clock rate – Varies from program to program • SPEC Performance – Standard Performance Evaluation Corporation – Tests PCs using benchmark suite of programs – SPECint: Integer intensive programs – SPECfp: Floating point intensive programs • TPC Performance – Transaction Performance Council – Tests servers and workstations MDSP Project | Intel Lab Moscow Institute of Physics and Technology 31
  • 32. Acknowledgements • These slides contain material developed and copyright by: – Grant McFarland (Intel) – Mark Louis (Intel) – Arvind (MIT) – Joel Emer (Intel/MIT) MDSP Project | Intel Lab Moscow Institute of Physics and Technology 32