This document introduces microprocessors and their history. It discusses how early computers used vacuum tubes and transistors were later developed, leading to integrated circuits and the first microprocessor. It describes the basic components of PCs and how memory hierarchy has evolved with multiple cache levels. The document outlines processor architecture and microarchitecture, how various techniques like pipelining, out-of-order execution, and superscalar issue improve performance. It concludes with how performance is measured.
Research article discussion and validation of a HPLC method for the simultaneous estimation of amlodipine and telmisartan in pharmaceutical dosage form.
A sensitive and simple reversed-phase high-performance liquid chromatographic method (RP-HPLC) was developed and validated for the simultaneous determination of four α-adrenergic receptor blockers: terazosin (TER), alfuzosin (ALF), tamsulosin (TAM) and doxazosin (DOX) using moxifloxacin (MOX) as an internal standard.
Various development trials were performed for the development of a chromatographic system for the estimation of RSV and EZE in their fixed dosage form. On the basis of their structural formula, the reversed-phase liquid chromatography was selected. ... Various columns were available for RP-HPLC method.
Los conectores, tanto internos como externos, de un equipo informático nos van a servir para conectarlo a diversos dispositivos perifericos o añadirle algún componente interno que amplie la funcionalidad del equipo.
Research article discussion and validation of a HPLC method for the simultaneous estimation of amlodipine and telmisartan in pharmaceutical dosage form.
A sensitive and simple reversed-phase high-performance liquid chromatographic method (RP-HPLC) was developed and validated for the simultaneous determination of four α-adrenergic receptor blockers: terazosin (TER), alfuzosin (ALF), tamsulosin (TAM) and doxazosin (DOX) using moxifloxacin (MOX) as an internal standard.
Various development trials were performed for the development of a chromatographic system for the estimation of RSV and EZE in their fixed dosage form. On the basis of their structural formula, the reversed-phase liquid chromatography was selected. ... Various columns were available for RP-HPLC method.
Los conectores, tanto internos como externos, de un equipo informático nos van a servir para conectarlo a diversos dispositivos perifericos o añadirle algún componente interno que amplie la funcionalidad del equipo.
clinical data management in clinical research, helpful for pharmacy, nursing, medical, health care providers, clinical research organization, PharmD, CROs, Clinical trial industry, human biomedical research.
User specification requirements (urs) rashRASHMINasare
user specification requirements, factory acceptance test, & design qualification is the part of validation it is doing because the satisfaction of the customer & full filled the user requirement
Data Integrity in pharmaceutical laboratories is a must, the attached ppt shall help the QC members to understand and develop an integral analytical culture
Design controls are not an easy subject to address during and after the design of medical devices and manufacturing processes. Design controls should drive the device design process, not be an afterthought. This session focuses on treating design as a separate entity within the quality management system, user needs vs. design inputs, continuation of design controls after the transfer process, design review and more.
The Implementing AI: Hardware Challenges, hosted by KTN and eFutures, is the first event of the Implementing AI webinar series to address the challenges and opportunities that realising AI for hardware present.
There will be presentations from hardware organisations and from solution providers in the morning; followed by Q&A. The afternoon session will consist of virtual breakout rooms, where challenges raised in the morning session can be workshopped.
Artificial Intelligence now impacts every aspect of modern life and is key to the generation of valuable business insights.
Implementing AI webinar series is designed for people involved in the management and implementation of AI based solutions – from developers to CTOs.
Find out more: https://ktn-uk.co.uk/news/just-launched-implementing-ai-webinar-series
clinical data management in clinical research, helpful for pharmacy, nursing, medical, health care providers, clinical research organization, PharmD, CROs, Clinical trial industry, human biomedical research.
User specification requirements (urs) rashRASHMINasare
user specification requirements, factory acceptance test, & design qualification is the part of validation it is doing because the satisfaction of the customer & full filled the user requirement
Data Integrity in pharmaceutical laboratories is a must, the attached ppt shall help the QC members to understand and develop an integral analytical culture
Design controls are not an easy subject to address during and after the design of medical devices and manufacturing processes. Design controls should drive the device design process, not be an afterthought. This session focuses on treating design as a separate entity within the quality management system, user needs vs. design inputs, continuation of design controls after the transfer process, design review and more.
The Implementing AI: Hardware Challenges, hosted by KTN and eFutures, is the first event of the Implementing AI webinar series to address the challenges and opportunities that realising AI for hardware present.
There will be presentations from hardware organisations and from solution providers in the morning; followed by Q&A. The afternoon session will consist of virtual breakout rooms, where challenges raised in the morning session can be workshopped.
Artificial Intelligence now impacts every aspect of modern life and is key to the generation of valuable business insights.
Implementing AI webinar series is designed for people involved in the management and implementation of AI based solutions – from developers to CTOs.
Find out more: https://ktn-uk.co.uk/news/just-launched-implementing-ai-webinar-series
IBM and ASTRON 64-Bit Microserver Prototype Prepares for Big Bang's Big Data,...IBM Research
IBM and the Netherlands Institute for Radio Astronomy ASTRON have unveiled the world’s first water-cooled 64-bit microserver. The prototype, which is roughly the size of a smartphone, is part of the proposed IT roadmap for the Square Kilometre Array (SKA), an international consortium to build the world’s largest and most sensitive radio telescope. Scientists estimate that the processing power required to operate the telescope will be equal to several millions of today’s fastest computers.
The microserver’s team has designed and demonstrated a prototype 64-bit microserver using a PowerPC based chip from Freescale Semiconductor running Linux Fedora and IBM DB2. At 133 × 55 mm2 the microserver contains all of the essential functions of today’s servers, which are 4 to 10 times larger in size.
Not only is the microserver compact, it is also very energy-efficient. One of its innovations is hotwater cooling, which in addition to keeping the chip operating temperature below 85 degrees C, will also transport electrical power by means of a copper plate. The concept is based on the same technology IBM developed for the SuperMUC supercomputer located outside of Munich, Germany. IBM scientists hope to keep each microserver operating between 35–40 watts including the system on a chip (SOC) — the current design is 60 watts.
The next step for scientists is to begin to take 128 of the microserver boards using the newest T4240 chips to create a 2U rack unit with 1536 cores and 3072 threads with up to 6 terabytes of DRAM. In addition, they will be adding an Ethernet switch and power module to the integrated water-cooling.
A memristor is an electrical component that limits or regulates the flow of electrical current in a circuit and remembers the amount of charge that has previously flowed through it. Memristors are important because they are non-volatile, meaning that they retain memory without power.
In the world of Very Large Scale Integration (VLSI), the Physical Design process plays a crucial role in transforming a logical design into a physical layout that can be manufactured. Among the various steps involved in the Physical Design flow, Place and Route (PnR) stand out as a critical phase. PnR consists in placing the different components of a design on a chip and routing the connections between them. In this article, we will delve into the PnR flow, exploring its key steps, challenges, and the tools involved.
1. Partitioning:
Partitioning is a preliminary step in the PnR flow that divides the design into manageable blocks or modules based on functionality, hierarchy, or timing constraints. It enables parallel processing during subsequent steps and facilitates easier placement and routing. Partitioning algorithms aim to balance the workload across partitions and minimize inter-partition communication.
2. Floorplanning:
Floorplanning is a critical aspect of the placement process, defining the overall chip's top-level structure and organizing the different functional blocks. It involves allocating space for each block, determining their relative positions, and defining the placement regions. Effective floorplanning ensures proper utilization of available chip areas, reduces congestion, and facilitates efficient routing.
3. Power Planning:
Power planning focuses on distributing power supply and ensuring a stable power delivery network throughout the chip. It involves inserting power distribution networks, decoupling capacitors, and voltage regulators to minimize voltage drop, signal noise, and power supply fluctuations. Power planning techniques aim to optimize power grid layout, reduce IR drop, and mitigate electromigration issues.
4. Placement:
Placement is the first step in the PnR flow and involves determining the optimal location for each logic component on the chip. The primary objective of placement is to minimize wire length, power consumption, and timing delays while adhering to various constraints such as blockages, power grid, and signal integrity.
5. Clock Tree Synthesis (CTS):
Clock Tree Synthesis is a crucial step in PnR flow that ensures the efficient distribution of clock signals to all sequential elements of the design. CTS aims to minimize clock skew, and power dissipation, and provide a balanced clock network. CTS algorithms construct a tree-like structure by inserting buffers and optimizing wire length to achieve reliable clock distribution.
6. Routing:
6.1 Global Routing:
Once the placement is complete, the next step is global routing, which establishes the connections between the placed components. Global routing generates a coarse routing structure using minimum spanning trees, maze routing, or other algorithms. It focuses on achieving reasonable wirelength and reducing congestion without considering the precise details of the interconnects.
A microprocessor is an electronic component that is used by a computer to do its work. It is a central processing unit on a single integrated circuit chip containing millions of very small components including transistors, resistors, and diodes that work together. Some microprocessors in the 20th century required several chips. Microprocessors help to do everything from controlling elevators to searching the Web. Everything a computer does is described by instructions of computer programs, and microprocessors carry out these instructions many millions of times a second. [1]
Microprocessors were invented in the 1970s for use in embedded systems. The majority are still used that way, in such things as mobile phones, cars, military weapons, and home appliances. Some microprocessors are microcontrollers, so small and inexpensive that they are used to control very simple products like flashlights and greeting cards that play music when you open them. A few especially powerful microprocessors are used in personal computers.
Macromolecular crystallography is an experimental technique allowing to explore 3D atomic structure of proteins, used by academics for research in biology and by pharmaceutical companies in rational drug design. While up to now development of the technique was limited by scientific instruments performance, recently computing performance becomes a key limitation. In my presentation I will present a computing challenge to handle 18 GB/s data stream coming from the new X-ray detector. I will show PSI experiences in applying conventional hardware for the task and why this attempt failed. I will then present how IC 922 server with OpenCAPI enabled FPGA boards allowed to build a sustainable and scalable solution for high speed data acquisition. Finally, I will give a perspective, how the advancement in hardware development will enable better science by users of the Swiss Light Source.
Biological screening of herbal drugs: Introduction and Need for
Phyto-Pharmacological Screening, New Strategies for evaluating
Natural Products, In vitro evaluation techniques for Antioxidants, Antimicrobial and Anticancer drugs. In vivo evaluation techniques
for Anti-inflammatory, Antiulcer, Anticancer, Wound healing, Antidiabetic, Hepatoprotective, Cardio protective, Diuretics and
Antifertility, Toxicity studies as per OECD guidelines
Synthetic Fiber Construction in lab .pptxPavel ( NSTU)
Synthetic fiber production is a fascinating and complex field that blends chemistry, engineering, and environmental science. By understanding these aspects, students can gain a comprehensive view of synthetic fiber production, its impact on society and the environment, and the potential for future innovations. Synthetic fibers play a crucial role in modern society, impacting various aspects of daily life, industry, and the environment. ynthetic fibers are integral to modern life, offering a range of benefits from cost-effectiveness and versatility to innovative applications and performance characteristics. While they pose environmental challenges, ongoing research and development aim to create more sustainable and eco-friendly alternatives. Understanding the importance of synthetic fibers helps in appreciating their role in the economy, industry, and daily life, while also emphasizing the need for sustainable practices and innovation.
Unit 8 - Information and Communication Technology (Paper I).pdfThiyagu K
This slides describes the basic concepts of ICT, basics of Email, Emerging Technology and Digital Initiatives in Education. This presentations aligns with the UGC Paper I syllabus.
Embracing GenAI - A Strategic ImperativePeter Windle
Artificial Intelligence (AI) technologies such as Generative AI, Image Generators and Large Language Models have had a dramatic impact on teaching, learning and assessment over the past 18 months. The most immediate threat AI posed was to Academic Integrity with Higher Education Institutes (HEIs) focusing their efforts on combating the use of GenAI in assessment. Guidelines were developed for staff and students, policies put in place too. Innovative educators have forged paths in the use of Generative AI for teaching, learning and assessments leading to pockets of transformation springing up across HEIs, often with little or no top-down guidance, support or direction.
This Gasta posits a strategic approach to integrating AI into HEIs to prepare staff, students and the curriculum for an evolving world and workplace. We will highlight the advantages of working with these technologies beyond the realm of teaching, learning and assessment by considering prompt engineering skills, industry impact, curriculum changes, and the need for staff upskilling. In contrast, not engaging strategically with Generative AI poses risks, including falling behind peers, missed opportunities and failing to ensure our graduates remain employable. The rapid evolution of AI technologies necessitates a proactive and strategic approach if we are to remain relevant.
Model Attribute Check Company Auto PropertyCeline George
In Odoo, the multi-company feature allows you to manage multiple companies within a single Odoo database instance. Each company can have its own configurations while still sharing common resources such as products, customers, and suppliers.
2024.06.01 Introducing a competency framework for languag learning materials ...Sandy Millin
http://sandymillin.wordpress.com/iateflwebinar2024
Published classroom materials form the basis of syllabuses, drive teacher professional development, and have a potentially huge influence on learners, teachers and education systems. All teachers also create their own materials, whether a few sentences on a blackboard, a highly-structured fully-realised online course, or anything in between. Despite this, the knowledge and skills needed to create effective language learning materials are rarely part of teacher training, and are mostly learnt by trial and error.
Knowledge and skills frameworks, generally called competency frameworks, for ELT teachers, trainers and managers have existed for a few years now. However, until I created one for my MA dissertation, there wasn’t one drawing together what we need to know and do to be able to effectively produce language learning materials.
This webinar will introduce you to my framework, highlighting the key competencies I identified from my research. It will also show how anybody involved in language teaching (any language, not just English!), teacher training, managing schools or developing language learning materials can benefit from using the framework.
Introduction to AI for Nonprofits with Tapp NetworkTechSoup
Dive into the world of AI! Experts Jon Hill and Tareq Monaur will guide you through AI's role in enhancing nonprofit websites and basic marketing strategies, making it easy to understand and apply.
Macroeconomics- Movie Location
This will be used as part of your Personal Professional Portfolio once graded.
Objective:
Prepare a presentation or a paper using research, basic comparative analysis, data organization and application of economic information. You will make an informed assessment of an economic climate outside of the United States to accomplish an entertainment industry objective.
The French Revolution, which began in 1789, was a period of radical social and political upheaval in France. It marked the decline of absolute monarchies, the rise of secular and democratic republics, and the eventual rise of Napoleon Bonaparte. This revolutionary period is crucial in understanding the transition from feudalism to modernity in Europe.
For more information, visit-www.vavaclasses.com
June 3, 2024 Anti-Semitism Letter Sent to MIT President Kornbluth and MIT Cor...Levi Shapiro
Letter from the Congress of the United States regarding Anti-Semitism sent June 3rd to MIT President Sally Kornbluth, MIT Corp Chair, Mark Gorenberg
Dear Dr. Kornbluth and Mr. Gorenberg,
The US House of Representatives is deeply concerned by ongoing and pervasive acts of antisemitic
harassment and intimidation at the Massachusetts Institute of Technology (MIT). Failing to act decisively to ensure a safe learning environment for all students would be a grave dereliction of your responsibilities as President of MIT and Chair of the MIT Corporation.
This Congress will not stand idly by and allow an environment hostile to Jewish students to persist. The House believes that your institution is in violation of Title VI of the Civil Rights Act, and the inability or
unwillingness to rectify this violation through action requires accountability.
Postsecondary education is a unique opportunity for students to learn and have their ideas and beliefs challenged. However, universities receiving hundreds of millions of federal funds annually have denied
students that opportunity and have been hijacked to become venues for the promotion of terrorism, antisemitic harassment and intimidation, unlawful encampments, and in some cases, assaults and riots.
The House of Representatives will not countenance the use of federal funds to indoctrinate students into hateful, antisemitic, anti-American supporters of terrorism. Investigations into campus antisemitism by the Committee on Education and the Workforce and the Committee on Ways and Means have been expanded into a Congress-wide probe across all relevant jurisdictions to address this national crisis. The undersigned Committees will conduct oversight into the use of federal funds at MIT and its learning environment under authorities granted to each Committee.
• The Committee on Education and the Workforce has been investigating your institution since December 7, 2023. The Committee has broad jurisdiction over postsecondary education, including its compliance with Title VI of the Civil Rights Act, campus safety concerns over disruptions to the learning environment, and the awarding of federal student aid under the Higher Education Act.
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Normal Labour/ Stages of Labour/ Mechanism of LabourWasim Ak
Normal labor is also termed spontaneous labor, defined as the natural physiological process through which the fetus, placenta, and membranes are expelled from the uterus through the birth canal at term (37 to 42 weeks
Normal Labour/ Stages of Labour/ Mechanism of Labour
[2010 10-02] intro to microprocessors[1]
1. Introduction to Microprocessors
Yuri Baida
yuri.baida@gmail.com
yuriy.v.baida@intel.com
October 2, 2010
MDSP Project | Intel Lab
Moscow Institute of Physics and Technology
2. Agenda
• Background and History
– What is a microprocessor?
– What is the history of the development of the microprocessor?
– How does transistor scaling affect processor design?
• PC Components
– What are the major PC components and their functions?
– What is memory hierarchy and how has it changed?
• Processor Architecture
– What are processor architecture and microarchitecture?
– How does microarchitecture affect performance?
– How is performance measured?
MDSP Project | Intel Lab
Moscow Institute of Physics and Technology 2
4. What is a Microprocessor?
• Microprocessor is a computer Central Processing Unit (CPU)
on a single chip.
• It contains millions of transistors connected by wires
Core i7 die Core i7 in package
Picture: Intel Picture: Ebbesen
MDSP Project | Intel Lab
Moscow Institute of Physics and Technology 4
5. Electrical Numerical Integrator and Calculator
• Designed for the U.S. Army's Ballistic Research Laboratory
• Built out of
– 17,468 vacuum tubes
– 7,200 crystal diodes
– 1,500 relays
– 70,000 resistors
– 10,000 capacitors
• Consumed 150 kW of power
• Took up 72 m2
• Weighted 27 tons
• Suffered a failure on average every 6 hours
MDSP Project | Intel Lab
Moscow Institute of Physics and Technology 5
6. Electrical Numerical Integrator and Calculator
Glen Beck and Betty Snyder program the ENIAC
in BRL building 328. (Picture: U.S. Army)
MDSP Project | Intel Lab
Moscow Institute of Physics and Technology 6
7. The First Transistor was Created in 1947
• Used germanium
• Created by a team lead
by William Shockley at Bell Labs
• Shockley later shared the Noble
prize in physics
• Shockley semiconductors
was founded in Palo Alto in 1955
• In 1957 Bob Noyce, Gordon Moore,
and 6 others (“Traitorous Eight”)
leave to found Fairchild
semiconductor
MDSP Project | Intel Lab
Moscow Institute of Physics and Technology 7
8. The First Integrated Circuit was Created
in 1959
• Proposed independently by Bob Noyce at Fairchild
and Jack Kilby at Texas Instruments
• In 1968 Noyce and Moore leave Fairchild to found Intel
• Contained a single transistor and supporting components
The first working integrated
circuit (1.6 × 11.1 mm)
Picture: TI
MDSP Project | Intel Lab
Moscow Institute of Physics and Technology 8
9. Intel Created the First Commercial
Microprocessor
• Introduced the 4004 in 1971, contained 2,300 transistors
• Had roughly the same processing power as ENIAC
Intel 4004 Intel founders (circa 1978)
Picture: Intel Picture: Intel
MDSP Project | Intel Lab
Moscow Institute of Physics and Technology 9
10. IBM Introduced its Original PC in 1981
• Used the Intel 8088 processor containing 29,000 transistors
• Used operating system (MS-DOS) designed by Microsoft
IBM PC Intel 8088
Picture: Intel Picture: Intel
MDSP Project | Intel Lab
Moscow Institute of Physics and Technology 10
11. Microprocessor Evolution
• 4004 transistors were 10 µm across
• Pentium 4 transistors are 0.13 µm across
• Human hair is about 100 µm across
• Smaller transistors allow
– More transistors per chip
– More processing per clock cycle
– Faster clock rates
– Smaller/cheaper chips
MDSP Project | Intel Lab
Moscow Institute of Physics and Technology 11
12. Microprocessor Evolution
Picture: Intel
MDSP Project | Intel Lab
Moscow Institute of Physics and Technology 12
13. Moore’s Law
• "The number of transistors incorporated in a chip
will approximately double every 24 months.“ (1965)
Picture: Intel
MDSP Project | Intel Lab
Moscow Institute of Physics and Technology 13
15. PC Components
• Microprocessor — performs all computations
• Cache — fast memory which holds current data and program
• Main memory — larger DRAM memory contains more data
• Chipset — controls communication between components
• Motherboard — circuit board which holds all the above
components
• Peripheral cards — controls added computer accessories
MDSP Project | Intel Lab
Moscow Institute of Physics and Technology 15
16. Memory Hierarchy
~1kB Register File ~1ns
~100kB Level 1 Cache ~5ns
~1MB Level 2 Cache ~10ns
~10MB Level 3 Cache ~20ns
~10GB Main Memory ~100ns
~1TB Hard Drive ~10ms
Capacity Access Time
MDSP Project | Intel Lab
Moscow Institute of Physics and Technology 16
17. Processor-Memory Performance Gap
1000 CPU
60% per year
(Doubles every 1.5 year)
100
Performance gap
Relative (Grows 50% per year)
performance
10
9% per year
(Doubles every 10 year) DRAM
1
Years
Source: David Patterson, UC Berkeley
MDSP Project | Intel Lab
Moscow Institute of Physics and Technology 17
18. Memory Hierarchy Evolution
CPU CPU CPU
L1 I D
Cache L2 L2
Chipset DRAM Chipset DRAM Chipset DRAM
386 486 Pentium
No on-die cache. Level 1 cache on-die. Separate Instruction
Level 1 cache Level 2 cache and Data Caches
on motherboard on motherboard
MDSP Project | Intel Lab
Moscow Institute of Physics and Technology 18
19. Memory Hierarchy Evolution
CPU CPU CPU
I D L2 I D I D
L2 L2
L3
Chipset DRAM
Chipset DRAM
Chipset DRAM
Pentium II Pentium III Core i7
Separate bus to L2 L2 cache on-die L3 cache on-die
cache in same
package
MDSP Project | Intel Lab
Moscow Institute of Physics and Technology 19
21. What is Architecture?
• Computer architecture is defined by the instructions
a processor can execute
• Programs written for one processor can run
on any other processor of the same architecture
• Current architectures include:
– IA32 (x86)
– IA64
– ARM
– PowerPC
– SPARC
MDSP Project | Intel Lab
Moscow Institute of Physics and Technology 21
22. What are Instructions?
• Instructions are the most basic actions the processor can
take:
– ADD AX, BX — Add value AX to BX and store in AX
– CMP AX, 5 — Compare value in AX to 5
– JE 16 — Jump ahead 16 bytes if comparison was equal
• High level programming languages (C, C++, Java) allow many
processor instructions to be written simply:
– if (A + B = 5) then… — Jump if sum of A and B is 5
• Every program must be converted to the processor
instructions of the computer it will be run on
MDSP Project | Intel Lab
Moscow Institute of Physics and Technology 22
23. What is Microarchitecture?
• Microarchitecture is the steps a processor takes
to execute a particular set of instructions
• Processors of the same architecture have the same
instructions but may carry them out in different ways
• Microarchitecture Features:
– Cache memory
– Pipelining
– Out-of-Order Execution
– Superscalar Issue
MDSP Project | Intel Lab
Moscow Institute of Physics and Technology 23
24. Simplified Microprocessor
Fetch Unit gets
Decode the next instruction from the cache.
Fetch
Floating Multimedia Decode Unit determines
Point Unit type of instruction.
Unit
Instruction and data sent to
Write Execution Unit.
L2 Cache
Write Unit stores result.
Integer Unit
Instruction Fetch Decode Execute Write
MDSP Project | Intel Lab
Moscow Institute of Physics and Technology 24
25. Sequential Processing (386)
Cycle 1 2 3 4 5 6 7 8 9
Instr1 Fetch Decode Execute Write
Instr2 Fetch Decode Execute Write
Instr3 Fetch
• Sequential processing works on one instruction at a time
MDSP Project | Intel Lab
Moscow Institute of Physics and Technology 25
26. Pipelined Processing (486)
Cycle 1 2 3 4 5 6 7 8 9
Instr1 Fetch Decode Execute Write
Instr2 Fetch Decode Execute Write
Instr3 Fetch Decode Execute Write
Instr4 Fetch Decode Execute Write
Instr5 Fetch Decode Execute Write
Instr6 Fetch Decode Execute Write
• Latency — elapsed time from start to completion of a particular task
• Throughput — how many tasks can be completed per unit of time
• Pipelining only improves throughput
– Each job still takes 4 cycles to complete
• Real life analogy: Henry Ford’s automobile assembly line
MDSP Project | Intel Lab
Moscow Institute of Physics and Technology 26
27. In-Order Pipeline (486)
Cycle 1 2 3 4 5 6 7 8 9
Instr1 Fetch Decode Execute Write
Instr2 Fetch Decode Wait Execute Write
Instr3 Fetch Decode Wait Execute Write
Instr4 Fetch Decode Wait Execute Write
Instr5 Fetch Decode Wait Execute
Instr6 Fetch Decode Wait
• In-Order execution requires instructions to be executed
in the original program order
MDSP Project | Intel Lab
Moscow Institute of Physics and Technology 27
28. Out-of-Order Execution (Pentium II)
Cycle 1 2 3 4 5 6 7 8 9
Instr1 Fetch Decode Execute Write
Instr2 Fetch Decode Wait Execute Write
Instr3 Fetch Decode Execute Write
Instr4 Fetch Decode Wait Execute Write
Instr5 Fetch Decode Execute Write
Instr6 Fetch Decode Execute Write
• Program Order vs Dataflow Order
• Dataflow: data-driven scheduling of events
– The start of an event should be enabled by the availability of its required input
(data dependency)
• Real life analogy: taking tests — work on the questions you know first
MDSP Project | Intel Lab
Moscow Institute of Physics and Technology 28
29. Superscalar Issue (Pentium)
Cycle 1 2 3 4 5 6 7 8 9
Instr1 Fetch Decode Execute Write
Instr2 Fetch Decode Wait Execute Write
Instr3 Fetch Decode Execute Write
Instr4 Fetch Decode Wait Execute Write
Instr5 Fetch Decode Execute Write
Instr6 Fetch Decode Execute Write
Instr7 Fetch Decode Execute Write
Instr8 Fetch Decode Execute Write
• Superscalar issue allows multiple instructions to be issued
at the same time
MDSP Project | Intel Lab
Moscow Institute of Physics and Technology 29
30. Microarchitecture and Performance
• Performance is measured by how long a processor takes to
run a program
• Time is reduced by increasing Instructions Per Cycle (IPC) and
clock rate
• Microarchitecture affects IPC and clock rate:
– More pipe stages
– Less work in each cycle means better clock rate
– More dependencies means worse IPC
– Superscalar Issue and Out-of-Order Execution
– Parallel work means better IPC
– More complexity can mean worse clock rate
MDSP Project | Intel Lab
Moscow Institute of Physics and Technology 30
31. Measuring Processor Performance
• Clock Rate
– Simplest but not especially accurate
• Instructions Per Cycle (IPC)
– Not meaningful without clock rate
– Varies from program to program
• SPEC Performance
– Standard Performance Evaluation Corporation
– Tests PCs using benchmark suite of programs
– SPECint: Integer intensive programs
– SPECfp: Floating point intensive programs
• TPC Performance
– Transaction Performance Council
– Tests servers and workstations
MDSP Project | Intel Lab
Moscow Institute of Physics and Technology 31
32. Acknowledgements
• These slides contain material developed and copyright by:
– Grant McFarland (Intel)
– Mark Louis (Intel)
– Arvind (MIT)
– Joel Emer (Intel/MIT)
MDSP Project | Intel Lab
Moscow Institute of Physics and Technology 32