Thesis_MS

Internally Compensated Linear Low Drop Out Regulator
Design in a Low Cost Pseudo BiCMOS Process.
A thesis submitted to the Department of Electrical and Electronic Engineering (EEE)
of
Bangladesh University of Engineering and Technology (BUET)
in partial fulfillment of the requirement for the degree of
MASTER OF SCIENCE IN ELECTRICAL AND ELECTRONIC ENGINEERING
by
Syed Mustafa Khelat Bari
DEPARTMENT OF ELECTRICAL AND ELECTRONIC ENGINEERING
BANGLADESH UNIVERSITY OF ENGINEERING AND TECHNOLOGY 2008

2
The thesis titled “Internally Compensated Linear Low Drop Out Regulator Design in a
Low Cost Pseudo BiCMOS Process” submitted by Syed Mustafa Khelat Bari, Roll No.:
040406248P, Session: April 2004 has been accepted as satisfactory in partial fulfillment
of the requirement for the degree of MASTER OF SCIENCE IN ELECTRICAL AND
ELECTRONIC ENGINEERING on June 14, 2008.
BOARD OF EXAMINERS
1.
______________________
Dr. A.B.M Harun-Ur-Rashid
Professor
Department of Electrical and Electronic Engineering
BUET, Dhaka—1000, Bangladesh.
Chairman
(Supervisor)
2.
______________________
Dr. Aminul Hoque
Professor and Head
Member (Ex-Officio)
3.
______________________
Dr. Mohammad Ali Choudhury
Professor
Member
4.
______________________
Dr. Md. Ashraful Hoque
Professor
IUT, Gazipur, Bangladesh.
Member
(External)

4
DECLARATION
I hereby declare that this thesis or any part of it has not been submitted elsewhere for the
award of any degree or diploma.
Signature of candidate
__________________
(Syed Mustafa Khelat Bari)

6
Acknowledgement
I am grateful to the Almighty ALLAH for giving me the strength, courage and
potentiality to complete this thesis.
I would like to express my profound and sincere gratitude to my supervisor Prof.
Dr. A.B.M Harun-ur-Rashid, Professor, Department of Electrical and Electronic
Engineering (EEE), Bangladesh University of Engineering and Technology (BUET),
Dhaka, Bangladesh, whose patient guidance and encouraging attitude have motivated me
much to have this thesis materialized. His constant pursuit of new ideas and
uncompromising attention to important details imprinted in my mind a model of a great
mentor to which I will endeavor to come close in coming years.
I would like to thank Prof. Dr. Aminul Hoque, Professor and Head of the
Department of Electrical and Electronic Engineering, BUET, and Prof. Dr. Satya Prasad
Majumder, Professor and Former Head of the Department of Electrical and Electronic
Engineering, BUET for their support through out the period of the thesis work.
I would also like to express my wholehearted gratitude to Mr. Didar Islam, my
employer and founder of the only IC design company in Bangladesh, Power IC Ltd.,
where I work as an IC design Engineer, for his great encouragement, dynamic technical
support with research papers, books, and relevant knowledge and nevertheless with the
models for simulation. I like to thank the members of the design group for their positive
criticism and invaluable support.
I am also grateful to all the members of my family especially to my father and
mother for their cooperation to accomplish this work. I also express my gratefulness to
my wife for her extra-ordinary support and encouragement to complete my work.

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Abstract
A high performance internally compensated Low Drop out (LDO) regulator has been
presented in this thesis which is stable with any value and type of output capacitor.
Normally any type of regulator consisting negative feedback loop requires an output
capacitor to collapse the loop bandwidth so that other internal poles in the loop do not
have much effect in the stability. Again depending on the type, the equivalent series
resistance (ESR) of the capacitor can vary a wide range like 10mΩ to 10Ω which
inherently produces a zero in the system and makes the stability requirements more
complex and challenging. Normally most of the regulators are designed to be stable either
with high ESR or with low ESR but not with both. The novelty of the LDO regulator
proposed in this thesis is its system architecture which makes it stable with ESR value of
the output capacitor as low as 10mΩ to as high as 10Ω which gives the user to choose
any type of capacitor in output and even with the absence of output capacitor itself which
can save the very valuable space in the application board. This LDO regulator is designed
in a pseudo BiCMOS process which includes few more layers like deep N-Well, P-well
layers with the vanilla CMOS process and hence has much lower cost than BiCMOS
process. Along with the output capacitor and ESR independent improved stability, the
other remarkable features of this proposed LDO regulator are ultra low line regulation,
very low drop out voltage, high power supply rejection ration (PSRR), short circuit
current limit, over temperature sensing and thermal shutdown, no shut down leakage
current, under voltage lock out (UVLO) mode, low operating current, ultra low output
voltage drift with temperature, quick start up time and low operating noise etc.
Simulation results are presented in this thesis to support all these claims. The full layout
of this proposed regulator has been implemented in 0.5µm technology and the
implementation issues and challenges with applied methods to overcome those in this
particular layout are also discussed in this thesis.

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Contents
Declaration iii
Dedication iv
Acknowledgement v
Abstract vi
Chapter 1. Introduction 1-7
1.1 Definition of LDO Regulator
1.2 Present Demand of LDO Regulator
1.3 Comparison with Alternative solution
1.4 Thesis Objective
1.5 Organization of the Thesis
1
1
3
5
6
Chapter 2. Linear Low Drop Out Regulator in Brief 8-16
2.1 Background of Voltage Regulators
2.2 Characteristics of LDO Regulator
2.3 Specifications of LDO Regulator
8
11
13
Chapter 3. Proposed Topology for Improved Stability 17-39
3.1 LDO Regulator Stability Analysis
3.2 System Requirements and ESR Issues
3.3 Stability Issues and Design Challenges
3.4 Miller Compensation Techniques
3.5 Proposed Pole Zero Location for Better Stability
17
23
24
27
32
Chapter 4. Process Issues and Implementation 40-55
4.1 Pseudo BiCMOS Process and its Issues
4.2 Amplifier Design and Issues
4.3 Reference Design and Issues
40
43
45

9
4.4 Current Limit Circuit
4.5 Layout Implementation Issues
47
49
Chapter 5. Proposed Enhancement of Performance 56-70
5.1 Noise Improvements & Quick Charge Block
5.2 Load Transient Improvement
5.3 Efficient Pass Transistor
5.4 Shutdown Mode with Ultra Low Ground Current
5.5 Over Temperature Sense and Thermal Shutdown
5.6 Output Voltage Temperature Coefficient Improvement
5.7 Under Voltage Lock Out (UVLO)
5.8 Kelvin Sense Method for Load Regulation Improvement
56
60
63
66
67
68
69
70
Chapter 6. Simulation and Results 71-78
6.1 Necessary Files and Tools
6.2 The Complete Block diagram of the LDO Regulator
6.3 The Start-up in Different Conditions
6.4 Different Modes of Operation
6.5 Load Transient Response
6.6 Current Limit and Short Circuit Protection
6.7 Line Regulation and Line Transient Response
6.8 Performance Summery
71
72
73
74
75
76
77
78
Chapter 7. Future Work 79
Chapter 8. Conclusion 80
Reference

10
Chapter 1
Introduction
1.1 Definition
Now a days LDO has become a very frequently uttered word in analog IC industry which
is a short form of ‘low drop out’. A LDO or low-drop-out series regulator is a voltage
regulator that provides a well regulated and stable dc voltage [1] whose input to output
voltage difference is low [2]. The drop-out voltage is defined as the value of the
input/output differential voltage where the control loop stops regulating. The term series
comes from the fact that a power transistor (pass device) is connected in series between
the input and the output terminals of the regulator [3]. The operation of the circuit is
based on feeding back an amplified error signal to control the output current flow of the
power transistor driving the load. This type of regulator has two inherent characteristics:
(1) the magnitude of the input voltage is greater than the respective output and (2) the
output impedance is low to yield good performance [2]. Low drop-out (LDO) regulators
can be categorized as either low power or high power. Low power LDO regulators are
typically those with a maximum output current of less than 1 A, exhibited by most
portable applications. On the other hand, high power LDO regulators can yield currents
that are equal to or greater than 1 A to the output, which are commonly demanded by
many automotive and industrial applications [4].
1.2 Present Demand of LDO
As a result of high variations in battery voltage, regulators are demanded by virtually all
battery operated applications. Furthermore, most designs find it necessary to include
regulators and other power supply circuits as products achieve or approach total chip
integration. Low dropout regulators are appropriate for many circuit applications,
namely, automotive, portable, industrial, and medical applications. In the automotive
industry, the low dropout voltage is necessary during cold-crank conditions where the
battery voltage can drop below 6 V. The increasing demand, however, is readily apparent

11
in mobile battery operated products, such as cellular phones, pagers, camera recorders,
and laptops [5]. This portable electronics market requires low voltage and low quiescent
current flow for increased battery efficiency and longevity [6]. As a result, high current
efficiency is necessary to maximize battery life. Low voltage operation is also a
consequence of the direction of process technology towards higher packing densities [7].
In particular, isolation barriers decrease as the component densities per unit area are
increased thereby manifesting lower breakdown voltages [8, 9]. Minimization of dropout
voltages in a low voltage environment is also necessary to maximize dynamic range. This
is because the signal-to-noise ratio decreases as the power supply voltages decrease while
noise typically remains constant [10, 11]. Consequently, low power and finer lithography
drive regulators to operate at lower voltages, produce precise output voltages, and require
low quiescent current flow [9]. Lastly, financial considerations also require that these
circuits be fabricated in relatively simple processes, such as standard CMOS, bipolar, and
stripped down BiCMOS technologies [13].
Major applications of LDO regulators are
Battery-powered equipment
Communication equipment
Audio/Video equipment
Wireless communication equipment
Voltage regulator for LAN cards
Portable electronics
Power saving application
Notebook computers
Bluetooth portable radios and accessories
PCMCIA cards
VCOs, RF receivers and ADCs
SMPS post-regulator

12
Fig 1.2: An example of LDO use in Mobile Phone Power Distribution
1.3 Comparison with Alternative solution
The alternatives to low dropout regulators are dc-dc converters, switching regulators.
Switching regulators are essentially mixed-mode circuits that feed back an analog error
signal and digitally gate it to provide bursts of current to the output. The circuit is
inherently more complex and costly than LDO regulator realizations [9]. Furthermore,
switching regulators can provide a wide range of output voltages including values that are
lower or greater than the input voltage depending on the circuit configuration, buck or
boost. The circuit, for the most part, requires a controller with an oscillator, pass
elements, an inductor, capacitors, and diodes. Some switched-capacitor implementations
do not require an inductor [14, 15]. The worst-case response time of a dc-dc converter is

13
dependent on the oscillating frequency of the controller (approximately 20 to 200 kHz
[16]) and circuit delay. As a result, the corresponding response time is roughly between 6
and 8 µs, whereas the LDO regulator typically requires between 1 and 2 µs [12]. Since
the pass elements switch high currents through an inductor at the rate of the oscillator, the
output voltage is inherently noisy. This is especially true for boost configurations where
RF noise tends to be worse [17]. The high noise present is a consequence of the rectified
inductor voltage behavior of the output of these converters. Furthermore, start-stop clock
operation (on/off sleep-mode transitions) further aggravates the noise content of the
output voltage [12]. On the other hand, switching regulators benefit from having high
power efficiency and the ability to generate larger output voltages than the input. They
can yield efficiencies between 80 and 95 % [18]. The efficiency of the LDO regulator
counterpart is limited by the quiescent current flow and the input/output voltages, and is
expressed as
  Vi
Vo
ViIqIo
VoIo
Efficiency Power 


. (1.1)
where Io and Vo correspond to the output current and voltage, Vi is the input voltage, and
Iq is the quiescent current or ground current. The main power issue in LDO regulator
design is battery life, in other words, the output current flow of the battery. When the
load-current is low, which is the normal operating mode for many applications; the
quiescent (ground) current becomes an intrinsic factor in determining the lifetime of the
battery. Consequently, current efficiency is important during low load-current conditions.
Power efficiency, on the other hand, becomes more pertinent during high load-current
conditions where quiescent current is negligible relative to the output current. If the
maximum load-current is much greater than the ground current, then the maximum
possible power efficiency is defined by the ratio of the output and the input voltages, as
seen in equation (1.1). Power efficiency increases as the voltage difference between the
input and the output decreases. Under these conditions, LDO regulators are better suited
for many applications than switching regulators because of lower cost, complexity, and
output noise. The choice becomes obscure, however, if the output current increases to the

14
point where the LDO regulator requires a heat sink [12]. A heat sink not only increases
cost by requiring an additional component but it also means more real estate area
overhead on the board, which further increases cost. Applications that require high
input/output voltage differentials with high output currents greatly benefit from the
efficiency of dc-dc converters. Nevertheless, there are some cases where a high
input/output voltage differential regulator is required to drive noise sensitive circuits. In
these situations, a switching regulator is used to bring down the voltage and an LDO
regulator is cascaded to provide a low noise output [4, 18]. These conditions arise in
mixed-mode designs where circuits that perform analog functions tend to be more
sensitive to noise originated in the supply rails than the digital counterparts [17, 19].
Other applications require output voltages that are larger than the respective inputs. In
these situations, dc-dc converters are necessarily used, in the form of a boost topology, a
boosting switch capacitor implementation, or a charge pump structure. However, LDO
regulators are still required in these applications to suppress noise generated by the
switching pre-regulator. In summary, both LDO regulators and switching regulators have
their place in today's market demand.
1.4 Thesis Objective
The objective of this thesis is to design an improved high performance LDO regulator
with a compensation network for voltage mode negative feedback loop with high gain
bandwidth and stable with a very large equivalent series resistance (ESR) range.
Normally most of the regulators need an output capacitor to limit its bandwidth which
bounds the user to use a minimum required size capacitor for stable operation. Depending
on the type of the capacitor ESR varies in a large range. Usually most regulators are
designed to work either with low ESR capacitor or with capacitor with higher ESR value
but not with both. In this thesis we will analyze the issues that are created to tolerate a
large ESR range of output capacitor and find their possible solutions. In fact, the target is
to make the proposed LDO regulator as much output capacitor type and value
independent as possible and hence make the regulator stability more robust. Along with
the improved stability, improvements of the performances of the proposed LDO regulator

15
are also brought into the focus of this thesis. Another objective of this thesis is to show
the step by step implementation of the proposed LDO regulator in a pseudo BiCMOS
process. This process is much cheaper than a true BiCMOS process in the sense that it
has less number of layers and masks than that of true BiCMOS process. Pseudo BiCMOS
process is basically a CMOS process where 2/3 extra layers are added to create NPN
transistor with a reasonable gain and bandwidth. We will also do the layout of our
proposed LDO regulator in 0.5μm technology. In that regard we will show the issues and
the challenges of this regulator layout and the techniques to overcome those challenges.
The outcome of this thesis is a high gain bandwidth linear low dropout voltage regulator
with internally compensated loop to make its stability output capacitor and its ESR
independent, designed and implemented in a comparatively low cost process.
1.5 Organization of the Thesis
In the chapter 1 we have given the basic fundamental definition of the LDO regulator.
Then we discussed demand of this electronic circuit in the electronics IC industry and we
also include some of its major applications. We also have shown a comparative analysis
of the characteristics of LDO regulator with its competitor.
In the chapter 2 we tried to introduce the characteristics of the LDO regulator briefly. We
discussed about the characteristics of the LDO regulator which includes the basic
functional blocks of the regulator and their working principles. Then we define the
performances of different parameters of the regulator by which it is evaluated.
In the chapter 3 we have tried to define the architecture of the proposed LDO regulator
system to solve the stability issues predominantly including other performance
consideration. At first we discuss the conventional regulator structure with gain amplifier,
pass element and output capacitor in stability point of view. Then we introduce the ESR
of output capacitor and stability complexity regarding the introduction of its zero into the
system. We propose to use Miller compensation technique to solve these complex
stability issues and discuss briefly about the fundamental of this technique. Lastly we

16
have shown the detail analysis of the application of the compensation technique on our
system and the simulation results to prove the claims.
In the chapter 4 implementation of our proposed architecture of the LDO regulator has
been discussed. Firstly we discussed about gain amplifier with Miller compensation
which includes the structure, gain and how we control the variation of gain with process
and temperature. Then we mentioned the basic protection circuit, i.e. short circuit current
limit circuit. At the end of this chapter we talked about the special issues and challenges
of the analog layout and how they are taken care of in this regulator layout.
In the chapter 5 we mentioned the performances of a LDO regulator which we have
implemented in this thesis. We discussed here the improvement of noise level of the
regulator, load transient performance, increase the efficiency in shutdown mode by
minimizing its ground current in nano ampere level in that mode. We also mentioned the
features we have added in this regulator to enhance its performance like thermal
shutdown feature, under voltage lockout (UVLO) feature, exclusion of bond wire drop by
using Kelvin sense to improve load regulation.
In the chapter 6 we have shown the functionality of the regulator with the simulation
results. We discussed here about the tools we have used, we have shown the full block
diagram of the regulator. Then describe the start up methods of the regulator along with
sequencing of different blocks. Then we discussed about the different working modes of
the regulator briefly along with simulation results to show them. Then we show the
simulation results of load transient and load regulation, short circuit current limit
protection simulation result, and line transient and regulation performance in brief.
In the chapter 7 we gave the conclusion describing our achievements in this thesis.
In the chapter 8 we discussed about the future possible scope of analysis on this topic.

Chapter 2
Linear Low Drop Out Regulator in Brief
2.1 Background of Voltage Regulators
A voltage regulator is an electronic regulator designed to automatically maintain a
constant voltage level. It may use an electromechanical mechanism, or passive or active
electronic components. Depending on the design, it may be used to regulate one or more
AC or DC voltages. With the exception of shunt regulators, all modern electronic voltage
regulators operate by comparing the actual output voltage to some internal fixed
reference voltage. Any difference is amplified and used to control the regulation element.
This forms a negative feedback servo control loop. If the output voltage is too low, the
regulation element is commanded to produce a higher voltage. For some regulators if the
output voltage is too high, the regulation element is commanded to produce a lower
voltage; however, many just stop sourcing current and depend on the current draw of
whatever it is driving to pull the voltage back down. In this way, the output voltage is
held roughly constant. The control loop must be carefully designed to produce the desired
tradeoff between stability and speed of response.
In general, these can be divided into several classes:
 Linear regulators
 Switching regulators
 SCR regulators
Linear regulators
Linear regulators are based on devices that operate in their linear region (in contrast, a
switching regulator is based on a device forced to act as an on/off switch). In the past,
one or more vacuum tubes were commonly used as the variable resistance. Modern
designs use one or more transistors instead. Linear designs have the advantage of very

Chapter 1 – Linear Low Drop Out Regulator in Brief
18
"clean" output with little noise introduced into their DC output, but are less efficient and
unable to step-up or invert the input voltage like switched supplies.
Entire linear regulators are available as integrated circuits. These chips come in either
fixed or adjustable voltage types.
Switching regulators
Switching regulators rapidly switch a series device on and off. The duty cycle of the
switch sets how much charge is transferred to the load. This is controlled by a similar
feedback mechanism as in a linear regulator. Because the series element is either fully
conducting, or switched off, it dissipates almost no power; this is what gives the
switching design its efficiency. Switching regulators are also able to generate output
voltages which are higher than the input, or of opposite polarity — something not
possible with a linear design.
Like linear regulators, nearly-complete switching regulators are also available as
integrated circuits. Unlike linear regulators, these usually require one external
component: an inductor that acts as the energy storage element. (Large-valued inductors
tend to be physically large relative to almost all other kinds of component, so they are
rarely fabricated within integrated circuits and IC regulators — with some exceptions.)
SCR regulators
Regulators powered from AC power circuits can use silicon controlled rectifiers (SCRs)
as the series device. Whenever the output voltage is below the desired value, the SCR is
triggered, allowing electricity to flow into the load until the AC mains voltage passes
through zero (ending the half cycle). SCR regulators have the advantages of being both
very efficient and very simple, but because they can not terminate an on-going half cycle
of conduction, they are not capable of very accurate voltage regulation in response to
rapidly-changing loads.

19
A low dropout or LDO regulator is a DC linear voltage regulator which has a very small
input-output differential voltage. The main components are a power FET and a
differential amplifier (error amplifier). One input of the differential amplifier monitors a
percentage of the output, as determined by the resistor ratio of R1 and R2. The second
input to the differential amplifier is from a stable voltage reference (bandgap reference).
If the output voltage rises too high relative to the reference voltage, the drive to the power
FET changes so as to maintain a constant output voltage.
The adjustable low dropout regulator debuted on April 12, 1977 in an Electronic Design
article entitled "Break Loose from Fixed IC Regulators". The article was written by
Robert Dobkin, an IC designer then working for National Semiconductor. Because of
this, National Semiconductor claims the title of "LDO inventor" Dobkin later left
National in 1981 to found Linear Technology where he is currently chief technology
officer.
Fig 2.1: Typical LDO system diagram

20
2.2 Characteristics of LDO Regulator
Block Level Description
Fig 2.2: Generic low dropout series linear regulator architecture.
Fig 2.2 illustrates the block level diagram of a generic series low dropout regulator. The
circuit is composed of a reference and associated start-up circuit, protection circuit and
associated current sense element, an error amplifier, a pass element, and a feedback
network. The reference provides a stable dc bias voltage with limited current driving
capabilities. This is usually a zener diode or a bandgap reference. The zener diode finds
its applications in high voltage circuits (greater than approximately seven volts) with
relaxed temperature variation requirements [1, 3]. The bandgap, on the other hand, is
better suited for low voltage and high accuracy applications. The protection circuitry
ensures that the LDO operates in safe stable conditions. Some of its functions include
over-current protection (typically a foldback current limiter [6]), thermal shutdown in
case of self-heating (junction temperature increases beyond safety levels), and other
similar functions. The error amplifier, the pass element, and the feedback network
constitute the regulation loop. The temperature dependence of the reference and the
amplifier's input offset voltage define the overall temperature coefficient of the regulator;
hence, low drift references and low input offset voltage amplifiers are preferred [20, 21].

21
Regulator Performance
Overall noise performance is strongly dependent on the physical layout of the chip and
the respective process technology. In particular, the noise present at the output of the
LDO is composed of three components, namely, noise injected from the system through
the substrate and the input voltage, noise generated by the reference circuit, and noise
associated with the output trace (lead) inductance and resistance [4]. Switching regulators
can typically be used to provide power to LDO regulators and can be integrated in the
same chip as the LDO thereby injecting noise through the substrate and the input voltage,
i.e., cellular phones. In these cases, physical layout isolation techniques and high power
supply rejection ratio are intrinsic circuit characteristics for good noise performance.
Transient load-current changes also affect the noise content seen by the load. This results
from the parasitic resistance and inductance of the trace (lead) from the LDO regulator’s
output to the load. Therefore, physical proximity of the LDO to its load must be
minimized to reduce the noise seen by the load [12]. Low dropout regulators tend to
necessitate large output capacitors that occupy large board areas. Furthermore, typical
LDO regulators require that these capacitors have low electrical series resistance (ESR).
Consequently, capacitors play an intrinsic role in the cost of the LDO. High power LDO
regulators may require heat sinks further aggravating the cost issue. However, a system
level design choice may circumvent the need for a heat sink by utilizing several smaller
LDO regulators distributed throughout the board [4]. Finally, the emergence of finer
lithography and the increasing demand for low power cause low voltage operation to be a
necessary condition. Therefore, there are some circuit design techniques that are
discouraged, which give rise to more complex and possibly more expensive circuits.
Some of the discouraged techniques include unnecessary cascoding, emitter followers,
and Darlington configurations [10].

22
2.3 Specifications of LDO Regulator
System Specifications
The important aspects of the LDO can be summarized into three categories, namely,
regulating performance, quiescent current flow, and operating voltages [19]. Some of the
specifications that serve as metrics for the LDO include dropout voltage, line regulation,
load regulation, tolerance over temperature, output voltage variation resulting from
transient load-current steps, output capacitor and ESR range, quiescent current flow,
maximum load-current, and input/output voltage range. The requirements of these
performance characteristics often contradict each other giving rise to necessary
compromises. The priority of the performance parameters is defined according to the
particular application. Dropout voltage is the minimum input/output differential voltage
where the circuit just ceases to regulate. This can be expressed in terms of switch "on"
resistance, Ron [6],
onloaddropout RIV  (2.1)
Typical dropout voltages range from 0.1 to 1.5 V [4]. The output voltage variation arising
from a specific change in input voltage is defined as line regulation. Similarly, load
regulation is the change in output voltage for specific changes in load-current [2].
Load regulation is essentially the output resistance of the regulator (Ro-reg),
1o
passo
O
LDR
rego
A1
R
I
V
R







(2.2)
where ∆VLDR and ∆Io are the output voltage and the load-current changes, Ro-pass is the
output resistance of the pass element, Aol is the open-loop gain of the system, and β is the
feedback factor [3]. Therefore, load regulation performance is improved as the dc open
loop gain is increased [12]. The temperature dependence of the output voltage is a

23
function of the temperature drift of the reference and that of the input offset voltage of the
error amplifier,
Tempo
ref
o
TCTC
TC
o
o
o VV
V
V
VV
Temp
Vo
VTemp
V
V
TC
Vosref









 ][
.
1
.
1 (2.3)
where TC is the temperature coefficient, ∆VoTC is the output voltage variation over the
temperature range ∆Temp, ∆VTCref and ∆VTCVos are the voltage variations of the
reference and input offset voltage of the error amplifier, and Vo / Vref is the ratio of the
nominal output and reference voltages. Transient output voltage variations resulting from
sudden load-current changes are dominated by the closed-loop bandwidth of the system,
output capacitor, and load-current. The worst-case situation occurs when the load-current
suddenly steps from zero to its maximum specified value. The resulting output voltage
variation is described as
esr
bo
Load
tr Vt
CC
I
V 

 max
(2.4)
where ∆Vtr is the output voltage change, ILoad-max is the maximum specified load
current, Co is the output capacitor, Cb refers to the bypass capacitors, ∆Vesr is the voltage
variation resulting from the electrical series resistance (ESR) of the output capacitor, and
∆t is the time required for the LDO to respond (approximately equal to the reciprocal of
the closed-loop bandwidth (BWcl) if internal slew-rate conditions are neglected). The
voltage variation resulting from ESR results because of the momentary current (provided
by Co) flowing through the ESR. This is reduced by the high frequency nature of the
bypass capacitors (low ESR capacitors). In other words, the bypass capacitors (Cb) help
filter out the effects of the output capacitor ESR. Consequently, fast response times and
low ESR values are necessary to yield low transient output voltage variations.
Low output voltage variations are desired to meet the overall accuracy requirements of
the system, i.e., 150 - 300 mV [9]. Thus, the circuit as a whole benefits from the use of a
high bandwidth amplifier in the feedback loop. A pivotal specification is the output

24
capacitor and associated ESR range for which the LDO is stable. This can typically prove
to be a difficult task if a wide range of values is to be allowed. The value of the load-
current also affects the frequency response of the circuit. Lastly, long term stability and
low external component count are also pertinent factors to keep in mind when designing
LDO regulators. The effects of line regulation, load regulation, temperature dependence,
and transient output voltage variations can be summed up into one specification,
accuracy. Accuracy refers to the total output voltage variation and can be described by
the absolute minimum and maximum output voltages (Vo-min and Vo-max), shown in the
following equations:
maxmin   o
ref
o
referencetrTCLDRLNRo V
V
V
VVVVVV
(2.5)
OSLNRrefTCrefrefreference VVVVV 
(2.6)
o
oo
system
V
VV
Accuracy minmax  

(2.7)
where ∆VLNR, ∆VLDR, ∆VTC, ∆Vtr, ∆VTCref, and ∆VLNRref are voltage variations
resulting from line regulation, load regulation, temperature dependence, worst-case
transient load-current steps, reference circuit's temperature dependence, and reference
circuit's line regulation respectively while Vos and Vo are the input offset voltage of the
error amplifier and the nominal output voltage of the regulator. In specifying accuracy,
the effect of the transient load-current step and the reference circuit is sometimes
excluded but they are included here for completeness. Low voltage operation often
implies more stringent specifications in the form of overall accuracy. Typical
implementations achieve roughly 1 to 2 % total variation resulting from load regulation,
line regulation, and temperature dependence while leaving some headroom for transient
output voltage variations [12].

25
Reference Specifications
The specifications of the reference include line regulation, temperature dependence,
quiescent current flow, and input voltage range. The effects of line regulation and
temperature drift on system accuracy are shown in equations (2.5) - (2.7). Line regulation
of reference refers to the variation of the reference voltage arising from a unit change in
input voltage. In the same token, the temperature coefficient of the reference (TCref)
refers to the variation in output voltage of the reference as a result of unit changes in
temperature and can be expressed as
Temp
V
V
1
Temp
V
V
1
TC
TCref
ref
ref
ref
ref





 ..
(2.8)
where ∆VTCref is the reference voltage change resulting from a temperature variation
equal to ∆Temp and Vref is the nominal reference voltage. The overall accuracy of
references is determined by the combination of line regulation and temperature
coefficient performance and is described
ref
LNRrefTCref
reference
V
VV
Accuracy



(2.9)
where ∆VTCref and ∆VLNRref are voltage variations resulting from temperature
dependence and line regulation respectively. Load regulation is sometimes included in
the accuracy of the reference but most appropriately specified for regulator structures.

Chapter 3
Proposed Topology for Improved Stability
3.1 LDO Regulator Stability Analysis
The most challenging aspect of the LDO regulator design is to ensure its stability in
different conditions.
Fig 3.1: System model under loading condition
Fig 3.1 illustrates the factors that determine the stability of the system, namely, an error
amplifier, a pass element, feedback resistors, an output load current and associated output
impedance, an output capacitor and associated electrical series resistance (ESR), and
bypass capacitors. It is assumed that there is no ac signal polarity inversion across the
pass device, corresponding to n-type transistor implementations. The polarity of the error
amplifier terminals would be reversed for p type devices, which introduce a polarity
inversion (-gmp instead of gmp). The ESR of the bypass capacitors can typically be
neglected because they are usually high frequency capacitors; in other words, they have
Vin
A
R2
gma
gmp
RL
Resr
R1
Cb
Cout
Vref
Cpar

Chapter 2 - Proposed Topology for Improved Stability
27
low ESR values [20]. The pass device is modeled as a circuit element exhibiting a
transconductance of gmp and an output impedance of Ropass. The value of R2 is
dependent on the desired value of the output voltage, i.e., R2 is zero if Vout is desired to
be equal to Vref. The value of R1, on the other hand, is designed to define the quiescent
current flowing through resistors R1 and R2 (R1 = Vref / IR1), which is typically high to
minimize quiescent current loss.
Frequency Response
For the purpose of analysis, the feedback loop can be broken at "A" in Fig 3.1. It is
readily apparent that the system must be unity gain stable, considering Vref and Vfb to be
the input and the output voltages respectively. The open-loop gain can be described as
  ]21[
1
.
1 RR
R
CsR
ZgRg
Av
Vref
Vfb
paroa
mpoama


(3.1)
where gma and gmp refer to the transconductance of the amplifier and the pass element
respectively, Roa is the output resistance of the amplifier, Cpar refers to the parasitic
capacitance introduced by the pass element, and Z is the impedance seen at Vout,
 
  1CsRCRRsCCRRs
CsR1R
Z
sC
1
sC
CsR1
RZ
bxoesrxboesrx
2
oesrx
bo
oesr
x




 ////
(3.2)
where Co and Resr are the capacitance and the ESR of the output capacitor, Cb represents
the bypass capacitors, and Rx is the resistance seen from Vout back into the regulator
defined as
L21passox RRRRR //)//(   (3.3)

28
where Ro-pass is the output resistance of the pass element. RL is the load resistance in case
of the resistive load. If Co is assumed to be reasonably larger than Cb (typical condition),
then Z approximates to
])//(1].[)(1[
]1[
besrxoesrx
oesrx
CRRsCRRs
CsRR
Z



(3.4)
It can be observed from equations (3.1) - (3.4) that the overall transfer function of the
system consists of three poles and one zero, a potentially unstable system. For the
majority of the load-current range, Rx simplifies to RL since R1 + R2 is greater in
magnitude (especially at load condition). The poles and the zero can thus be
approximated to be the following:
oL
1
CR2
1
P
.

(3.5)
besr
2
CR2
1
P
.

(3.6)
paroa
3
CR2
1
P
.

(3.7)
oesr
1
CR2
1
Z
.

(3.8)
For the simplicity of the stability analysis of our proposed LDO regulator which we are
going to discuss in this section lets consider few parameters. First of all, lets take the
output voltage of the regulator is 3.3V which is decided by the feedback network R1, R2
and Vref, and the output capacitor, Cout=1uF for the system. Now the load condition of
the regulator may vary from No load to full load which is 300mA. In fact in the no load
condition there will be some current at output which will be set by the feedback
resistance network. If we consider the feedback voltage 1V and the feedback resistance is

29
100k then 1V/100k=10uA will be the minimum current at the output which we will call
no load current. So in the no load condition the equivalent output impedance RoutNL will
be
K330
uA10
33
RoutNL 
. (3.9)
Hz50
CR2
1
P
outoutNL
laodNL .
.


(3.10)
In the full load condition the equivalent output impedance RoutFL will be
 11
mA300
33
RoutFL
. (3.11)
KHz15
CR2
1
P
outoutFL
laodFL 
.
(3.12)
Fig 3.2: System model for our proposed LDO regulator for stability analysis
A
RF
2
gm
Pass
Transistor
RL
Resr
RF
1
Cb
Cout
Vref
Pass
drive
Vin
CgRg
Rdrv
Cdrv

30
The next major pole of the system is decided by the pass transistor gate parasitic
capacitance, Cpar. Gate capacitance will be dependant on the size of the pass transistor
which will be decided by dropout performance and Max load capacity of the LDO
regulator. To minimize the dropout and maximize the load capacity the pass transistor
needs to be as big as possible. But the constraints for making the pass transistor size big
are manifold. One of the main constraints is layout area for pass transistor and the pass
transistor gate capacitance. Bigger the pass transistor size bigger will be the gate
capacitance which will create a big pole in the system and also cause slew rate problem.
We chose the pass transistor for 300mA load and low dropout such a way so that it’s on
resistance, Ron = 0.5 Ohm. So the dropout for 300mA load will be 150mV. For 0.5µm
process the gate capacitor for the SW will be approx 100pF. If the gate is driven by push
–pull driver which has a low output impedance contribute a resistance for the pole. If we
take this resistance 30k approx. the gate pole will be –
drvdrv
drv
CR2
1
P
.
 (3.13)
KHz
pFk
Pdrv 300
100.30.2
1


(3.14)
There will be a third pole of the system which will be created by the gain amplifier output
impedance, Rg and the capacitance Cg The capacitance Cg will be the combination of
gain amplifier output capacitance and driver stage input capacitance. Lets assume that the
Rg ≈300K and the Cg ≈1pF. So the third pole Pg will be –
gg
g
CR2
1
P
.
 (3.15)
KHz
pFk
Pg 300
1.300.2
1


(3.16)

31
Now these are the three major poles of the system. We know from the Nyquist Stability
[21] criterion that phase shift has to be lees than 180 degree within the bandwidth region.
We also know that each pole contributes 90 degree of phase margin. So these three pole
system will be unstable unless any zero is added or compensation network is used. For a
high gain system like ours these poles position makes the system very difficult to become
stable.
Fig 3.3: AC simulation results of the uncompensated LDO regulator system
model with three major poles
We can see from the Fig 3.3 that gain is chosen 40dB and load pole is in approx 15 KHz.
We see that the gain amplifier pole, Pgm is in approx 200 KHz and driver stage pole,
Pdrv is in approx 300 KHz. The net result is clearly visible here is that when the gain is 0
dB on the left scale then the phase is -40 degree on the right scale which means the
system is unstable.
Unity Gain Point
Gain Bandwidth ≈ 800KHz
Phase Margin ≈ -40 deg
PLoad
Pdrv
Pgm

32
3.2 System Requirement and ESR Issues
ESR is an abbreviation for Equivalent Series Resistance [22], the characteristic
representing the sum of resistive (ohmic) losses within a capacitor. While ESR is
undesirable, all capacitors exhibit ESR to some degree. Materials and construction
techniques used to produce the capacitor all contribute to the component’s ESR value.
ESR is a frequency dependent characteristic, so comparison between component types
should be referenced to the same frequency [23]. Industry standard reference for ESR is
100 KHz, +25°C. ESR is an important characteristic, as the power dissipation (watts)
within the capacitor, and the effectiveness of the capacitor’s noise suppression
characteristics, will be related directly to the ESR value.
Fig 3.4: In effect, all of the ESR components add to equal one
resistor placed in series with the ideal capacitor
Now, the load resistance Rload, equivalent series resistance (ESR) Resr, and the output
capacitor Co combination will create one pole which is the load pole Pload and one zero
Zload in the system [35]. The equation of this pole-zero pair will be

33
  oesrload
load
CRR2
1
P



(3.17 )
oesr
load
CR2
1
Z



(3.18)
Now depending on the system LDO regulator is putting in different PCB may have
different kind of capacitor. We know different kind of capacitor has different ESR. So the
ESR zero will move accordingly when the pole will not move much as the load resistance
is most of the cases considerably larger that the ESR value. There are lots of capacitor
types in the market, namely Electrolyte, Tantalum or ceramic. Now the surface mount
(SMT) capacitors are very popular for their low ESR value. Depending on the type of the
capacitor, ESR value can be approximately from 10mΩ to 10Ω.
There are some more ways a series resistance can be added with the output capacitor.
One of the major sources can be the PCB layout. If the distance between capacitor and
the regulator output pin is high, that will surely add ESR to the system.
Another very important place where ESR issue is very important is wafer testing. In
wafer testing normally basic parameters of the regulator are being tested. In that time
long wires are connected to the die PADs through needles in the probe station. As the
output capacitor is put in the Probe Card, so the long wire resistance along with contact
resistance and the needle resistance are added to the ESR of the output capacitor. ESR is
also a issue in final test (FT) when the packaged part is put in the socket. Then the output
capacitor is soldered in the test board where the socket is connected through the wire. So
the wire resistance along with board metal trace resistance is added to the ESR of the
capacitor.

34
3.3 Stability Issues and Design Challenges
Worst-case Stability
The worst-case stability condition, given the set of elements shown in Fig 3.1, arises
when the phase margin is at its lowest point, which occurs when the unity gain frequency
is pushed out to higher frequencies where the parasitic poles reside. This happens when
the load-current is at its peak value [20]. This is because the dominant pole (P1) usually
increases at a faster rate (Ro-pass decreases linearly with increasing current, 1/λIo or Va/Io
where λ is the channel length modulation parameter of MOS devices and Va is the early
voltage of bipolar transistors) than the gain of the system decreases (gmpRo-pass decreases
with the square root of the increasing current for an MOS device or stays constant for a
bipolar transistor). The type and value of the output capacitor determine the location of
P1, P2, and Z1 according to the equation (3.5), (3.6), and (3.8). Therefore, the permissible
range of values of ESR for a stable circuit is a function of load-current and circuit
characteristics [5]. Simulations confirm the aforementioned tendencies.
Parasitic Pole Requirements
The parasitic poles of the system can be identified as P3 in equation (3.7) and the internal
poles of the error amplifier. These poles are required to be at high frequencies, at least
greater than the unity gain frequency (UGF). The phase margin for the case where only
one parasitic pole was at the vicinity of the UGF is approximately 45°.Ensuring that P3 is
at high frequencies is an especially difficult task to undertake in a low current
environment. The pole is defined by the large parasitic capacitance (Cpar) resulting from
a large pass device (necessary trait for reasonable output current capabilities) and the
output resistance of the amplifier (Roa). The amplifier's output impedance is usually a
function of the circuit topology and the bias current of its output stage. As a result, low
quiescent current and frequency design issues have conflicting requirements that
necessitate compromises.

35
Maximum Load Regulation Performance
Load regulation performance (output resistance of the regulator, Ro) is a function of the
open-loop gain (Aol) of the system and can be expressed as
11 o
passoLDR
A
R
Io
V
Ro






(3.19)
where ∆VLDR is the output voltage variation arising from a load-current variation of ∆Io,
Ro-pass is the output resistance of the pass device, and β is the feedback factor.
Consequently, the regulator yields better load regulation performance as the open-loop
gain increases [12]. However, the gain is limited by the closed-loop bandwidth of the
system, equivalent to the open-loop unity gain frequency (UGF). The minimum UGF is
bounded by the response time required by the system during transient load-current
variations, as discussed in the specifications section of chapter 2. Furthermore, the UGF
is also bounded at the high frequency range by the parasitic poles of the system, i.e.,
internal poles of the amplifier and pole P3. If these parasitic poles are assumed to be
located at higher frequencies than 1 MHz, then the gain at 1.0 kHz has to be less than
approximately 35 - 45 dB depending on the location of Z1 and P2. In particular, the
worst-case condition occurs when Z1 is at low frequencies and P2 is at high frequencies,
which corresponds to the maximum value of ESR and the lowest bypass capacitance
(Cb). Moreover, the pass element's associated input capacitance (error amplifier's load
capacitance) is significantly large. This places a ceiling on the value of the amplifier's
output resistance (Roa). The pass element typically needs to be a large device to yield low
dropout voltages and high output current characteristics with limited voltage drive in a
low voltage and low power environment. Overall, load regulation is limited by the
constrained open-loop gain of the system.

36
3.4 Miller Compensation Technique
In 1919 John M. Miller was physicist with the National Bureau of Standards when he
wrote a paper on how the grid capacitance of a vacuum tube was so much larger in use
than measured statically [25]. The voltage gain, he said, multiplies the capacitance
between grid and plate. What he described has been known as the Miller effect or the
Miller capacitance ever since.
In electronics, the Miller effect accounts for an increase in the equivalent input
capacitance of an inverting voltage amplifier due to amplification of capacitance between
the input and output terminals. Although Miller effect normally refers to capacitance, any
impedance connected between the input and another node exhibiting high gain can
modify the amplifier input impedance via the Miller effect.
Fig 3.5: Miller Effect
This increase in input capacitance is given by
CM = C (1- AV) (3.20)
where CM is the Miller Capacitance, Av is the gain of the amplifier and C is the feedback
capacitance.

37
Miller went on to doing research at Atwater Kent, RCA and the Naval Research
Laboratory. In 1953 he was awarded the IRE Medal of Honor. The exact same effect was
found in both the bipolar and MOS transistor. In most applications it is detrimental,
limiting the frequency response; in IC op-amps, however, it has been helpful, greatly
decreasing the size of the compensation capacitance [26][27].
Fig 3.6: Op amp with various parasitic and circuit capacitance along with compensating Miller
capacitance
In the Fig 3.6 a conventional two stage op amp circuit is given with its all capacitances.
Normally two stage op amp is used to achieve high gain and in the frequency domain,
each stage contributes a pole which will make the system as a two pole system which is
difficult to stabilize [28].
Fig 3.7: small-signal equivalent circuit for a two stage op amp with Miller capacitance

38
Fig 3.8: Simplified small-signal equivalent circuit
Analysis
The overall transfer function that results from the two stage op amp small signal model
with Miller capacitance is
)]C(CCC[CRRs]CRRgm)C(CR)C(Cs[R1
)/gmsC-(1RRgmgm
Vin(s)
Vo(s)
L1cL1III
2
cIIIIIcLIIc1I
IIcIIIIII


… (3.21)
where
gmI = gm1 = gm2 , gmII = gm6 ,
RI =1/(gds2+gds4) , and RII =1/(gds6+gds7).
By simplifying the above equation we will get the following two widely spaced
compensated poles.
cIIIII
1
CRRgm
p

 (3.22)
and
L
IIcII
C
gmCgm 




c1cLL1
2
CCCCCC
p (3.23)
Where as poles in the uncompensated system were
II
1
CR
'p

 (3.24)
and
IIII
2
CR
'p

 (3.25)

39
It is of interest to note that a zero occurs in the right-half-plane due to the feed forward
path through Cc. The right-half-plane zero is located at
c
1
C
z IIgm
 (3.26)
Fig 3.9: Pole spitting in the Bode plot achieved by Miller compensation
Compensation technique used to eliminate or relocate the RHP zero
As we all know the right-half-plane (RHP) zero increases the phase shift (acts like a left-
half-plane (LHP) pole) but increases the magnitude (acts like a LHP zero). Consequently
the RHP zero causes the two worst things possible with regard to stability considerations.
There are several ways of eliminating the effect of this zero. We are discussing the
approach of putting a nulling resistor in series with compensation capacitor Cc.

40
Fig 3.10: Op amp with various parasitic and circuit capacitance along with compensating Miller
capacitance and nulling resistor in series
Fig 3.11: Small-signal model of the RHP zero elimination circuit
The circuit has following node-voltage equations
0))(
1
( 0111
1
1
1 

 VV
RsC
sC
VsC
R
V
Vgm
zc
c
in (3.27)
0))(
1
( 1002
2
0
12 

 VV
RsC
sC
VsC
R
V
Vgm
zc
c
(3.28)
These equations can be solved to give
32
cz2c
dscsbs1
]}CR-)/gms[(C-a{1
Vin(s)
Vo(s)

 (3.29)

41
where
a gm1gm2R1R2
b (C2 Cc)R2 (C1Cc)R1 gm2R1R2Cc RzCc
c [RIRII(CICII CcCI CcCII) RzCc(RICI RIICII)]
d RIRIIRzCICIICc
If Rz is assumed to be less than RI or RII and the poles widely spaced, then the roots are
cIIIIIcIIIII CRRgmCRRgm
P
1
)(1
1-
1




(3.30)
II
II
IIcIcIII C
gm
CCCCCC
P



 cII
2
Cgm-
(3.31)
IzCR
P
1-
3  (3.32)
and
)/1(
1
1
zIIc RgmC
Z

 (3.33)
The resistor Rz allows independent control over the placement of the zero. In order to
remove the right-half-plane zero, Rz must be set equal to 1/gmII. Another option is to
move the zero from the RHP to the LHP, and place it on the top of P2.
3.5 Proposed Pole Zero Location for Better Stability
We have previously seen that there are three poles in the system so far. We have also
seen that the output capacitor may have series ESR which can introduce a zero in the
system. The position of the ESR zero will be decided by the value of output capacitor and
the value of ESR. Now for 1uF output capacitor, the position of ESR zero will differ
according to the ESR value of the capacitor.
For ESR value 1 Ω, according to the equation (3.10)
KHz
F
Zesr 150
1.1.2
1
min 

(3.34)

42
and For ESR value 10 mΩ, according to the equation (3.10)
MHz
Fm
Zesr 15
1.10.2
1
min 



(3.35)
Fig 3.12: AC simulation result of uncompensated system with 1 OHM ESR with output capacitor
It is clearly visible from the simulation result in Fig 3.12 that when Z1 is in the range of
150K for higher value of ESR then the system stability is improved. We can see that at
the unity gain point the phase is -10 degree which was previously -40 degree. But
definitely the system is still unstable as phase shift is mort than 180 degree. Actually we
can see that bandwidth is still very high which is almost 2 MHz. We have to decrease the
bandwidth to achieve more stability in this condition.
PLoad
Pdrv
Zesr
Pgm
Unity Gain Point
Gain Bandwidth ≈ 2MHz
Gain
Phase

43
Fig 3.13: AC simulation result of uncompensated system with 10mΩ ESR with output capacitor
Now SMT good capacitor is used in the PCB then ESR zero Z1 will be in MHz region. In
that case both the pole P1 and P2 will dominate and phase margin will be really bad.
Applying the Miller compensation Technique
So far we have seen that the system is not stable with its three major poles not even with
the help of ESR zero. First of all we already have seen that we got the help of big ESR
zero which definitely helped the phase improvement while the low ESR value did a little.
But it was not enough as the bandwidth was still large. So we have to reduce the
bandwidth by pulling the dominant pole to more close to origin. Now the dominant pole
is the load pole which exists in 50 KHz at its full load condition. If we want to get this
PLoad
Pdrv
Zesr
Pgm
Unity Gain Point
Gain Bandwidth ≈ 2MHz
Gain
Phase

44
pole more close to origin then we either have to increase the output capacitance or we
have to decrease the full load capacity. Both of them will enervate the performance of the
regulator and hence not very much preferable.
To solve this problem we propose to use the miller compensation technique. We have
seen in the previous section that miller compensation serves the stability by splitting the
poles where dominant pole comes closer to the origin and other one moves out farther.
Fig 3.14: Application of the Miller compensation technique in the gain
amplifier to improve the system stability
First of all we segment the gain of our main amplifier into two parts- gm1 & gm2. The
advantages of doing that are manifold. Firstly we will be able to give high gain in the
amplifier which will produce very small load regulation. Then to improve the stability we
decide to apply the miller compensation technique around the amplifier gm2. This will
give a new location of all the poles and zeros in the system.
A
RF
2
gm1
gm2
RL
Resr
RF
1
Cb
Cout
Vref
gm2
Vin
C1R1
Cc
R2
RZ
C2

45
For the let’s consider the value of the parameters as follows:
Parameters of the gmamp1
gm1=400µA/V (3.36)
R1=20KΩ (3.37)
C1=500fF (3.38)
Parameters of the gmamp2
gm2=300µA/V (3.39)
R2=300KΩ (3.40)
C2=100fF (3.41)
From the analytical observation and AC simulation we set the value of compensation
network element values. The value of compensating capacitor Cc and the value of RHP
nullifying resistance Rz for best stability are
Rz=60kΩ (3.42)
and, Cc=6pF (3.43)
Then the new pole and zero location will be
KHz
CRRg
P
cm
15
....2
1
122
1 

(3.44)
9
2
2m
2 103
C2
g
P 
.
(3.45)
MHz54
CR2
1
P
1z
3 .
.


(3.46)
KHz
CR
g
Z
cz
m
500
)
1
.(2
1
2
1 


 (3.47)

46
Fig 3.15: AC simulation of the compensated network with output capacitor in
full load condition with no ESR zero
From the Fig 3.15 we can see that dominant pole moves closer than before as dominant
pole is Pgm in 15K now where as previous dominant pole was PLoad in 50K. So the
bandwidth of the system decreases to approx 200 KHz which was 2MHz in
uncompensated system. We can see that up to the unity gain point it is only double pole
roll off. This is because the miller compensation network brings the gain amplifier pole,
Pgm at 15KHz according to the eq. 3.36 which was in approx 200K previously. The other
pole which is the driver stage pole, Pdrv which is in 300K approx, is driven away from
origin as an artifact of its pole splitting advantage. And lastly the Miller compensation
zero ZComp in 500KHz, outside the unity gain point, improves the phase margin without
increasing the bandwidth. That’s why the phase margin in unity gain point is approx 20
degree which was -40 degree in the uncompensated system.
PLoad
Phase improvement
for zero, ZComp
Pgm
Unity Gain Point
Gain Bandwidth ≈ 200KHz
Phase Margin ≈ 20 deg
Gain
Phase

47
Fig 3.16: AC simulation result of the compensated system with ESR range
of 10mΩ to 10Ω
In the AC simulation in the Fig 3.16 we step the ESR value of the output capacitor from
10mΩ to 10Ω in the compensated system in full load condition. We can see that the
phase margin is worst (approx 20 degree from Fig 3.16), in case of lowest ESR value of
10mΩ as in this case the help of ESR zero is minimum. But we can clearly see that the
system is stable in the whole ESR range from 10mΩ to 10Ω for 1uF output capacitor.
The maximum phase margin is 55 degree in case of 10Ω ESR value. So we can say that
the compensated system is stable in the full ESR value range which means that the
stability of the regulator is ESR value independent. In addition we can also say that any
type of capacitor we will be able to use with the system without being worried about
stability.
PLoad
Zesr step
15 KHz for 10Ω
6 MHz for 10 mΩ
Pgm
Unity Gain Point
Gain Bandwidth ≈ 200KHz to 2MHz
Phase Margin ≈ 55 deg for 10Ω ESR
Gain
Phase
Phase Margin ≈ 20 deg for 10mΩ ESR

48
Fig 3.17: AC simulation result of the compensated system with no ESR and
no output capacitor.
The Fig 3.17 above shows the most fascinating part of the stability proposal of this LSO
regulator where we can see here that the system is stable without any output capacitor
and it’s ESR. Here the dominant pole is Pgm in 15K and after that single pole roll-off
almost up to the 1.5MHz bandwidth. Finally we can say that this stability approach is
independent of the type and the value of output capacitor. This is a very significant factor
for a LDO regulator as in most of the practical cases we find that a CMOS LDO in any
SOT package has surface area equal to surface mount capacitor and smaller that other
type capacitors. In that respect it will reduce a large component in the PCB board which
will eventually reduce the cost and space in the PCB board.
Single pole roll-off
Unity Gain Point
Gain Bandwidth ≈ 1.5MHz
Phase Margin ≈ 50 deg
Gain
Phase
Dominant Pole, Pgm

Chapter 4
Process Issues and Implementation
4.1 Pseudo BiCMOS Process and its Issues
BiCMOS technology is a combination of Bipolar and CMOS technology. CMOS
technology offers less power dissipation, smaller noise margins, and higher packing
density. Bipolar technology, on the other hand, ensures high switching and I/O speed and
good noise performance. It follows that BiCMOS technology accomplishes both -
improved speed over CMOS and lower power dissipation than bipolar technology. The
main drawback of BiCMOS technology is the higher costs due to the added process
complexity. Impurity profiles have to be optimized to both NPN and CMOS issues. This
greater process complexity results in a 1.25 to 1.4 times cost increase compared to
conventional CMOS technology [29].
The primary approach to realize high performance BiCMOS devices is the addition of
bipolar process steps to a baseline CMOS process. To realize the BiCMOS process flow
clearly we discuss in this section a 0.8μm BiCMOS process flow, emphasizing reliability,
process simplicity and compatibility with a 0.8μm CMOS technology.
The integration of the bipolar process steps into the baseline CMOS process flow is given
by Table 4.1. First, the P+ substrate is replaced by a P- substrate material to incorporate
the NPN device into the N-well of the PMOS device. This lower doped substrate
increases the susceptibility for latchup. To improve latchup immunity retrograde N-well
doping is used. The retrograde doping can be either achieved by high energy ion
implantation or by using buried layers. With the first approach no epitaxial layer is
required, but ion implantation damage has to be considered. By using buried layers a
relatively thick and expensive epitaxial layer has to be grown on top of the substrate. This
epitaxial layer hosts the collector of the NPN as well as the P-well and the N-well of the
CMOS devices. The epitaxial deposition process must be optimized to reduce material
defects and minimize autodoping.

Chapter 3 - Process Issues and Implementation
50
CMOS process Change for Bipolar process
P+ Substrate P- Substrate
Buried N+/P- Layer
P- Epi Intrinsic doped EPI-Layer
N-well/ P-well
Well drive in Reduce drive time
Poly Buffer Locos High pressure Oxidation
Deep Collector/N+ Resistor
Base/ P resistor
Vt implant
Gate oxidation( 200 ˚A)
Poly Deposition/Doping Poly Deposition
Emitter Pattern/Etch
Implant Poly Emitter
Pattern/Etch Poly
LDD pattern/Implant
SWO Deposition/Etch
Pattern/Implant N+/P+ S/D
Anneal S/D Anneal optimization for Emitter
Table 4.1: BiCMOS process flow showing the integration of a bipolar
process into an existing baseline CMOS process.
Due to the usage of the buried layers the well drive-in has to be optimized for bipolar
collector requirements. From the bipolar point of view the collector profile should consist
of a thin heavily doped collector region (buried N+ layer) and a thick lightly doped
collector region on top. The first one minimizes the Kirk effect, where the second one
ensures higher collector-base breakdown voltage. The CMOS device on the other hand
requires a sufficiently high concentration below the surface to avoid punchtrough,
especially as device dimensions are shrinking. Practically, the various conflicting
requirements have to be balanced.

51
This leads to steeper collector N-well profiles which cause an increase of the collector
series resistance. To improve the collector series resistance a deep subcollector N+
diffusion is used.
Finally, the same polysilicon material is used for the fabrication of the NMOS and PMOS
gates as well as for the bipolar polysilicon emitter. The doping for the emitter junction is
usually provided by a N-type implant into the polysilicon, which forms the emitter-base
contact during the source-drain anneal of the CMOS device by outdiffusion. The N-type
polysilicon gates result in a surface channel NMOS device and a buried channel PMOS
device. In the process, we call pseudo BiCMOS process we didnt use buried layers for
cost minimization and for less process complexity. The process musks are like this
For CMOS process
Substrate (PSUB)
1. N-well
2. Thin Oxide Layer (to form diffusion)
3. Poly to form gate or connector & block diffusion
4. N+ Implantation
5. P+ Implantation
6. Contact
7. Metal1
8. VIA Hole
9. Metal2
10. Passivation / Pad opening
Additional layer for Mixed-signal process:
1. Deep N-well
2. P-well
3. N-base
4. Vt-adjust
5. Second poly
Absence of the buried layer in pseudo BiCMOS process interoduces some additional
issues. they are like beta of bipolar is very small, ac performance of the bipolar devices
are not good, latch-up tendency increased quite highly, and most importantly collector
resistance increases very high which makes the bipolar velnerable to saturation at high
current and decrease the maximum current capacity of bipolar at the end.

52
4.2 Amplifier Design and Issues
Block wise the amplifier design part is the most important and challenging for any
designer in a LDO regulator design.The first deciding factoe of the amplifirer is its gain,
which will be decided by the laod regulation number. Load regualtion is pefered to be as
small as possible whch calls for maximizing the gain. On he other hand gain will be
constrained by the stability issue as for a fixed output pole higher the gain higher will be
the bandwidth and the system becomes more unstable. For our system we decise to give
open loop gain 60dB whcih is considered as very high gain for any conventional LDO
regulator.
Fig 4.1: Amplifier Gain Stage Implementation methodology
For giving this high gain first we decide to give this gain in two stages followed by the
third stage pass transitor. The first stage gain, gm1 is approximately 400µA/V and use
bipolar NPN as gain elemnet. We use PTAT (proportional to temperature) current for
biasing which will produce the gain equation like this
RF
2
gm1
Pass Tran
gm3
RF
1
Vref
gm2
Vin
C1
R1
R2
C2

53
Ak
R
R
k
R
VtR
kVt
R
Vt
Ic
RgmA
o
o
o
ov
.
.
1
.
.
.
1
1
1
1
1
1
11





Here, Av is the voltage gain of the first stage where NPN is the input device, gm1 is the
current gain of the first stage, Ic1 is its bias current, Ro1 is its output resistance, and K and
A are constants. Its bias current comes form the REF bias current generator which is a
PTAT current. We can clearly see from the equation above that if PTAT current
generation resistance R1 and gain stare output resistance Ro1 are same type then amplifier
first stage gain will be irrespective of the resistance process variation and vt variation. So
the Av1 will be irrespectivr of process and temperarture variation.
In the second amplifier (AMP2) we decide to use folded cascade topology for its output
voltage rail to rail swing advantage and high gain producing capacity. We make the
output of the AMP2 single ended while AMP1 output was differential one. At the output
we use resistance to make the gain process and temperature independent like we did in
AMP1.
The third and last stage is the pass transistor. This is a huge PMOS device in order to
keep dropout voltage low. Gain of this stage will vary with process and temperature and
load.
So the total variation in the gain will be the gain variation of pass transistor. In this case
maximum to minimum gain ratio will be 2:1 to 3:1 with process and temperature where
as in a conventional amplifier this ratio can be as large as 10:1.

54
4.3 Reference Design and Issues
Reference block is one of the major blocks in any regulator. This constitutes a precise
band-gap core. The principle of the band-gap core [3] relies on two groups of transistors
running at different emitter current densities. This difference in the current densities
cause a difference between the base-emitter voltages, let’s call it ∆VBE .
From the large signal behavior of the bipolar transistor and neglecting the base current
(for high βF ) of it, we have the following relationship













1
1
1 ln
S
BE
I
I
q
KT
V
(4.1)













2
2
2 ln
S
BE
I
I
q
KT
V
(4.2)
and 2211 & AIAI SS 
.
,
,&
where,
222
111
transistorbipolaraofareajunctionemitterbaseA
currentsaturationI
III
III
S
EC
EC




(4.3)
)ln(
)ln()(
2
1
2
1
12
A
A
V
A
A
q
KT
VVV
T
BEBEBE


 (4.4)
for I1=I2, i.e in the balanced condition of the band-gap core.
VT = )(
q
KT
,is called thermal voltage.
The core, used in the design, has the emitter area ratio of 8:1, i.e. A1:A2=8:1 and it’s
shown in the Fig 4.2.

55
Fig 4.2: The basic Band-gap core we used in reference.
In the design, the rich transistor will runs at 8 times the density of the lean ones, and a
factor of 8 will cause a 54 mV (i.e. 26mv*ln8) delta between the base-emitter voltages of
the two groups. This delta voltage is usually amplified by a factor of about 10 and added
to a VBE voltage, i.e.
V
K
K
mvBG
V
R
R
V
VIRBG
R
V
I
BEBE
BE
BE
212.1
6.0
30
170
)54(2
1
2
2
22
,
1







56
4.4 Current Limit Circuit
Current limit methodology has two basic parts.
1. One is output current sense block – where we sense the output and create a
proportional voltage.
2. Second part is where we compare this voltage with a program voltage and
create two things- one is logic ‘ILIM’ and a push current proportional to the error voltage
of the comparator.
Fig 4.3: Current Limit Implementation Methodology
The load current is shared among Pass transistor P2 and ILIM sensing power transistor
P3 according to their width ratio which is here 150:9. So if we set the current limit
threshold 600mA then current through P3 will be 36mA. Here we have to keep the
voltage drop across the ILIM resistance i.e. Vcs significantly smaller that the total Vds of
pass transistor in ILIM mode so that Vcs does not degenerate the source of P3. For this
reason we have to keep this voltage drop as small as possible. The other side constraint

57
comes from the ILIM comparator. We need to keep this input signal level as high as
possible for minimizing offset of the comparator. So we have to choose the CS resistance
such a way so that the input voltage is 50mV to 100mV which is a moderate voltage level
for both purposes.
When the load current crosses the ILIM threshold current then the voltage across ILIM
sense resistance CS, Vcs will crosses the programmed ILIM threshold voltage PROGV.
Then immediately the ILIM comparator will give an ILIM logic high signal and ILIM gm
block will produce a pushing current IILIM proportional to error voltage. This IILIM will be
pushed in the pass transistor gate Vgpass and try to take it to higher potential to reduce
Vgs, so that output current can not increase anymore. At the same time if we think about
the regulator feedback loop we can realize that as the output voltage is low because of
short circuit condition, loop will try to push more current through the pass transistor to
pull the Vout up. Here comes the requirement of the ILIM logic. At that time ILIM logic
will turn off the driver stage high gate pulling current. As a result the pass transistor gate
will not be pulled down by the loop as soon as short circuit condition happens, rather will
go to higher potential to decrease the Vgs of pass transistor. This phenomenon is very
important by the way. Because if we allow the Vgpass node to fall down momentarily, it
will produce a high current spike in the output which may damage the die by producing
high temperature in the die.
Another important thing is the short circuit current limit variation over temperature and
process. First of all if the program voltage is a PTAT voltage then it will be process
independent and will increase with temperature. So the over all current limit process
variation will be only the sense resistor process variation. We have chosen the poly1
resistance as sense resistance which has very little process variation and increases with
temperature. So surely we can say that temperature wise voltage across sense resistance
Vcs and program voltage VPROG have the same direction. The over all temperature
variation of current limit will be temperature variation difference of PTAT voltage and
poly1 resistance.

58
4.5 Layout Implementation Issues
Device Mismatch Issue in layout
Two devices with the same physical dimension in layout never have quite the same
electrical properties. Variations between devices are called mismatches. Mismatches may
have large impacts on certain circuit parameters, for example common mode rejection
ratio (CMRR) [30]. Mismatches may be either
 random or
 systematic, or
 a combination of both.
Random Mismatches
Random mismatches are usually due to process variation. These process variations are
usually manifestations of statistical variation, for example in scattering of doping atoms
or defect sites. Random mismatches cannot be eliminated, but they can be reduced by
increasing device dimensions. In a rectangular device with active dimensions W by L, an
area mismatch can be modeled as:
WL
Kp
P )( (4.5)
Random mismatches thus scales as the inverse square root of active device area. To
reduce mismatch by a factor of two, increase area by a factor of four. Precision matching
requires large devices. Other performance criteria (such as speed) may conflict with
matching.
Systematic Mismatch
Systematic mismatches may arise from imperfect balancing in a circuit. For example: A
mismatch ∆VCE between the two bipolar transistors of a differential pair generates an
input offset voltage ∆VBE equal to:
CE
A
T
BE V
V
V
V  (4.6)

59
Systematic mismatches may also arise from gradients. Certain physical parameters may
vary gradually across an integrated circuit, for example: Temperature, Pressure, Oxide
thickness. These types of variations are usually treated as 2D fields, the gradients of
which can (at least theoretically) be computed or measured. Because of the way we
mathematically treat these variations, they are called gradients.
Fig 4.4: Temperature gradients caused by the Power Device in the die
Even subtle gradients can produce large effects. A 1°C change in temperature produces a
–2mV in VBE, which equates to an 8% variation in IC. Power devices on-board an
integrated circuit can easily produce temperature differences of 10–20°C.
Matching Techniques in Layout
Unlike the digital layout device matching issue is a very significant issue in analog layout
and hence requires meticulous manual layout craftsmanship. Three fundamental matching
techniques are followed all through out this entire layout.
1. Orientation (all device should be placed either horizontally or vertically)
2. Placement (all devices are to be placed at closest distance)
3. Co-location (all nodes i.e. VDD, VSS or S/D from matched devices should be
one metal line)

60
Fig 4.5: NMOS transistor standard matching
In the Fig 4.5 a standard MOS matching is shown in case of a diode and its current
mirror layout. Here Diode ND1 is at middle and all MOS are on same orientation and
all MOS are at minimum spacing. Along with standard matching techniques analog
layout requires some special high accuracy matching techniques in some critical
circuits maintain high performances. These techniques are
1. Inter-digitization
2. Cross coupling
3. Same isothermal plane (i.e. equidistance from power device)
4. Common-Centroid
5. Cross-cell matching.
Fig 4.6: NPN with Common-Centroid matching

61
Fig 4.7: MOS with Cross-couple match
In the Fig 4.6 we give the picture of common-centroid bipolar NPN matching which
we have used in Reference circuit layout to minimize the offset in the bandgap circuit.
We have shown the MOS cross-couple matching in Fig 4.7 is used in amplifier input
pair matching, current mirror matching etc.
Fig 4.8: Resistances with inter-digitized matching
The resistance inert-digitized matching shown in the above Fig 4.8 serves the critical
resistance matching requirements. We have used this technique in many places in ore
layout like in R1 and R2 matching in bandgap core shown in Fig 4.8 or amplifier
output resistance matching in gain amplifier first stage etc.

62
Metal path issues
We have used 2 metal layers in this layout, metal1 and metal2. Few things about
metal line path we have to consider in the layout. First of all, metal width for metal
bus line for adequate current capacity. In this layout we kept the VDD, VSS or high
current path like current limit resistance path, pass transistor metal path for maximum
load, transient current for pass gate charging-discharging in driver block etc.
Fig 4.9: Wide Metal for High current path in ILIM Sense Resistance
Another thing we kept had to consider about metal connection in this layout is – the
ILIM sense i.e. CS node connection with pass transistor we can see in Fig 4.3. We had
to make sure the metal resistance is not added with the CS resistance. That’s why we
had to take the CS resistance sense connection right form the end of the resistance.
We had to check the high current ground metal path if it is minimum metal path to the
pad or not. If the high current ground path is too long the ‘ground bounce’ may occur.
We also check that REF ground and amplifier ground is connected through shortest
possible metal line. Other wise an offset may exist in the main amplifier.
There are few more things those should be taken care of. One of those issues is metal
overlap. We need to be very careful that in a critical node metal1 and metal2 should
not be overlapped in a big area. That might add metal1 to metal2 capacitance in that
critical node.

63
Latch up issue
Latch up problem, inherent in the standard CMOS technology is due to the relativity
large number of PNPN junctions which are formed in these structures and the
consequent presence of parasitic transistors and diode [3].
Fig 4.10: Parasitic lateral NPN and vertical PNP bipolar transistor in
CMOS integrated circuits.
Fig 4.11: Equivalent circuit of the SCR formed from the parasitic
bipolar transistors.
In order to for latchup to occur, one of the junctions in the sandwich must become
forward biased. In the SCR structure in the Fig 4.11, current must flow in one of the
resistors of Rn and Rp. This current can come from a variety of causes. Examples are
an application of a voltage that is larger than the power supply voltage to an input or
output terminal, improper sequencing of the power supplies, presence of large dc
currents in the substrate or p- or n-well, or the flow of displacement current in the
substrate or well due to fast charging internal nodes. Latch up is more likely to occur
in circuits as the substrate and well concentration is smaller. All these trends in
process technology tend to make the ohmic resistances in the Fig 4.11 higher, and also

64
tend to make the beta of the two transistors higher. Both these changes increase the
likelihood of the occurrence of latchup.
The layout of CMOS- integrated circuits must be carried out with careful attention
paid to the prevention of latch up. In our layout we had to be careful that no high
current should be flown through the substrate or well. So we include the special
protection structures at each input and output pad so that excessive current flowing
into or out of the chip are safely shunted.
The second thing we did in our layout to protect our circuit from latchup we surround
our NMOS by p-diffusion guard-rings ion substrate and surround the PMOS with n-
diffusion ring in n-well. These two guard ring pick up will produce a series low
impedance in parallel with the high impedance Rn and Rp in the Fig 4.12
Fig 4.12: an ordinary latch-up condition due to successive PNPN junctions
In the Fig 4.12 we can see that one PMOS in the left which is crated in the n-well is
surrounded by the n-diffusion pick up and taken to the chip supply potential. Same
way the NMOS on the right is surrounded by the p-diffusion substrate pick up which
is taken to the ground potential.

Chapter 5
Proposed Enhancement of Performance
5.1 Noise Improvement & Quick Charge Block
Noise is one of the most important features of the LDO regulator. Fig 5.1 shows the
output noise voltage performance of the reference. The circuit shows some 1/f noise
as well as significant thermal noise. The 1/f noise comes from the PMOS transistors
defining the temperature dependent currents flowing through the output. Appreciable
thermal noise results from the use of large resistors at the output of the reference. The
noise bandwidth is defined by the load capacitor of the reference. The resulting output
noise voltage starts to drop at a frequency between 6 and 10 kHz and at a rate of
roughly 20dB/dec. The overall noise content can be improved by simply reducing the
noise bandwidth, which is achieved by increasing the load capacitance of the
reference.
Fig 5.1: Spectral Noise density and integrated noise from the AC
simulation of REF

Chapter 4 - Proposed Enhancement of Performance
66
That’s why we put an RC filter after the REF voltage so that high frequency noise
becomes blocked in this filter. We have to choose the size of this RC filter very
judiciously. If the size is too big then BW will be very low which helps the noise
performance but it will take more time for REF to settle down. If it is too small then it
will loose its purpose. Normally filer capacitor which is called bypass capacitor Cbyp
is used externally, outside the chip. The resistance is used internally to make the RC
filter. The capacitor Cbyp can vary from no capacitor to 100nF capacitor depending
on the user’s noise suppression requirement. We have to choose the size of internal
resistance so that it can make the filter big enough to suppress noise. In this case one
limitation is die area- bigger the resistance bigger the area in layout. The other
limitation is loading effect. If any leakage current in bypass pin because of capacitor
leakage or pin ESD leakage then there will be voltage drop across this resistance.
Vdrop= Ileakage x Rfilter
Normally, there exists some leakage current in bypass pin especially in high
temperature, that’s why we can not make this resistance very big. We used here 300K
resistance.
Fig 5.2: Spectral Noise density and integrated noise from the AC
simulation of REF after using the Filter

67
Quick Charge Block
When user uses a capacitor in the bypass pin for noise rejection the startup will be
slower as the REF for the amplifier will take huge time to settle down. If we take a
RC like R=300K and C=10nF then RC time constant will be 3mS. So for a faster
startup we need to pre charge the capacitor by current boosting. That’s why we need a
quick charge block which can perform this action.
Fig 5.3: Noise elimination & Quick charging Startup methodology
From the Fig above we can see that quick charge block is connected to the filtered out
REF node. Operation methodology is like this- when the BYP node is in low
potential, in practical case at the starting it is in ground potential which is much lower
that 90% REF. So the quick charge amplifier gets a large error signal in input which
produces high push current in the BYP node through the PMOS. As the BYP voltage
increases, the error voltage decreases and then the push current decreases. This
regulated control of the current eliminates the chance of on-off oscillation of the
charging current. When BYP node reaches 90% REF then this quick charge PMOS is
turned off and BYP grows further 10% by the RC time constant.
300K
10nF
BYP

68
Fig 5.4: Simulation Result of the Regulator Startup without Quick
Charge Circuit.
Fig 5.5: Simulation Result of the Regulator Startup with Quick
Charge Circuit.
Vin
BYP pin
Vout
Startup time= 16mS
Vin
BYP pin
Startup time= 40uS
Quick Charge current to
charge BYP pin
BYP ready in 15uS
20mS for BYP ready

69
5.2 Load Transient Improvement
A very important specification for the LDO regulator is maximum allowable output
voltage change for a full range transient load current step. This value depends on the
application where the regulator is being used. For an application as a supply of digital
blocks, a much relaxed specification can be allowed. But this specification is not that
relaxed for most of the analog applications.
We know that the time ∆t1 required for the loop to respond to the applied load
transient is inversely proportional to close loop bandwidth BWcl. In typical
application the time ∆t1 is not only a function of bandwidth but also defined by the
internal slew-rate associated with the parasitic capacitance Cpar of the pass element in
Fig 2.2. The resulting time ∆t1 can be approximated to be
sr
par
cl
sr
cl
1
I
V
C
BW
1
t
BW
1
t

 (5.1)
where BWcl is the closed-loop bandwidth of the system, tsr is the slew-rate time
associated with Cpar, ∆V is the voltage variation at Cpar to produce load variation, and
Isr is the slew-rate limited current. Now the maximum output voltage variation ∆Vtr-
max caused by the full range transient load change will be
1
bo
laod
tr t
CC
I
V 

 
max
max (5.2)
where Co is the output capacitor, Cb is the the bypass capacitors and ILoad-max is the
maximum load-current. For our proposed LDO regulator, if BWcl is 600 MHz, Cpar is
100pF, ∆V is 0.7 V, Isr is 10uA which is the bias current at output stage of the gain
amplifier, Cout is 1 µF, and ILoad-max is 300mA, then loop response time ∆t1 from
equation (5.1) will be

70
6
66
6
12
3
10668
10710661
1010
70
10100
10600
1
1t










.
.
.
(5.3)
And from the equation (5.2) and value of ∆t1 from the equation (5.3) the maximum
output voltage variation ∆Vtr-max will be
V62
10668
101
10300
V 6
6
3
tr
.
.max




 


 (5.4)
This 2.6V transient voltage drop is very high compared to any standard and hence not
acceptable. To solve this we have to improve the ∆t1 number first. We propose to use
a buffer between the gain amplifier and the pass element to drive the pass element
gate capacitance Cpar to solve the slew problem. The slew-rate condition typically
occurs when the load-current steps from zero to full range. A typical topology is that
of a class-B push-pull buffer driving a PMOS pass element and associated parasitic
capacitance (Cpar). An example of this is illustrated in the simplified schematic of Fig
5.7 where the pass device is assumed to be a p-type transistor. This type of buffer can
easily supply 1mA slew current to Cpar at load transient response time. In that case the
value of Isr in the equation (5.1) will be 1mA which is almost 100 times multiplied
than previous one, 10uA. Now the response time ∆t1 will be according to the equation
(5.1)
6
96
3
12
3
10731
107010661
101
70
10100
10600
1
1t










.
.
.
(5.5)

71
Fig 5.7: Push-Pull pass-gate drive for load transient improvement
And putting the value of ∆t1 from the equation (5.5) in the equation (5.2), the
maximum output voltage variation ∆Vtr-max will be
3
6
6
3
tr
10519
10731
101
10300
V









 .max
(5.6)
It is clearly evident from the value of maximum output variation in load transient
response from equation (5.4) and equation (5.6) that load transient performance of
output voltage has been improved after introducing the buffer in the system.

72
5.3 Efficient Pass Transistor
The pass transistor we chose in this LDO is a PMOS. Since most of the silicon area is
used up for the power device, it is required to optimize the given silicon area for the
efficient operation of the regulator. In designing of the switch several factors are taken
into account:
a). Total resistance which decide the dropout performance,
b). The percentage of channel resistance in total resistance,
c). The current carrying capability of each segment of the switch.
In order to increase the efficiency of the regulator in the dropout mode, one of the
requirements is to reduce the I2
R loss of the switch and for that purpose the total
resistance of the switch needs to be reduced. Total resistance includes channel
resistance, parasitic resistances of metal layers, metal to metal contact, metal to
diffusion contact and diffusion resistance. However, this reduction, for a given silicon
area, depends on some parameters like the aspect ratio of the switches, orientation of
the switches, the pitch of the segments, the number of metal layers, the number of
contacts among different metal layers or between metal layer and diffusion etc.
We want to have the total resistance dominated by the channel resistance, as it’s the
more predictable part than any other sorts of resistance of the switch. The channel
resistance, as we know, is derived by the following relationship:
)(
1
tgs
ch
VV
R



(5.7)
To have the effect of the other resistances of the switch, minimized, several metal
layers (at least 2) are used in parallel, number of metal to metal and metal to diffusion
contacts etc. are increased.
Each type of metal has a safe current carrying capacity, above which there may have
some destructive effect. Hence, while designing a switch, special care has to be taken
in this respect.
Referring to Fig 4.18, a segment of switch with only 4 layers has been illustrated.
Here metal layer is the top most layer, then contact, then polysilicon (poly1) and
diffusion lays in the bottom most position.

73
Fig 5.8: A Sample Segment of a Switch Used
The switch segment shown in Fig 5.8, consists of four fingers of breadth B, two of
which are connected to Port E and the remaining two connected to Port F. At first, the
current enters the two fingers connected to port E, through the metal layer in the X
direction. It then flows downward in the Z direction through the contacts to the
diffusion and reaching the diffusion area it then flows in the Y direction through the
channels in that plane, underneath the polysilicon gates, comes upward through the
contacts to the metal layer of the fingers connected to Port F. Hence, for the channel
resistance we’ve,
W
L
Rch (5.8)
As the width W of each finger is increased or gate length L is decreased or both, the
channel resistance is decreased and vice-versa. Again, for the parasitic resistance of
metal and diffusion, we’ve,
B
W
Rx (5.9)
Metal
Contact
Diffusion
Polysilicon
Direction of
Current Flow
W
PL
B
X
Z
Port
E
Port
F
Y

74
Hence, with W the parasitic resistance of the switch increases. Hence, to have total
resistance minimized and the contribution of channel resistance to the total resistance,
maximized, an optimization is needed. Moreover, for the same area, these two
features will be changed with aspect ratio, orientation of the switch with respect to the
direction of current flow etc. Besides, the breadth B of each finger has to be optimized
for the maximum current density.
Fig 5.9: The Pass Transistor with Parasitic Resistances for
the Simulation Purpose
For the simulation purpose, the switch is modeled as shown in Fig 5.9. Here a normal
NMOS is used with its size calculated considering the required optimization of all the
resistances for a given area. The channel resistance is calculated by SPICE from its
information of size. The resistances for the parasitic elements are lumped in each side
of the MOS, as shown.

75
5.4 Shutdown Mode with Ultra Low Ground Current
The ENABLE/SHUTB pin of the regulator enables the whole part. When this logic
input is low then the whole part is in shut down mode. The bias current becomes zero
though supply is given to the part to make the power dissipation in the shut down
mode zero. Only issue here is that in very high temperature, especially more that 100
degree C, there are some leakage currents which is mainly caused by the zero Vgs
current of the CMOS devices. But we measured our maximum shut down ground
current at 125 degree C which is not more than 1uA.
In the shut down mode we turned off the pass transistor also. So the Vout becomes
zero by the load current as there is no current supply from pass transistor. We also
have an internal switch to discharge the output capacitor in shut down mode in no
load condition.
We have a transistor-transistor logic (TTL) compatible ENABLE input. This means
ENABLE pin does not have to go higher than vdd/2 point to become high. In our
design we guarantee that if ENABLE pin crosses 1.2V ENABLE will be considered
as high.
Temperature
I supply at
Shutdown
-40 1.23E-09
-15 3.16E-09
0 4.85E-09
25 6.23E-09
50 7.49E-09
75 9.00E-09
SHDN Current VS Temperature
0.00E+00
2.00E-09
4.00E-09
6.00E-09
8.00E-09
1.00E-08
-40 -20 0 20 40 60 80
Temperature
SHDNCurrent
Fig 5.10: Supply current at Shutdown mode at different temperature

76
5.5 Over Temperature Sense and Thermal Shutdown
When Vout goes into short circuit condition then the output current will be limited by
the current limit circuit, in our design 575mA. So naturally the power dissipation in
the pass transistor will be very high as the voltage seen by the pass transistor is the
full supply voltage. So the power dissipation, Pd = Vsupply x IILIM
= 5V (max) x 600mA
= 3 Watt
In that power dissipation package temperature will rise to more than 160 deg C. The
circuit has to be protected form that high temperature. So there is a thermal sense and
shutdown block which sense the die temperature and trigger if the die temperature
goes beyond 160 deg C. in that case this block generate a logic and stop the gate of
the pass transistor PMOS. So the load current collapses and power dissipation
becomes zero. Then naturally the part temperature decreases. In this way the part
temp crosses 130 deg C then the part becomes alive again.
Fig 5.11: Thermal Shutdown Implementation Methodology
From the above Fig we can see that when the temperature will increase then the VPTAT
will be increasing and as usual Vbe will be decreasing. When temperature will cross
the thermal shutdown threshold temperature, Tth then VPTAT will be large enough to
turn on the Q3. As a result there will be current on that branch. This is basically an
over temperature current which will increase with temperature after a certain
temperature and will not exist before that temperature.

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