Introduction to DSP - Digital Signal Processing
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Introduction to DSP - Digital Signal Processing For 2nd year engineering students (BTech) New Horizon College, Bengaluru
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Introduction to DSP - Digital Signal Processing
- 1. Shivananda (Shivoo) R Koteshwar General Manager & Site Head, MediaTek LINKEDIN : https://in.linkedin.com/in/shivoo2life SLIDESHARE : www.slideshare.net/shivoo.koteshwar New Horizon, 2nd Year Engineering (BTech), Bangalore April 2018
- 3. ¡ Digital Signal Processors (DSP) take real-world signals like voice, audio, video, temperature, pressure, or position that have been digitized and then mathematically manipulate them. ¡ A DSP is designed for performing mathematical functions like "add", "subtract", "multiply" and "divide" very quickly DSP is used in an MP3 audio player. D S P a p p l i c a t i o n s i n c l u d e a u d i o a n d s p e e c h processing, sonar, radar and other sensor array processing, spectral density estimation, statistical signal processing, digital image processing, signal processing for telecommunications, control systems, biomedical engineering, seismology, among others.
- 4. ¡ Signals need to be processed so that the information that they contain can be displayed, analyzed, or converted to another type of signal that may be of use ¡ In the real-world, analog products detect signals such as sound, light, temperature or pressure and manipulate them. Converters such as an Analog-to-Digital converter then take the real-world signal and turn it into the digital format of 1's and 0's. From here, the DSP takes over by capturing the digitized information and processing it. ¡ DSP then feeds the digitized information back for use in the real world. It does this in one of two ways, either digitally or in an analog format by going through a Digital-to-Analog converter. All of this occurs at very high speeds.
- 5. ¡ A DSP's information can be used by a computer to control such things as security, telephone, home theater systems, and video compression. ¡ Signals may be compressed so that they can be transmitted quickly and more efficiently from one place to another (e.g. teleconferencing can transmit speech and video via telephone lines) ¡ Signals may also be enhanced or manipulated to improve their quality or provide information that is not sensed by humans (e.g. echo cancellation for cell phones or computer-enhanced medical images). ¡ Although real-world signals can be processed in their analog form, processing signals digitally provides the advantages of high speed and accuracy ¡ Because it's programmable, a DSP can be used in a wide variety of applications. You can create your own software or use software provided by third parties to design a DSP solution for an application
- 7. ¡ Program Memory: Stores the programs the DSP will use to process data ¡ Data Memory: Stores the information to be processed ¡ Compute Engine: Performs the math processing, accessing the program from the Program Memory and the data from the Data Memory ¡ Input/Output: Serves a range of functions to connect to the outside world
- 8. ¡ Analog filter uses resistors, capacitors, inductors, amplifiers. It can be cheap and easy to assemble, but difficult to calibrate, modify, and maintain- a difficulty that increases exponentially with filter order ¡ For many purposes, one can more easily design, modify, and depend on filters using a DSP because the filter function on the DSP is software- based, flexible, and repeatable. ¡ Further, to create flexibly adjustable filters with higher-order response requires only software modifications, with no additional hardware- unlike purely analog circuits ¡ Mathematical transform theory and practice are the core requirement for creating DSP applications and understanding their limits.
- 10. ¡ Until about 25 years ago, most signal processing was performed using specialized analog processors. As digital systems became available and digital processing algorithms could be implemented, the digital processing of signals became more widespread. ¡ Initially, DSP was performed on general-purpose microprocessors such as the Intel 8088. While this certainly allowed for more sophisticated signal analysis, it was quite slow and was not useful for real- time applications ¡ In the 1980s, DSP such as the TMS32010 from TI emerged, which had similar functionality to microprocessors, but differed in that they were based on the Harvard architecture , with separate program and data memories and separate buses ¡ In other words, they were microprocessor architectures which had been optimized for DSP that perform multiply and accumulation operations, consuming less power. A more specialized design was needed ¡ A lot of changes in the original architecture have occurred since the inception of DSP microprocessors
- 11. ¡ Computationally intensive ¡ Highly suited to implementation with parallel processors ¡ Exhibits a high degree of parallelism, data independent ¡ Have lower arithmetic requirements than other high- performance applications, e.g. scientific computing
- 12. ¡ Pipelining § Reduce the effective critical path by introducing pipelining latches along the critical data path ¡ Parallel Processing § Increases the sampling rate by replicating hardware so that several inputs can be processed in parallel and several outputs can be produced at the same time Datapath pipelined Parallel Processing
- 13. ¡ The sequential nature of the microprocessor architecture makes it unsuitable for the efficient implementation of computationally complex DSP systems, either in that it cannot achieve the required sampling rate, or it meets the requirement, but consumes a lot of power. ¡ The serial architecture is such that for data processing applications, a lot of the transistors will not be performing any useful part in the computation being performed but are consuming power ¡ Microprocessors normally run large blocks of software, such as operating systems, and usually are not used for real-time computation ¡ A DSP, on the other hand, is designed to perform a fairly limited number of functions, but at very high speeds.
- 14. ¡ Are really just specialized microprocessors ¡ The digital signal processor must be capable of performing the computations necessary to carry out the techniques like transformation to the frequency domain, averaging, and a variety of filtering techniques ¡ In order to perform these operations, a typical digital signal processor would include the following elements: 1. Control processor 2. Arithmetic processor 3. Data memory 4. Timing control 5. Systems
- 16. ¡ Very Long Instruction Word (VLIW) ¡ Increased number of data buses ¡ Fixed point operation ¡ Bit-serial processing ¡ Pipelining ¡ Parallel processing ¡ Array processing – Systolic and Wavefront Arrays ¡ Reduced Instruction set computer (RISC) ¡ Multiprocessing ¡ Retiming
- 17. ¡ The various wireless communication technologies have led to the tremendous increasing demand for mobile processing devices which has intensive DSP and communication blocks ¡ Unlike wired devices that are optimized in favor of performance § minimization of power/energy consumption while maintaining a certain level of performance is a critical concern for wireless devices with limited energy capacity § With continuous demand for increasing levels of performance, Digital processing techniques requires high levels of computational throughput, particularly for real-time applications ¡ The trend in DSP design is toward more algorithm-based architectures. In other words, the ease with which VLSI design can be done today leads the designer to more specialized architectures. ¡ Research is focused on the voltage over scaling (VOS) techniques in DSP and communication system design, such as filters, FFT/IFFT, etc. § The VOS is one of the most prominent techniques that can significantly reduce the power consumption at the cost of incurring computational error/noise due to timing violation. § This is because as the supply voltage scales the power consumption decreases quadratically while the delay increases linearly. ¡ Research is also in low-power architectures for biomedical applications. Specifically efforts are directed towards low-power feature extractors and classifiers.
- 18. ¡ Efficient power estimation tool development § Power estimation for DSP circuits based on switching activity estimation which incorporates glitching ¡ Various approaches to low-power arithmetic implementations are being addressed ¡ New types of low power binary adders ¡ Various division, square-root and CORDIC architectures are being evaluated for low-power consumption ¡ Approaches to power reduction in parallel FIR filters through novel strength reduction ¡ Novel approaches to power reduction by gate resizing, supply voltage scheduling and threshold voltage scheduling ¡ Low Power DSP system design approaches by pipelining of DSP structures or novel arithmetic architectures
- 19. ¡ Development of algorithms and design tools for rapid prototyping of these algorithms using either dedicated VLSI chips or commercially available programmable digital signal processors or using field-programmable systems § Folding techniques to design any bit-serial architectures from digit-serial or bit-parallel, and to design digit-serial architectures from bit-parallel ones which can be pipelined at sub-digit levels § Usual adhoc approaches limits the digit-size to be a divisor of word-length. Newer techniques to accommodate arbitrary digit sizes § Developing multiple rate signal processing algorithms – such as interpolation and decimation ¡ In hardware system prototyping, we are concerned with high-level hardware synthesis of specified algorithms for specified sample rate constraints, with the objective of minimizing the number of functional units (such as adders, multipliers, latches, buses, and interconnections etc.) ¡ Focus is on addressing systematic pipelining, retiming, unfolding of data-flow graphs for unraveling the hidden concurrently in algorithms, addressing scheduling and resource allocation for fixed multiprocessor architectures for software system prototyping of signal processing problems, minimization of registers in data path,
- 20. ¡ In 1960s and 1970s, digital signal processing algorithms were implemented using the available microprocessors which executed the algorithms sequentially. Therefore, there was no motivation for designing concurrent signal processing algorithms, which could exploit pipelining or parallelism ¡ But today it’s a world of parallel processing. The efforts are in § Transforming existing non-concurrent algorithms into concurrent forms to create pipelining and parallel processing § Designing new algorithms which are inherently concurrent- Sum, delay, and product relaxed look-ahead techniques
- 21. ¡ Achieving pipelining and parallel processing in encoders and decoders used for speech and image processing applications § Because the processing of high-definition and super high-definition television video signals requires very high data rates § Demands of the high-throughput real-time signal and image processing application is the trend
- 24. ¡ Involving use of advanced signal and image processing techniques in classification of biomedical signals ¡ The objective here is to use signal processing for preprocessing and feature extraction and use classifiers for classification. ¡ Applications include epilepsy detection and prediction, lung sound signal processing, automated fundus eye scan analysis for diabetic retinopathy and glaucoma screening, and detection of neural disorders ¡ The work on language understanding of Schophrenic patients from MEG signals ¡ Synthesis of various signal processing functions by chemical or molecular reactions. These reactions are mapped to DNA strands. The objective here is to synthesize molecular reactions for a specified signal processing function. The emphasis is on design of robust reactions that are (almost) rate-independent. This research is expected to find applications in drug delivery and biosensing
- 25. ¡ Language Understanding of Schizophrenic Patients § Attempts to understand language understanding at various levels in from magnetoencephalogram (MEG) signals ¡ Molecular Signal Processing § This research attempts to understand synthesis of DSP functions through molecular reactions, where inputs and outputs are proteins or chemical molecules § One example of implementation involves DNA strands. § Synthesizing signal processing functions in biochemical and biomolecular systems will enable biosensing, drug delivery, monitoring and controlling rate of therapy or treatment § Efforts are directed towards implementation of FIR and IIR digital filters, FFTs, and equalizers using chemical reactions. Efforts are also directed towards implementation of iterative computations through the molecular reactions ¡ Design Deep Brain Stimulation Therapy for Parkinsons and Dystonia ¡ Lung Sound Analysis
- 27. Existing Components ¡ Central processing Unit (CPU) ¡ Digital Signal Processing (DSP) ¡ Graphical processing Unit (GPU) New Components ¡ Neural Processing Unit (NPU) ¡ AI Accelerator Chip ¡ Tensor Processing Unit (TPU) ¡ Brain inspired Computing ¡ Neuromorphic computing ¡ Neurosynaptic Chip (Cognitive Chip) ¡ Bionic Chip ¡ SDN (software-defined networking) ¡ NFV (network functions virtualization) ¡ Computer vision accelerator (CVA) ¡ pseudo-static RAM (PSRAM)
- 29. Google Pixel Buds Sony Glasses
- 33. ¡ Comparing the performance of DSPs is not always a straightforward procedure. ¡ While MIPS (million instructions per second) or MFlops (million floating-point operations per second) are often used when comparing microprocessor speed, this is not well suited to DSPs ¡ A common benchmark for comparing the performance of DSPs is the multiply and accumulate (MAC) time ¡ The MAC time generally reflect the maximum rate at which instructions involving both multiplication and accumulation can be issued. More meaningful benchmarks would be computations such as FFTs and digital filters
- 34. ¡ VLSI Digital Filters ¡ VLSI Speech and Image Coders ¡ Binary and Finite Field Arithmetic Architectures ¡ Design Methodologies for Signal Processing Low-Power ¡ DSP System Design ¡ Digital Integrated Circuit Chips ¡ Error Control Coding ¡ Ultra Wideband Systems ¡ High Speed Transreceivers ¡ 3D Video Systems ¡ Soft Decision Reed-Solomon Decoder
- 35. ¡ Digital signal processing (DSP) applications are becoming more prevalent in everyday use ¡ Because of this widespread usage and advances in computer technology, the DSP algorithms themselves are being subjected to more demanding specifications ¡ There is a constant need for designing systems with lower power, higher speed (>100G bps), and lower area ¡ Focus is on developing new algorithms, architectures, techniques, and design tools
- 36. ¡ Audio Signal Processing, Audio Compression, Speech processing, Speech Recognition § hi-fi loudspeaker crossovers and equalization, and audio effects for use with electric guitar amplifiers § Speech compression and transmission in digital mobile phones § Room correction of sound in hi-fi and sound reinforcement applications ¡ Digital Image Processing, Video Compression § Medical imaging such as CAT scans and MRI, MP3 compression, computer graphics, image manipulation ¡ Digital Communication, RADAR, SONAR, Seismology § Weather forecasting, economic forecasting, seismic data processing, analysis and control of industrial processes ¡ Biomedical Signal Processing is another important area of research § Signal Processing, Machine Learning and Classification are important tools for biomedical signal processing – Feature extraction and classification is key here § Monitoring, Diagnosis, Prevention and Therapy is driven by DSP § Signal processing for monitoring and processing proteins
- 37. ¡ Software Configurable Global Positioning Systems Receiver ¡ Wireless FSK burglar alarm: algorithmic/structural/architectural design and gate array implementation ¡ Digital/switched-capacitor filters for integrated very low frequency, vehicle burglar alarm system ¡ Digital part of a SD CODEC: feasibility study and architectural design for custom-silicon ¡ Software Radio Cellular Base station System: Feasibility Study, Design and Development ¡ Interactive Virtual Classroom ¡ Software DAB Radio Receiver: design, implementation and frequency synchronization in software ¡ Linear mixed-signal SD CODECs for GSM base station: design and implementation ¡ SD based fast hopping fractional-N frequency synthesizer: design and FPGA implementation ¡ Programmable switched-capacitor ladder-filter chipset for duplex modem systems complying with the CCITT magnitude and group delay specification ¡ Oversampled PWM 28-bit DAC for very high fidelity audio applications: feasibility study and architectural design for custom- silicon implementation ¡ Integrated SD based mixed-signal commander for mobile telephone systems: trouble-shooting and correction ¡ 13-bit linear mixed-signal SD CODEC for GSM mobile systems: algorithmic/structural/architectural design and silicon implementation ¡ GSM base station SD ADC: algorithmic/structural/architectural design, implementation and silicon integration ¡ Algorithmic/structural/architectural design, silicon integration and implementation of a mixed-signal, SD and All pass polyphase based low-power CODEC, for use within a Completely In Canal (CIC) digital hearing aid chip ¡ GNSScope: Platform for rapid prototyping and testing of designs targeting multi-platform multi-frequency GNSS systems ¡ Ultra-low power configurable baseband processor for GNSS algorithms ¡ Adaptive IIR filtering techniques for channel equalization applications ¡ Efficient frequency transformation algorithm and toolbox development ¡ Low-power reconfigurable full-custom DSP processor design and development ¡ Novel frequency estimation algorithm development and Implementation ¡ Adaptive schemes for non-linear distortion compensation in communication systems ¡ ULTRA-low-power algorithm development for real-time biomedical application
- 38. ¡ Research into natural algorithms for fixed and adaptive digital filtering. ¡ Development of fractional-delay filters for sample rate conversion and beamforming. ¡ Research in the area of modelling and design of wireless communication systems. ¡ Development of new signal processing architectures and architectural component realisation in full-custom integrated circuits. ¡ Development of switched-capacitor filters for telecommunication applications. ¡ Development of IIR filter design techniques based upon balanced model truncation of much higher order FIR filters. ¡ Development of computer-aided packages for the design of discrete-time filters. ¡ Evaluation of adaptive notch filters for tracking and eliminating harmonic interference in mains-powered systems. ¡ Research into sigma-delta data conversion techniques for baseband and bandpass applications. ¡ Design and silicon implementation of bitstream codecs for mobile telephone applications. ¡ Development of high-fidelity decimators using polyphase allpass filters. ¡ Low-distortion wideband microwave amplifier design. ¡ Research into the suppression of harmonic distortion in microwave transmission systems. ¡ Development of Global Positioning Satellite (GPS) receiver systems. ¡ Research into asynchronous logic techniques to realise low-power digital signal processors. ¡ Research into flexible receiver structures and architectures for software radio applications. ¡ Breaking the Nyquist barrier using non-equispaced sampling for radar applications. ¡ Computer-aided techniques for the design of RF and microwave filters. ¡ Development of ultra-low-power digital signal processors for use in digital hearing aids. ¡ Research into high-quality digital image processing for biomedical and urban traffic control applications
- 42. ¡ Belakoo Education Trust offers free quality education for underprivileged children. We run STEAM programs for Government School kids substituting their learnings at school. ¡ We participate in Skill Development Program for students under various running central/stage level schemes https://www.facebook.com/belakootrust/
- 45. ¡ https://www.engadget.com/2018/04/06/mit-wearable-silent-words/ ¡ http://www.analog.com/en/analog-dialogue/articles/dsp-101-part-1.html ¡ http://www.analog.com/en/education/education-library/ scientist_engineers_guide.html ¡ http://www.ee.umn.edu/users/parhi/current_research.html ¡ http://www.advrg.wmin.ac.uk/about.html ¡ http://www.dspguru.com/ ¡ http://sestevenson.wordpress.com/ ¡ http://www.ee.umn.edu/groups/ddp/research.html ¡ http://www.ee.umn.edu/users/parhi/past_research.html ¡ https://www.youtube.com/watch?v=I2T3OYNqhyA
- 49. § Design of pipelined and parallel recursive digital filters, recursive lattice digital filters, recursive wave digital filters, LMS adaptive digital filters, adaptive lattice digital filters, two-dimensional recursive digital filters, and rank-order and stack digital filters § Examining Finite word-length effects in these filters for fixed-point hardware implementations and introducing pipeline in these algorithms § Pipelined stable recursive digital filters § Pipelined architecture topologies for various forms of adaptive filters § Recursive least square (RLS) adaptive filters § Annihilation Reordering Look-Ahead recursive least square (RLS) adaptive filters can also be pipelined based on Givens rotation; these filters maintain exact orthogonality. Truly orthogonal IIR recursive filters have also been developed. These structures provide excellent round-off noise properties.
- 50. ¡ Forward-error correction (FEC) codes can be used in almost all kinds of communication systems (wireless, wireline, fiber optic network, etc.) to provide significant gains over the overall transmit power budget of the link, and at the same time, lower the bit error rate. ¡ Research is on on both soft-decision and hard-decision error control code ¡ e.g. Convolutional Viterbit and Turbo Codes, Block Turbo Codes, LDPC Codes (a re-discovery), conventional Convolutional Codes and Reed-Solomon Codes.
- 51. ¡ As Ultra wideband (UWB) wireless communication has very high data rates, ultra-low power consumption, robustness to interference and fine ranging capabilities, it has been chosen as candidate for different wireless personal area network (WPAN) standards, including IEEE 802.15.3a and 802.15.4a. ¡ Research is on low power, area-efficient implementation of different modules in digital baseband system in the wireless UWB systems, including FFT/IFFT processors, time-domain/frequency- domain equalizers, channel code decoders (Viterbi decoders and LDPC decoders) ¡ Research to address the algorithms related to ranging, geolocation, MIMO-UWB modulation and demodulation.
- 52. ¡ IEEE 802.310GBASE-T study group or IEEE-P802.3an Task Force, has completed investigating the feasibility of transmission of 10 Gbps over 4 pairs of unshielded twisted pair (UTP) cables, and is developing its baseline transmission scheme ¡ In this received signal at a receiver not only suffers from signal attenuation and ISI but also suffers from echo, near-end cross talk (NEXT), far-end cross talk (FEXT), and other noises such as alien NEXT (ANEXT) ¡ To meet the desired throughput and target BER requirements, we need to perform significant amount of DSP operations in the transceivers, which include channel equalization, channel coding, and echo/NEXT/FEXT cancellation. ¡ Research focus is on high speed, low power and area-efficient implementation of various DSP blocks used in 10GBASE-T Transceiver which includes Parallel Decision Feedback Decoders, High speed Tomlinson-Harashima precoders, Interleaved trellis coded modulation and decoding, Efficient long FIR Adaptive Filter Implementation and Low Power Echo&Next Cancellers
- 54. ¡ Soft-Decision Reed-Solomon (RS) codes are of great interest in modern communications and storage systems applications ¡ Koetter-Vardy (KV) soft-decision decoding algorithm of RS codes can achieve substantial coding gain for high-rate codes, while maintaining a complexity polynomial with respect to the codeword length ¡ Present: § In the KV algorithm, the factorization step can consume a major part of the decoding latency. A novel architecture based on root-order prediction is proposed to speed up this step. As a result, the exhaustive-search-based root computation from the second iteration of the factorization step is circumvented with more than 99% probability. In addition, resource sharing among root-prediction blocks, as well as normal basis representation for finite field elements and composite field arithmetic, are exploited to reduce the silicon area significantly. § Applying the proposed fast factorization architecture to a typical (255, 239) RS code, a speedup of 141% can be achieved over the fastest prior effort, while the area consumption is reduced to 31% In the architecture of the fast factorization for the KV algorithm, the root computation and polynomial updating can be carried out simultaneously to reduce the factorization latency further. The latency and area of the polynomial updating account for more than half of the total latency and the total area of the factorization architecture, respectively. ¡ Future: § Future work will address efficient implementations of polynomial updating. There is no real hardware implementation of the entire KV algorithm so far. The only available implementation is for the interpolation step only, which uses four Xilinx Virtex2000E devices and achieves a maximum clock frequency of 23 MHz. This implementation has overwhelming complexity and runs too slow for practical applications. Current research is directed towards bringing down the complexity of the KV decoding algorithm to practical level through further algorithmic and architectural level optimizations.
- 55. ¡ Focus is on layout design, fabrication and testing of IC for demonstration of key algorithmic ideas § 4th order recursive digital filtering which uses loop pipelining and has 86MHz sample rate § Fine grain pipelined chips - 16x16-bit multiplier which makes use of internal redundant number representation, and another one for a 100 MHz ADPCM video codec § Shared divider/square-root chip § Bit-level pipelined RLS adaptive filter § Viterbi Coder chip § Shared divider/square root and CORDIC chips
- 56. ¡ High-speed algorithms for predictive coders (including differential pulse code modulation (DPCM), and adaptive DPCM), Huffman and arithmetic decoders, Viterbi decoders (which are variations of dynamic programming computations), arithmetic coders, decision feedback equalizers (DFEs), and adaptive DFEs ¡ Design of architectures for VLSI discrete wavelet transforms which require fewer number of registers using life time analysis ¡ Various approaches of implementations of DCTs ¡ Design approach to arbitrarily parallel Variable Length Coder
- 57. ¡ New architectures for arithmetic operations § Goal is to save the number of pipelining latches § Faster operation § Complex designs - multiply-adder, shared divider/square-root ¡ Arithmetic architecture design for finite field (i.e., Galois field) which can be used in error control coding applications ¡ Appropriate scheduling techniques based on a hardware- software co-design approach is also used ¡ Goal is low area, low latency and low power consumption