The document discusses CMOS fabrication processes and scaling. It covers the following key points in 3 sentences:
The fabrication process involves using a series of photolithography masks to define layers of the chip, including n-well, polysilicon, diffusion regions, contacts and metal. Scaling can involve either full scaling, which preserves electric fields, or constant voltage scaling, which leaves voltages unchanged but can increase power consumption. The document also discusses MOSFET capacitances including oxide capacitances between gate and other terminals and junction capacitances due to diffusion regions.
3. Fabrication Process
The fabrication sequence consists of a series of steps in which layers
of the chip are defined through a process called photolithography.
The inverter could be defined by a hypothetical set of six masks:
n-well, polysilicon,n+ diffusion, p+ diffusion, contacts, and metal
4.
5. 1) Si with p-type impurities
nMOS fabrication steps:
2) Thick layer of SiO2 on substrate
6. (3) Photoresist on the layer of SiO2
(4)Photoresist layer exposed to UV light through mask
19. LAYOUT DESIGN RULES
Designers often describe a process by its feature size.
Feature size refers to minimum transistor length, so LAMBDA λ
is half the feature size.
For example, a 180 nm process has a minimum polysilicon width (and hence
transistor length) of 0.18 μm and uses design rules with λ= 0.09 μm
26. CMOS TECHNOLOGIES
WAFER FORMATION
• pure silicon
• amounts of impurities
• seed crystal
• silicon ingot
• wafer or disk of silicon, 75
mm to 300 mm in diameter
and less than 1 mm thick.
27. PHOTOLITHOGRAPHY
• Is a process used in microfabrication to pattern parts on a thin film
• photomask
• photoresist
28. •The following are main CMOS technologies:
•n-well process
•p-well process
•twin-well process
•triple-well process
WELL AND CHANNEL FORMATION
33. SILICON DIOXIDE (SIO2)
l Wet oxidation––when the oxidizing atmosphere contains water vapor.
The temperature is usually between 900 °C and 1000 °C.
Also called pyrogenic oxidation when a 2:1 mixture of hydrogen and
oxygen is used.
It is used to form thick field oxides.
Wet oxidation is a rapid process.
Oxidation of silicon is achieved by heating silicon wafers in an oxidizing
atmosphere.
34. • Dry oxidation––when the oxidizing atmosphere is pure oxygen.
• Temperatures are in the region of 1200 °C to achieve an acceptable growth rate.
• Dry oxidation forms a better quality oxide than wet oxidation.
• It is used to form thin, highly controlled gate oxides.
• Atomic layer deposition (ALD)––when a thin chemical layer (material A) is
attached to a surface and then a chemical (material B) is introduced to produce a thin
layer of the required layer (i.e., SiO2––this can also be used for other various
dielectrics and metals).
• The process is then repeated and the required layer is built up layer by layer.
52. What is Scaling?
Moving VLSI designs to new fabrication processes
Shrinking the size of the circuitry
The reduction of the size, i.e., the dimensions of MOSFETs, is
commonly referred to as scaling.
MOSFET SCALING
53. Why do we Scale?
1) Improve Performance
•More complex systems
2) Increase Transistor Density
•Reduce cost per transistor & size of system
3) Reduce Power
•Smaller transistors require less supply voltage
54.
55. There are two basic types of size-reduction strategies:
full scaling (also called constant-field scaling) and
constant voltage scaling.
Both types of scaling approaches will be shown to have unique effects
upon the operating characteristics of the MOS transistor.
56. • This scaling option attempts to preserve the magnitude of
internal electric fields in the MOSFET, while the dimensions are
scaled down by a factor of S.
• To achieve this goal, potentials must be scaled down
proportionally, by the same scaling factor.
FULL SCALING ( CONSTANT FIELD SCALING)
57.
58.
59. - by scaling tox, we effect Cox :
Scaling Effect on Device Characteristics : Linear Region
- the transconductance parameter kn will also be scaled by a factor of S.
60. - The voltages VGS, VTO, and VDS also scale down by S, which creates a
1/S2 in this expression:
- which results in:
61. Scaling Effect on Device Characteristics : Saturation Region
- again, k effects IDS
- which gives
62. Scaling Effect on Device Characteristics : Power
- Static Power in the MOSFET can be described as:
- both quantities scale by 1/S
This significant reduction of the power dissipation is one of the most
attractive features of full scaling.
63. Scaling Effect on Device Characteristics : Power Density
-Power Density is defined as the power consumed per area-this is an
important quantity because it shows how much heat is generated in a
small area, which can cause reliability problems
-Power scales by 1/S2
-Area scales by 1/S2
-this means that the scaling cancels out and
the Power Density remains constant
64. CONSTANT VOLTAGE SCALING
-sometimes it is impractical to scale the voltages
-this can be due to:
1) existing I/O interface levels
2) existing platform power supplies
3) complexity of integrating multiple power supplies on chip
65. - ConstantVoltage Scaling refers to scaling the physical quantities
(W,L,tox,xj,NA) but leaving the voltages un-scaled (VT0, VGS, VDS)
-while this has some system advantages, it can lead to some unwanted
increases in MOSFET characteristics
66. Scaling Effect on Device Characteristics : Linear Region
- we’ve seen that scaling tox, W, and L causes:
- if the voltages (VGS, VT0, and VDS) aren’t scaled, then the IDS expression in
the linear region becomes:
- which results in:
IDSlin actually increases by S when we get smaller, this is NOT what we wanted!!
67. Scaling Effect on Device Characteristics : Saturation Region
- this is also true in the saturation region:
- which results in:
IDSSAT also increases by S when we get smaller,
this is NOT what we wanted!!!
68. Scaling Effect on Device Characteristics : Power
- Instantaneous Power in the MOSFET can be described as:
- but in Constant-Voltage Scaling, IDS increases by S and VDS remains
constant
Power increases by S as we get smaller,
this is not what we wanted!!!
69. Scaling Effect on Device Characteristics : Power Density
-Power Density is defined as the power consumed per area
-we’ve seen that Power increases by S in Constant-Voltage Scaling
-but area is still scaling by 1/S2
-This is a very bad thing because a lot of heat is being generated in a
small area
70. Scaling Choices
•So Which One Do We Choose?
-Full Scaling is great, but sometimes impractical.
-Constant Voltage can actually be worse from a performance standpoint
-We actually see a hybrid approach.
71. Scaling Effect on AC Performance
- Assume Full Scaling
- 1. Resistance (R)
76. MOSFET Capacitance
-the Capacitances of a MOSFET are considered parasitic
-"parasitic" means unwanted or unintentional.
They are unavoidable and a result of fabricating the devices using physical
materials.
-we can use the capacitances of the MOSFET to estimate factors such as
rise time, delay, fan-out, and propagation delay
78. MOSFET Capacitance
-We group the various capacitances into two groups
1) Oxide Capacitances-capacitance due to the Gate oxide
2) Junction Capacitances -capacitance due to the Source/Drain diffusion
regions
79. Oxide-Capacitance
-Oxide Capacitance refers to capacitance which uses the gate oxide as the
insulator between the parallel plates of the capacitor
-as a result, these capacitances always use the Gate as one of the
terminals of the capacitor
Cgb= Gate to Body Capacitance
Cgd= Gate to Drain Capacitance
Cgs= Gate to Source Capacitance
80. Overlap Capacitance
- capacitance from the Gate to the Source/Drain due to the overlap
region (LD)
- this creates:
where Cox is the unit-area capacitance
