1. 1
RF power silicon-on-glass VDMOSFET
Nebojˇsa Nenadovi´c, Student Member, IEEE, Vittorio Cuoco, Student Member, IEEE, Steven J. C. H. Theeuwen,
Hugo Schellevis, Geert Spierings, Antonio Griffo, Marco Pelk, Lis K. Nanver, Member, IEEE, Rik F. F. Jos, and
Jan W. Slotboom, Member, IEEE
Abstract— We have fabricated VDMOSFETs that are designed
for applications in future base station power amplifiers. They are
made in a substrate transfer silicon-on-glass technology. For a
gate length of 0.8 µm and gate width of 350 µm the fT /fmax is
6/10 GHz and the breakdown voltage approaches 100 V. The
devices feature excellent linearity (IM3 of -50 dBc at 10 dB
back-off) and high power gain (14 dB) at 2 GHz, and are the
first vertical DMOSFETs suitable for 2 GHz power applications.
Excellent heat sinking and no significant degradation of the
quiescent current due to hot-carrier injection ensure thermal
stability and good long-term reliability of fabricated devices.
Index Terms— RF power MOSFETs, substrate transfer, self-
heating.
I. INTRODUCTION
HIGH frequency power gain of bulk-silicon vertical dou-
ble diffused MOSFETs (VDMOSFETs) is limited due
to large gate-drain capacitance and source leads inductance
to ground. Governed by an excellent linearity performance of
VDMOSFETs, laterally diffused MOSFETs (LDMOSFETs)
were designed and fabricated [1], [2], and demonstrated to
feature high RF power gain and good linearity. Nowadays,
LDMOSFETs are state-of-the-art devices for highly linear RF
power applications [3].
To improve RF performance, the initial concept of a LD-
MOSFET has been modified to include a field-plate electrode
[4], which overlaps the gate and is connected to the source.
Such electrode reduces the fields at the edge of the gate
thus increasing the breakdown voltage, reducing feedback
capacitance and improving device linearity. Combined with
reduction of the gate area, a field-plate electrode has been
introduced within a VDMOSFET as well [5]. However, even
though gate-drain capacitance is significantly reduced, large
leads inductance from source to ground still limits the RF
gain of bulk-silicon VDMOSFETs.
Future generations of highly integrated wireless systems ask
for new RF power device concepts. Implementation of a LD-
MOSFET in thin-film SOI was demonstrated to be a promising
technology to meet such demands [6]. Nevertheless, in both
bulk and especially SOI device realization, inefficient heat re-
moval from the active device regions degrades carrier mobility
and negatively affects device RF performance [7]. Recently
N. Nenadovi´c (contact author), V. Cuoco, H. Schellevis, A. Griffo, M. Pelk,
L. K. Nanver and J. W. Slotboom are with Laboratory of ECTM, DIMES,
Delft University of Technology, Feldmannweg 17, P.O. BOX 5053, 2600 GB
Delft, The Netherlands. Tel. +31-15-2782185, fax. +31-15-2622163, E-mail:
n.nenadovic@dimes.tudelft.nl.
J. W. Slotboom is also with Philips Research Laboratories, Prof. Holstlaan
4, 5656 AA Eindhoven, The Netherlands.
S. J. C. H. Theeuwen, G. Spierings and R. Jos are with Philips Semicon-
ductors - RF Modules, Gerstweg 2, 6534 AE Nijmegen, The Netherlands.
developed substrate transfer technology [8] opens possibilities
to solve heat transport related problems. Moreover, it allows
a complete freedom of substrate choice which can result in
elimination of substrate losses implying integration of even
better passives, and further reduction in cross-talk and power
consumption. Besides, substrate transfer technology opens the
way for other technological advances like back-wafer low-
ohmic contacting [9] and 3D integrated circuit fabrication [10].
The above mentioned device and technology concepts (i.e.
substrate transfer, back-wafer low-ohmic contacting and usage
of a field-plate electrode) are combined in this work to design
and fabricate VDMOSFETs very attractive for 3G wireless
applications. This paper describes the first VDMOSFETs
fabricated in substrate transfer silicon-on-glass technology.
II. DEVICE DESIGN AND FABRICATION
A schematic of the process flow is shown in Fig. 1. The
substrate transfer technology divides the processing into first a
conventional front-wafer silicon processing on the SOI starting
material, second the wafer transfer to glass by gluing with
removal of the bulk silicon to the buried oxide, and lastly the
back-wafer processing at temperatures below 300◦
C.
In the front-wafer processing here, a production RF LDMOS
process at Philips Semiconductors has been modified to realize
the source, gate and drain epi-profile of the VDMOS structure.
The n-profile of the drain is formed by growing an n-epi
followed by a blanket implantation and high temperature
diffusion. The modified 0.8-µm LDMOS processing includes
p+
-sinker source and gate implantation/diffusion, a 40 nm-
thick thermal gate oxidation, poly-Si field-plate and gate
electrode formation with self-aligned p-well and n+
-source
implantation/diffusion, and Al on TiN metallization.
The substrate transfer to glass and the bulk Si removal to the
buried oxide by TMAH etching follows. The substrate transfer
is also a Philips production process but is run at DIMES with
several enhancements: the back-wafer is patterned with the
same high-precision lithography as the front-wafer and low
ohmic n- and p-type contacts are formed by implanting and
laser annealing 5 keV As+
and B+
, respectively, and metal-
lization with sputtered Al/Si. The gate p+
-plugs are isolated
by trench etching from the back-wafer to the front-wafer oxide
isolation. The trenches are then filled with BCB and etched
back till Al/Si. The processing continues with electro-plating
of a two level thick copper interconnect on the back-wafer
with Ti/TiN diffusion and adhesion barrier. Electro-plated Cu
is covered with BCB before the devices can be soldered
to a PCB. The first 4 µm-thick copper layer on the drain
minimizes debiasing over long drain fingers, and the second

2. 2
source
Si substrate
source
(a) modified bulk silicon LDMOS processing on SOI starting material
(b) gluing to glass and bulk-Si removal
(c1) laser annealed back-wafer contacts, deep trenches
(c2) two level electro-plated copper covered with BCB, mounting to PCB
BCB
PCB
oxide
source
Cu Cu Cu
source gatedrain
oxide
p++ p++n++ p++
source source gatedrain
trench
glue
glass
oxide
p-well p-well
oxide
n+ p+ enhanc.n+p+ enhanc.
n-epi
oxide
p++
p+ sinker p+ sinker
field-plate
gates
d2
d3
d1
p+ sinker
polypoly
source source
p-well p-well
n+n+
n-epi
gates
polypoly
glue
glass
source source
n-epi
p+ sinker p+ sinker p+ sinker
Cu
p++ p++ p++
glue
glass
source source
n-epi
polypoly
n++
field-plate
Fig. 1. Schematic of VDMOSFET on glass process flow: (a) front-wafer
processing, (b) substrate transfer and (c) back-wafer processing.
4+4 µm-thick layer to the source contacts improves thermal
conductance to the thermal ground. In contrast to conventional
bulk-silicon VDMOSFETs, the back-wafer contacting along
with copper electro-plating allow the elimination of the source
leads inductance to ground by forming a common thermal and
electrical ground. A SEM image of a single-cell device after
the two level copper electro-plating is given in Fig. 2.
III. RESULTS AND DISCUSSION
In the development of the present VDMOS structure, several
device layouts and process flows, based on a 0.8 µm RF-
LDMOS technology, were considered and thoroughly analyzed
by means of process, device and RF-performance simulations
[11], [12]. The first fully processed VDMOS devices that are
measured here have a gate-to-drain distance d1=5.6 µm, a
n-epi thickness d2=3.5 µm and a distance between the gate
DRAIN
4 m Cum
GATE
SOURCE
3.5 m TRENCH filled with BCB
m
SOURCE
4+4 m Cum
Fig. 2. SEM image of two levels of copper electro-plated on the back-wafer
of silicon-on-glass VDMOST. Gate width is Wg=70 µm.
and field-plate electrode d3=1 µm, where all the distances are
specified in Fig. 1(c2). We focus on measurements done on a
single-cell GSG devices suitable for RF characterization, such
as those shown in Fig. 2 having the gate width Wg=350 µm.
Fig. 3(a) displays measured output characteristics and off-state
breakdown voltage BVoff of nearly 100 V. Pulsed small signal
s-parameters of the devices were measured versus frequency
upto 11 GHz, and fT and fmax (Fig. 3(b)) were extracted
from 20 dB/dec current gain and maximum available gain
(k < 1) characteristics, respectively. The measured values are
fT /fmax=5/8 GHz for VDS=25 V and fT /fmax=6/10 GHz for
VDS=45 V. Furthermore, pulsed s-parameters were measured
versus bias and used as input for the powerful Smoothie
database model for FET devices, proven to yield very accurate
prediction of RF performance [13]. Load-pull simulations at
2 GHz yields, in class-AB bias conditions, a two-tone power
gain as high as 14 dB, IM3 lower than -50 dBc at 10 dB
back-off and very low IM5 (Fig. 4). The same production line
bulk-Si RF-LDMOSFETs, show two-tone power gain of 15 dB
and IM3 of -40 dBc at 10 dB back-off.
Silicon-on-glass VDMOSFETs experience no significant
degradation of the quiescent current Idq even though no
additional efforts were made to engineer the drain profile.
Measurements on the fabricated devices indicate degradation
of less than 10% in 20 years, which is very good for such RF
performance and is much better compared to the same produc-
tion line LDMOSFETs. Furthermore, temperature distributions
shown in Fig. 5, numerically calculated for large, high power
devices, predict that a silicon-on-glass VDMOSFET, when sol-
dered to a thermally conducting substrate, features much lower
temperature increase than the bulk silicon device soldered to
the same substrate. This is due to the much closer proximity of
the heat sink to the active device regions achieved by substrate
transfer.
IV. CONCLUSIONS
The fabricated silicon-on-glass VDMOSFETs demonstrate
highly linear characteristics that are attractive for many
wireless power applications. They feature an fT /fmax of
6 GHz/10 GHz, high power gain at 2 GHz, very good thermal
stability and long-term reliability. These are the first VDMOS-
FETs featuring excellent RF characteristics being suitable for
3G applications.

3. 3
0
2
4
6
8
10
12
14
0 10 20 30 40 50 60 70 80 90
ID[mA]
V
DV =0.1VGS
DS [V]
10
-10
10
-8
10
-6
10
-4
10
-14
10
-12
0 20 40 60 80 100
V
GS
=0V
(a)
0
2
4
6
8
10
12
10
-1
fT[GHz]
I
fT
V =45VDS
fmax
D [mA]
10
0
10
1
10
2
,fmax
V =25VDS
(b)
Fig. 3. Measured (a) off-state breakdown voltage and pulsed output
characteristics, and (b) current dependence of fT and fmax.
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pp. 635–638.
12
12.5
13
13.5
14
14.5
15
15.5
-10 -5 0 5 10 15 20
Gain[dB]
P
I =dq 2.1 mA
1dB
out
[dBm]
freq. = 2 GHz
Df = 200 kHz
V = 26 VDD
-80
-60
-40
-20
0
IMD[dBc]
10 dB
IM3
IM5
Fig. 4. Two-tone transducer gain and third- and fifth-order intermodulation
distortion versus output power.
gate
source
312.0
311.75
311.5
311.25
311.0
310.75
310.5
312.0
302.6
302.8
SILICON
10
0
-10
-20
-30
-40
-50
315
310
305
300
Tmax
50-5-10-15 1510
(a)
gate
303.6
302.4
302.6
source
glass
field
plate
drain
302.2
302.0
302.6
302.8 302.8
BCB
Cu
Cu
SILICON
10
0
-10
-20
-30
-40
-50
315
310
305
300
Tmax
50-5-10-15 1510
thermally conducting substrate
(b)
Fig. 5. Simulated temperature profile along the cross section of high-power
(a) bulk and (b) silicon-on-glass device at VDS=25 V and IDS=3.5 µA/µm.
Silicon substrate thickness in (a) is set to 300 µm, while the thickness
of a thermally conducting substrate in both (a) and (b) is set to 200 µm.
The ambient temperature and temperature of the heat sink below thermally
conducting substrate is made 300 K.