Sequential logic circuits use a clock signal to control the timing of state changes in memory elements like flip-flops. A master-slave JK flip-flop allows both the J and K inputs to be simultaneously 1, toggling the output. When this occurs, the master section is reset if the clock is 1, and set if the clock is 0, preventing unstable oscillations between circuits.

3. Flip-Flops
• The latch circuits presented thus far are not appropriate
for use in synchronous sequential logic circuits.
• The possibility of two cascaded combinational circuits
feeding each other, generating oscillations and unstable
transient behavior can be controlled by using a special
timing control signal called a clock.
• The clock can then be used to restrict the times at which
the states of the memory elements may change thus
preventing the unstable behavior just described.

4. Clock Signal
Sequential logic circuits have memory
Output is a function of input and present state
Sequential circuits are synchronized by a periodic “clock” signal

5. Master-Slave JK Flip-Flop
• The output state of a master-slave SR flip-flop
is undefined upon returning the control input
to 0 when S = R = 1.
– Necessary to avoid this condition.
• Master-slave JK flip-flop allows its two
information input lines to be simultaneously
1.
– Results in toggling the output of the flip flop.

6. Master-Slave JK Flip-Flop
• Assume in 1-state, C = 0, J = K = 1.
– Due to feedback, the output of the J-gate is 0, output of K-gate is 1.
– If clock is changed to C = 1 then master is reset.
• Assume in 0-state, C = 0, J = K = 1.
– Due to feedback, the output of the J-gate is 1, output of K-gate is 0.
– If clock is changed to C = 1 then master is set.
• 1 on J input line, 0 on K input line sets the flip-flop.
– If in 1-state, unchanged b/c S,R set to 0.
– If in 0-state, S set to 1, R set to 0.
• 0 on J input, 1 on K input line resets the flip-flop. Why?

7. Master-Slave JK Flip-Flop

8. Timing Diagram for
Master-Slave JK Flip-Flop

9. T (toggle) Flip-flop
• It’s a complementing flip-flop
• It can be made using JK flip-flop or D flip-
flop.
• If made using JK flip-flop
– Inputs J & K are tied together
– T=0, J=K=0, No Change in Q
– T=1, J=K=1, Q = Q’
• If made using D flip-flop
– Q = D = T XOR Q = TQ’ + T’Q