3. Course Objectives
目標
Digital Logic Basic Concept
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● Understanding of FPGA/CPLD device
● Verilog HDL Simulation and Verification by ModelSim
● Verilog HDL for synthesis
● Altera design flow in Quartus
● Design a project with 『 GFEC MAX II Starter Kit 』
6. Tools: What we need
Windows PC
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Verilog HDL Simulator:
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Modelsim, to compile and execute HDL for
simulation, debugging, verification
Device/Board: GFEC MAX II Starter Kit, IO Board
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Synthesizer/Fitter/Porgrammer: Quartus/Altera
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