Lab1:
 Modelsim Setup and Hello World
  1. Make Sure your “Modelsim-Altera” ready
  2. Go through a tutorial example for R...
Lab1:
    Basic Simulation Flow
ModelSim:
a verification and simulation t
ool for
● VHDL,

● Verilog,

● SystemVerilog,

●...
ModelSim RTL simulation


   1. Create libraries.
   2. Map to libraries.
   3. Compile source code and testbenches.
   4....
Start ModelSim

    Verilog: Copy counter.v and tcounter.v file
●

    s from
    /<install_dir>/examples/tutorials/verilo...
Change Folder

    Select File > Change Direc
●

    tory and change to
    the directory you
    created.


    C:Altera6...
Create the working library.
             Select File > New > Library.
             OK
             dir work, file 『 _info ...
Create the working library.


   Transcript window
Compile the design

1. Select
   Compile > Compile
2. Select both counter.
   v tcounter.v modules
3. Compile, Done
View the compiled design units

    Library window
●
    click the ’+’ icon
●
    next to the work lib
    rary
Load Design
    Select Simulate -> Start Simulation
●
    OK
●
    ModelSim> vsim -t ns work.test_counter
●
Structure window
 (labeled sim) that displays the
hierarchical structure of the design in simulation
Process and Object Window
Run the Simulation

    Select View > Wave
●
    or > view wave
    Resize or Move 『 Window 』 by mouse
●
    right-click t...
Run the Simulation
    Click Run Icon
●
    Run up to 100 ns
●
    VSIM> run 500
●
    Run -All
●
    Simulate ->Break
●
Waveform Display, Zoom-In Out
Breakpoints and Step




Open source file
Breakpoint set, hit
Goto line 36
Double click

Right click

Restart the simulation
Click Reset
Click Run -all
Check Transc...
Step Run


  Step
  Step over
  Run


  Simulate -> End Simulation
Where to get on-line help?
Appendix
Lab1: design Hierachical
LM_LICENSE_FILE
Lab1:
 ModelSim-Altera License File in Vista
Day1 Lab1
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Day1 Lab1

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Day1 Lab1

  1. 1. Lab1: Modelsim Setup and Hello World 1. Make Sure your “Modelsim-Altera” ready 2. Go through a tutorial example for RTL simulati on with ModelSim 1. quartus_install.pdf, www.altera.com 2. oem_tutor.pdf, ModelSim Tutorial
  2. 2. Lab1: Basic Simulation Flow ModelSim: a verification and simulation t ool for ● VHDL, ● Verilog, ● SystemVerilog, ● SystemC, and mixed-language designs.
  3. 3. ModelSim RTL simulation 1. Create libraries. 2. Map to libraries. 3. Compile source code and testbenches. 4. Load the design. 5. Add design stimulus. 6. View the simulation results. 7. Advance the simulator You already had practiced it at Lab1.
  4. 4. Start ModelSim Verilog: Copy counter.v and tcounter.v file ● s from /<install_dir>/examples/tutorials/verilog/basi cSimulation to the new directory. Start ModelSim ● Click from your Desktop
  5. 5. Change Folder Select File > Change Direc ● tory and change to the directory you created. C:Altera61 C:AlterapjtLab1
  6. 6. Create the working library. Select File > New > Library. OK dir work, file 『 _info 』 Library Window modelsim.ini
  7. 7. Create the working library. Transcript window
  8. 8. Compile the design 1. Select Compile > Compile 2. Select both counter. v tcounter.v modules 3. Compile, Done
  9. 9. View the compiled design units Library window ● click the ’+’ icon ● next to the work lib rary
  10. 10. Load Design Select Simulate -> Start Simulation ● OK ● ModelSim> vsim -t ns work.test_counter ●
  11. 11. Structure window (labeled sim) that displays the hierarchical structure of the design in simulation
  12. 12. Process and Object Window
  13. 13. Run the Simulation Select View > Wave ● or > view wave Resize or Move 『 Window 』 by mouse ● right-click test_counter to open a popup co ● ntext menu. Select Add > To Wave
  14. 14. Run the Simulation Click Run Icon ● Run up to 100 ns ● VSIM> run 500 ● Run -All ● Simulate ->Break ●
  15. 15. Waveform Display, Zoom-In Out
  16. 16. Breakpoints and Step Open source file
  17. 17. Breakpoint set, hit Goto line 36 Double click Right click Restart the simulation Click Reset Click Run -all Check Transcript and source Window examine data
  18. 18. Step Run Step Step over Run Simulate -> End Simulation
  19. 19. Where to get on-line help?
  20. 20. Appendix
  21. 21. Lab1: design Hierachical
  22. 22. LM_LICENSE_FILE
  23. 23. Lab1: ModelSim-Altera License File in Vista

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