1. ModelSim OverView

2. What we already learned
Verilog can model: behavioral, RTL structure
●
Module: basic unit in Verilog
●
A tutorial: Module instantiation, stimulus, respone
●
Procedure block: initial, always
●

3. ModelSim RTL simulation
1. Create libraries.
2. Map to libraries.
3. Compile source code and testbenches.
4. Load the design.
5. Add design stimulus.
6. View the simulation results.
7. Advance the simulator

4. ModelSim Tutorial
ModelSim Tool OverView

5. ModelSim Flow 1
2
3
Link
4
5

6. Vlog order independent

7. ModelSim use mode

8. Command Mode

9. Batch Run

10. ModelSim Tutorial
Projects

11. ModelSim: New Project
File > New > Project

− *.mpf

12. Add Existing File
HDL files 路徑名稱不能有中文

13. Add Existing File

14. File > Add to Project

15. Compile
Mouse
right click

16. Load Design
Mouse
double
Click
Simulate > End Simulation.

17. OPEN CLOSE A PROJECT
FILE > OPEN


FILE > CLOSE


18. ModelSim Tutorial
Projects Folder

19. Add Folder
File > Add to Project > Folder.


20. Add a sub folder
File > Add to Project > Folder.


21. Move Files to folder HDL
NOTE:
NO actual directories created
in the file system.

22. ModelSim Tutorial
Simulation Configuration

23. Simulation Configuration
File > Add to Project > Simulation Configuration.


24. Loading

25. ModelSim Tutorial
Project Setting

26. Right Click > Properties...

27. Project Setting

28. ModelSim Tutorial
Waveform Display

29. Waveform Window

30. Add wave
View wave

 Add wave *
 OR
VIEW > DEBUG WINDOWS > WAVE

31. Add signals to waveform
Or, Mouse Drag-and-Drop

32. Zoom-in 2X Zoom-in Full
2X Zoom-out

33. Cursor in Wave Window

34. Rename the Cursor
Mouse Right Click

A

35. Add Cursor
Click

 Rename
Cursor2 to
B
 Drag B
to measure
the Delta

36. Cursor
CURSOR HERE

38. Window Undock & Dock

39. Tools > Combine Signal

40. Save Waveform Format: File > Save
File > Load
Select wave.do

42. ModelSim Tutorial
SDF

43. SDF
SDF versions 1.0 through 4.0

 vsim
-sdfmin [<instance>=]<filename>
-sdftyp [<instance>=]<filename>
-sdfmax [<instance>=]<filename>
 Ex
vsim -sdfmax /testbench/u1=myasic.sdf testbench
 Or
Simulate > Start Simulation
> SDF

44. $sdf_annotate system task
$sdf_annotate ([quot;<sdffile>quot;], [<instance>],

[quot;<config_file>quot;], [quot;<log_file>quot;], [quot;<mtm_spec>quot;],
[quot;<scale_factor>quot;], [quot;<scale_type>quot;]);
 Ex
$sdf_annotate(quot;myasic.sdfquot;, testbench.u1);
$sdf_annotate(quot;myasic.sdfquot;, testbench.u1, , ,
quot;maximumquot;);


45. The SDF TIMESCALE construct specifies time

units of values in the SDF file. The annotator
rounds timing values from the SDF file to the time
precision of the module that is annotated. For
example, if the SDF TIMESCALE is 1ns and a
value of .016 is annotated to a path delay in a
module having a time precision of 10ps (from the
timescale directive), then the path delay receives
a value of 20ps. The SDF value of 16ps is
rounded to 20ps. Interconnect delays are rounded
to the time precision of the module that contains
the annotated MIPD.

46. ModelSim Tutorial
Library

47. Appendix