Day4




Sync. Counter Design
LAB: Sync Counter

                                    LED
                SW1
                      m10 counter
         ...
除頻器 Frequency Divider, clk_gen.v
        cnt[23:0]                                     1sec

                             ...
7-seg Display, bin2seg.v

                    clk_ms      dig4, dig3, dig2, dig1
                                         ...
Quartus: RTL Viewer
 Tools > Netlist Viewer > RTL Viewer
同部設計 Syncrounous clock design


                       CLOCK SKEW




利用 Alteara Device 之 Global Clock
Assign Clock
LAB: Sync Counter


    Sample Code
  ●
  ● 00 ~ 99 計數
  ●

      可預設
  ●

      DIP[8:5] 十位
      DIP[4:1] 個位
Day4




TIMER
Timer




 one-shot
Timer Delay
Debouncer




       LAB3
LAB: Timer Delay


                          Delay Timer
                          時間可設定


                               ...
LAB: Timer Delay


         1. 按鍵 RELEASE 偵測
         2. TIMER 設定 最大值限制
Day4




EVENT COUNTER
LAB: PLC Counter + LED Display

SW1: RESET


SW2: INC

                           Counter
                           設定值
 ...
LAB:
 PLC Counter + LED Display

                                        LED
             SW1: reset
             SW2: inc...
LAB: PLC Counter + LED Dis-
 play

          1. 由初值往下減
          2. LED 動作反相
Day4



FSM
Finite State Machine
FSM

                                 有限狀態
   X

                                 輸入
   reset      FSM
           { q1, q0...
FSM State Diagram

                    state
Mealy machine
                            input


                           ...
Clock Syncronous FSM

                       Mealy




                        Moore
always @(state or x1)
                                          begin
     FSM: HDL Coding                         case (s...
LAB: fsm

    SW1: reset
●
    SW2: start
●
    DIP1: a0
●
    DIP2: a1
●
    LED1: FWD
●
    LED2: BWD
●
    7-seg: state...
LAB: fsm2

    Copy your project
●


    SW1: reset
●
    SW2: start
●
    DIP1: a0
●
    DIP2: a1
●
    LED1: FWD
●
    L...
LAB: fsm3

    Copy your project
●


    SW1: reset
●
    SW2: start
●
    DIP1: a0
●
    DIP2: a1
●
    LED1: FWD
●
    L...
狀態機編碼 (ENCODING)

Assignments > Setting
State Machine Viewer

Tools > NetlistViewer > StateMachineViewer
LAB: FSM


           1. fsm3 加入 一個 DELAY
           2. 兩個 DELAY
BACK UP
LAB: ledtest 跑馬燈




      Ref p.18, MAX II_SG_V2.pdf
  ●
LAB: ledtest 跑馬燈


         1. 變慢
         2.
Day4 Lab
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Day4 Lab

  1. 1. Day4 Sync. Counter Design
  2. 2. LAB: Sync Counter LED SW1 m10 counter D1 7-seg 以秒為單位 之 0 ~ 9 counter 7-seg Display
  3. 3. 除頻器 Frequency Divider, clk_gen.v cnt[23:0] 1sec cnt23=clk_sec 0 ~ 16M 16Mhz (24'hF42400) cnt23=clk_ms 1.024ms +1 16Mhz Not 50-50% duty =16000000
  4. 4. 7-seg Display, bin2seg.v clk_ms dig4, dig3, dig2, dig1 dig[4:1] 0001 0~9 clk_sec digit1 7-seg digit2 decoder seven_seg[7 bin digit3 digit4 Quaratus II, CODE 已修改過
  5. 5. Quartus: RTL Viewer Tools > Netlist Viewer > RTL Viewer
  6. 6. 同部設計 Syncrounous clock design CLOCK SKEW 利用 Alteara Device 之 Global Clock
  7. 7. Assign Clock
  8. 8. LAB: Sync Counter Sample Code ● ● 00 ~ 99 計數 ● 可預設 ● DIP[8:5] 十位 DIP[4:1] 個位
  9. 9. Day4 TIMER
  10. 10. Timer one-shot
  11. 11. Timer Delay
  12. 12. Debouncer LAB3
  13. 13. LAB: Timer Delay Delay Timer 時間可設定 LED SW1: reset SW2: start D1 timerdelay DIP 7-seg
  14. 14. LAB: Timer Delay 1. 按鍵 RELEASE 偵測 2. TIMER 設定 最大值限制
  15. 15. Day4 EVENT COUNTER
  16. 16. LAB: PLC Counter + LED Display SW1: RESET SW2: INC Counter 設定值 DIP[8:1] LED D1
  17. 17. LAB: PLC Counter + LED Display LED SW1: reset SW2: inc plc counter D1 DIP 7-seg
  18. 18. LAB: PLC Counter + LED Dis- play 1. 由初值往下減 2. LED 動作反相
  19. 19. Day4 FSM Finite State Machine
  20. 20. FSM 有限狀態 X 輸入 reset FSM { q1, q0 } Output 輸出 ( 動作 ) CLK reset State Diagram
  21. 21. FSM State Diagram state Mealy machine input state output output input Moore machine.
  22. 22. Clock Syncronous FSM Mealy Moore
  23. 23. always @(state or x1) begin FSM: HDL Coding case (state) s1: if (x1==1'b1) next_state = s2; else next_state = s3; module fsm (clk, reset, x1, outp); s2: next_state = s4; input clk, reset, x1; s3: next_state = s4; output outp; s4: next_state = s1; reg outp; endcase reg [1:0] state, next_state; end parameter s1 = 2'b00; parameter s2 = 2'b01; parameter s3 = 2'b10; always @(state) parameter s4 = 2'b11; begin always @(posedge clk or posedge reset) case (state) begin s1: outp = if (reset) 1'b1; state = s1; s2: outp = else 1'b1; state = next_state; s3: outp = end 1'b0; s4: outp = 1'b0; endcase end endmodule
  24. 24. LAB: fsm SW1: reset ● SW2: start ● DIP1: a0 ● DIP2: a1 ● LED1: FWD ● LED2: BWD ● 7-seg: state ●
  25. 25. LAB: fsm2 Copy your project ● SW1: reset ● SW2: start ● DIP1: a0 ● DIP2: a1 ● LED1: FWD ● LED2: BWD ● 7-seg: state, timer ●
  26. 26. LAB: fsm3 Copy your project ● SW1: reset ● SW2: start ● DIP1: a0 ● DIP2: a1 ● LED1: FWD ● LED2: BWD ● 7-seg: state, ● loop_count
  27. 27. 狀態機編碼 (ENCODING) Assignments > Setting
  28. 28. State Machine Viewer Tools > NetlistViewer > StateMachineViewer
  29. 29. LAB: FSM 1. fsm3 加入 一個 DELAY 2. 兩個 DELAY
  30. 30. BACK UP
  31. 31. LAB: ledtest 跑馬燈 Ref p.18, MAX II_SG_V2.pdf ●
  32. 32. LAB: ledtest 跑馬燈 1. 變慢 2.

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