The document outlines the topics to be covered on Day 2 of training which includes a review of electronic design and Boolean logic, an introduction to FPGA/CPLD devices, a Verilog HDL tutorial and running ModelSim, tools installation, and a Q&A session on using FPGA/CPLD. The day will also cover logic circuits, Verilog HDL basics for combinational logic, and a hands-on lab using ModelSim that is over 50% of the time. Resources on logic design from Altera and a note page from GFEC in traditional Chinese are also listed.

1. Day2 Open
Review
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● Review of Electronic Design
Boolean Logic and Logic Design
● FPGA/CPLD Device Introduction
● HDL Tutorial, ModelSim Running
● Tools Installation( MAX II_SG_V2.pdf 附錄 C Windows
XP/2000 下安裝 Download cable……100)
● Q&A: Usage of FPGA/CPLD
Day2 Topics
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● Logic Circuits
● Verilog HDL Basic, Combinational Logic
● Lab: > 50%, Hands-on
ModelSim GUI

2. ALTERA 中文參考書籍 茂綸股份有限公司
http://www.gfec.com.tw/note.php?language_page=big5
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