3. Register Power Up Value, Reset
P7-31, Quartus II Version 6.1 Handbook Volume 1: Design & Synthesis
Registers in the device core always power up to a low (0)
logic level on all Altera devices............
Designers typically use an explicit reset signal for the de-
sign, which forces all registers into their appropriate val-
ues after reset but not necessarily at power-up. You can
create your design such that the asynchronous reset al-
lows the board to operate in a safe condition and then
you can bring up the design with the reset active. This is
a good practice so you do not depend on the power-up
conditions of the device.
