Introduction to VHDL (Very High Speed Integrated Circuits Hardware description Language )

1. VHDL Introduction
Eng.M.Atef.Elhusainy
Design and Simulation of
Electronic circuits
Lecture 02
Elc-sim-lec02

2. 1. Introduction To VHDL
• VHDL : Very High-Speed Integrated Circuit Hardware Description Language
• VHDL is primarily used to describe hardware
• VHDL is a concurrent language.
• VHDL instructions are all executed at the same time (concurrently), regardless of
the size of your implementation
– higher-level computer languages are used to describe algorithms (sequential execution)
– VHDL is used to describe hardware (parallel execution)
• VHDL will provide you with the tools to model digital circuits in a much more
intelligent manner.
• A Field Programmable Gate Array (FPGA) is probably the most common device that
you can use for your VHDL implementations
Elc-sim-lec02
Eng.M.Atef.Elhusainy

3. 2. VHDL Invariants
There are several features of VHDL that you should know before moving
forward
 VHDL is not case sensitive This means that the two statements shown
have the exact same meaning Keep in mind that the shown example
of VHDL case sensitivity is not good VHDL coding practices.
 VHDL is not sensitive to white space (spaces and tabs) The two
statements shown have the exact same meaning.
 Comments in VHDL begin with the symbol “--”
Elc-sim-lec02
Eng.M.Atef.Elhusainy

4. Similar to other algorithmic programming languages,
 every VHDL statement is terminated with a semicolon ;
• Every if statement has a corresponding then component
• Each if statement is terminated with an end if;
• If you need to use an else if construct, the VHDL version is elsif
• Each case statement is terminated with an end case;
• Each loop statement has a corresponding end loop;
• An identifier refers to the name given to various items in VHDL
• Examples of identifiers in VHDL include variable names, signal names and port
names
• Identifiers should be self-describing
• Identifiers can be as long as you want
• Identifiers can only contain a combination of letters (A-Z and a-z), digits (0-9) and
the underscore character (“_”).
• Identifiers must start with an alphabetic character.
• Identifiers must not end with an underscore and must never have two consecutive
underscores.
Elc-sim-lec02
Eng.M.Atef.Elhusainy

5. Invalid identifiervalid identifier
• There is a list of words that have been assigned special meaning by the VHDL language
Elc-sim-lec02
Eng.M.Atef.Elhusainy

6. 3. VHDL Design Units
• help you to minimize the time of coding
• The VHDL entity construct provides a method to abstract the
functionality of a circuit description to a higher level.
• It provides a simple wrapper for the lower-level circuitry.
• This wrapper effectively describes how the black box interfaces with
the outside world
• Each port name is unique
• The VHDL compiler allows several port names to be included on a
single line. Port names are separated by commas
Elc-sim-lec02
Eng.M.Atef.Elhusainy

7. • The architecture describes what the circuit actually does
• There can be any number of equivalent architectures describing a
single entity
• An architecture can be written by means of three modeling
 data-flow model
 behavioral model
 structural model
 hybrid models
Elc-sim-lec02
Eng.M.Atef.Elhusainy

8. • The signal type is the software representation of a wire
• The variable type, like in C or Java, is used to store local information
• The constant is like a variable object type, but it cannot be changed
• when you want to assign a new value to an object of type signal you use the
operator “<=”
• assign a new value to an object of type variable you will use the operator“ := ”
Elc-sim-lec02
Eng.M.Atef.Elhusainy