Abstract: Hardware accelerators are an effective solution to increase the performance of algorithms in a wide array of disciplines, from data science to computational finance. However, data scientists and mathematicians often do not have the required knowledge or time to fully exploit these accelerators, and they perceive them as difficult and frustrating to use. OpenCL was created to simplify the creation of computational pipelines with heterogeneous hardware, but as of today its integration with high level languages commonly used in data science is limited. In this paper, we propose a framework to integrate OpenCL kernels running on FPGAs with Python, R and MATLAB, the most common languages used in data science. Our framework can automatically generate all the interfaces needed to wrap an OpenCL kernel into these high level languages, and provide the user with a transparent access to the kernel itself.

1. FIDA: a framework to automatically
integrate FPGA kernels within
Data-Science applications
Luca Stornaiuolo
Dipartimento di Elettronica Informazione e Bioingegneria (DEIB)
luca.stornaiuolo@polimi.it
Alberto Parravicini, Donatella Sciuto and Marco Santambrogio
05/21/2018

2. 2
Context Definition
Huge amount of data that need to be processed
to get aggregated information
Machine Learning
(e.g. Neural Network)
Data Mining
(e.g. K-means)
Image Analysis
(e.g. Vessel segmentation)
Signal Processing
(e.g. Autocorrelation)

3. 3
Problem Definition
• Most computational pipelines rely on high-level
languages like Python, R and MATLAB.
• These pipelines can be accelerated with OpenCL and
FPGAs.
• Integrating OpenCL kernels with high-level languages
is slow and error-prone.
FPGA

4. 4
Proposed Solution
• Integrating OpenCL kernels with high-level languages
is slow and error-prone.
• FIDA automatize this process!
From a simple description of the kernel, we
create interfaces for Python, R and MATLAB.
FPGA

5. 5
From this…

6. 6
…to this!

7. 7
Architecture
Input FIFO
Output FIFO
Boost
Rcpp
MEX
Unified
FIFO Interface
OpenCL
Host File
FPGA
Kernel
PCIe
Named
Pipes

8. 8
Experimental Results
• We tested our architecture on different
computational kernels.
• We profiled executions to find where
bottlenecks are.
• We analyzed introduced execution time
overheads.

9. 9
Experimental Results
• Execution profile:

10. 10
Experimental Results
• Execution profile:
• Most of the time is spent in interprocess communication:
shared memory could drastically improve performance!

11. FIDA: a framework to automatically integrate
FPGA kernels within Data-Science applications
Luca Stornaiuolo
Dipartimento di Elettronica Informazione e Bioingegneria (DEIB)
luca.stornaiuolo@polimi.it
Alberto Parravicini, Donatella Sciuto and Marco Santambrogio
05/21/2018
https://necst.it/
https://www.slideshare.net/necstlab
https://www.facebook.com/groups/ReconfigurableArchitecturesWorkshop/