Gopimanohar Prathipati is seeking a challenging position in VLSI ASIC verification. He has a B.Tech in Electronics and Communication from Chebrolu Engineering College with over 70% aggregate. He has experience verifying RTL designs using SystemVerilog and UVM methodologies. Some of his project experience includes verifying an SPI Master core with APB interface and an up-down counter. He also has experience developing GSM software for implementing traffic control for ambulances.

1. Gopimanohar Prathipati mobile no: +91 9441428584
Mailid:prathipatigopi434@gmail.com
Career Object:
I am seeking a challenging position with a progressive organization that will allow me to exhibit
my commitment to excellence in the field of VLSI (ASIC Verification).
ACADEMIC PROFILE:
Degree Discipline
Institute
University
Year of
Passing Aggregate
Certificate
courses
VLSI (Design and
Verification)
MosChip Institute of
silicon systems (ISS)
Hyderabad
11th
July
2019
B.Tech
Electronics &
Communication
Chebrolu
Engineering College
(Affiliated from
JNTUK) 2018 71.3 %
12th MPC
Sri Chaitanya Jr.
Kalasala affiliated to
Board of
Intermediate
Education, A.P 2014 70.40%
10th SSC
Vidya kendramn
high School. 2012 5.8 GPA
Knowledge on Technical Competency:
• Good knowledge of Digital Design Concepts, implementing the RTL using verilog.
• Good knowledge in System Verilog concepts, implementing the testbench using UVM.
• Good debugging skills.
• Good understanding of MOS fundamentals.
• Good knowledge of Core JAVA
• Basic knowledge of Linux and C programming.
• Basic knowledge in C# (Sharp) Programme.
PROJECT -1 : SPI Master core Verification with APB interface
HVL : System Verilog
TB Methodology : UVM
EDA Tools : Cadence INCISIVE 15.2 Version(NCsim, simvision)

2. Description: The SPI provides the interfacing between Master and Slave. It is responsible for
buffering address, control and data from the Master and converting the data to a serial form and
send to the slave. And slave will send the data in the form of serial it has to convert back to
parallel. At a time only one slave can be selected.
Responsibilities:
➢ Created the verification plan.
➢ Architected the class based verification environment using UVM
➢ Verified the RTL model using UVM.
PROJECT -2 :UP-DOWN COUNTER
HVL : System Verilog
TB Methodology : System Verilog
EDA Tools : Cadence INCISIVE 15.2 Version(NCsim, simvision)
Description: The design consists of four internal registers, the output has certain output format
based on internal registers values.
Responsibilities:
➢ Implemented the design using Verilog.
➢ Created the verification plan.
➢ Architected the class based verification environment using system verilog
➢ Verified the RTL model using system verilog.
PROJECT -3 : Traffic controlling System for Ambulance through GSM
Role : Developing the GSM Programme for Hardware then Implementation.
Organization : Data point Technologies
Duration of
Project : 6 weeks
Description : Clearing the traffic for Ambulance during the emergency time by using GSM in
Ambulance, Save the Patient/Human.
Tools Used : GSM Satellite Maps.
Personal details:
Date of Birth : 22-08-1996.
Address : D No: 3-30, Abburu (PO), Sattenapalli (MD), Guntur (DT),AP
Father’s Name : Parameswara Rao.
Nationality : Indian.
Languages known : English, Telugu.
I hereby declare that all the information given above is good and true up to my knowledge.
Date:
Place: