Indian Institute of Astrophysics Presentation by Aritra Sarkar on Astrosat memory management

1. “ASTROSAT SSR”
15-05-2015

2. Presentation Overview
• Introduction
• SSR Mission Requirements and Specifications
• System Design
• Hardware Architecture
• SSR Interfaces
• Software Mission Requirements
• Software Design
• Telecommands and Telemetry
• Software Testing

3. INTRODUCTION

4. Introduction
• ASTROSAT carries the following payloads:
• Ultra Violet Imaging Telescope (UVIT)
• Large area Xenon proportional Counter (LAXPC)
• Soft X‐ray Telescope (SXT)
• Cadmium Zinc Telluride Imager (CZT)
• Scanning Sky Monitor (SSM)
• Charge Particle Monitor (CPM)
• Solid State Recorder (SSR) of 144 Gb at BOL and 120 Gb at EOL is the
requirement for storing science data
• The formatted payload data is stored in SSR during recording
• During Playback, Differentially Encoded data from SSR is routed to X-band
data transmitter directly

5. REQUIREMENTS & SPECIFICATIONS

6. SSR Requirements
• SSR Capacity
• 144 at BOL and 120 at EOL
• 4 Input channels with LVDS I/F for 8 data lines and strobe on each port.
• Channel 0, 1, 2 data strobe rate is 22MHz and 8.8.MHz for Channel 3
• 2 Output port for playback with downlink data rate of 105 Mbps on each
• Recording, Playback, Command and Telemetry
SSR must be capable of
• Recording 4 external input channels for BDH data interface
• 2 external output ports for RF interface for QPSK transmitter
• 1553B bus interface for command reception and HK data transmission
• SSR shall also provide following functions
• SSR controller redundancy
• FDIR management
• Power supply redundancy
• Memory management
• Graceful degradation

7. System Specifications
Capacity 144 Gb BOL and 120 Gb at EOL
Data rate Input : 22 * 8 Mbps for CH1, CH2, CH3 (Burst)
8.8 * 8 MHz for CH4 (Burst)
Output: 210 Mbps – 105 Mpbs each on 2 ports
Ports 4 Input ports
2 Output serial ports (52.5Mbps x2) I& Q @ 8125MHz & 8300 MHz
Interface with BDH & XBS LVDS
Command & telemetry
interface
1. 1553 interface for data commands & digital telemetry words.
2. 64ms pulse for discrete SEL/DESEL, ON/OFF and CPU reset commands.
3. Analog channels for voltage & temperature monitoring.
Number of partitions Four
System Modes 1.Record, 2. Playback, 3. Simultaneous record and playback and 4. Maintenance
Input Raw bus supply Raw bus A & B (28V to 42V DC)
Power Consumption 1) Configuration mode : 14 W
2) Maintenance mode : 32 W
3) Record (nominal) + Playback : 32 W
4) Record (120/40) + Playback (0/210) : 40 W (peak)
Redundancy System I/O controller, Internal Bus, power bus

8. Data Rates
8125 MHz 8300 MHz
Port 0
α
Port 0
β
Port 1
α
Port 1
β
Line Type Serial Serial Serial Serial
Clock Rate 52.5 MHz 52.5 MHz 52.5 MHz 52.5 MHz
Line Bandwidth 52.5 Mbps 52.5 Mbps 52.5 Mbps 52.5 Mbps
Data Mode 1
Data Mode 2
105 Mbps 105 Mbps
playback not allowed
SSR Data Rate
Budget
Playback
Channel 0 Channel 1 Channel 2 Channel 3
Line Type Parallel (8 bit) Parallel (8 bit) Parallel (8 bit) Parallel (8 bit)
Clock Rate 22 MHz 22 MHz 22 MHz 8.8 MHz
Line Bandwidth 176 Mbps 176 Mbps 176 Mbps 70.4 Mbps
Data Mode 1 ≤ 40 Mbps ≤ 40 Mbps ≤ 40 Mbps ≤ 12 Mbps
Data Mode 2 = 120 Mbps ≤ 32 Kbps
SSR Data Rate
Budget
Record
= 120 Mbps (only 1 Ch, other one 0 )

9. SYSTEM DESIGN

10. System Configuration
• Primary Functions of the SSR are
• Collecting formatted data from base band Data Handling system
• Storing it in Mass Memory
• Retrieval of the stored data upon request
• Performing of above function is based on Telecommand received from
OBC. Similarly health parameters and functional indicators of SSR are
transmitted to ground through Telemetry system of OBC.
SSR -10
Controller
M
Controller
R
LVDS
Ip Inf
Memory
Boards
0,1,2,3
LVDS
Op Inf
BDH M
BDH R
XBS
1,2 M
XBS
1,2 R
4chs
4chs

11. Package Stack

12. SSR Package

13. Functional Blocks

14. HARDWARE ARCHITECTURE

15. Hardware Architecture (FEL)
• Front End Logic handle four channels data from BDH and temporarily stores in
buffer/FIFO before transferring it to memory board for storage
• Consists of two parts FEL0 and FEL1. FEL0 handles CH0 and CH1 whereas FEL1
handles CH2 and CH3
• Data is burst in nature for all ports and data is transferred at 176 Mbps for
CH0, CH1 and CH2 and at 70.4 Mbps for CH3
• The data throughput varies depending on Payload modes of operation.
Maximum of 120 Mbps is expected during UVIT diagnostics (window) mode.

16. Hardware Architecture (FEL)
• Data from both FEL0 and FEL1 is transferred through 32 bit data bus, shared
between both FELs and MMC to Slave Memory Controller in memory board.
Design is targeted to Microsemi Actel RT54SX32SU-1 FPGA
• Implementation of Channel 0, 1 & 2 are identical with FIFO size (of 512 Mb)
and while for Channel 3 the FIFO size is smaller (of 64 Mb). This is to cater to
the slower data rate requirement for Channel 3.
• Data Transfer from FEL to SMC are in blocks of 512/64 Mb segments. The data
is retained in the FEL FIFO SDRAM till the required packet size data is received.

17. FEL Design

18. Hardware Architecture (MMC)
• MMC allows processor software to take control over the system by acting as
peripheral interface
• Generates necessary control signals and cycle time signals to make Front End
Logic and Slave memory controller to act as a single unit for achieving record
and reading of BDH data in SSR
• MMC has interface with processor multiplexed bus of Address and data. It
receives Clock from crystal oscillators of 52.5MHz and 24 MHz frequency.
24 MHz frequency period is used to operate 1553B protocol chip and
processor clock of 2.66 MHz for a duty cycle of 33%
• MMC provides timing and logical support for SµMMIT 1553 protocol chip, FEL
and SMC

19. Hardware Architecture (MMC)
• The BDH data collected by FEL is transferred the output FIFO. MMC on
realizing that FEL FIFO is full and waiting to be stored in SSR memory, releases
the record slot to FEL
• Upon receiving record slot, FEL shifts the data stored in FIFO to SMC through
Memory bus and data reaches to Memory devices via SMC along with parity
• All these actions are done with respect to defined slots for record, playback
and refresh
• The requirement of two playback slots, for two output ports having data rate
105 Mbps is met by the MMC

20. Hardware Architecture (MMC)
• Data received in Front End Logic is transferred to memory board based on
slots
• Timing logic inside the Master Control Logic FPGA generates fixed slots for
record, playback and refresh
• While recording Data will be transferred to Memory board whenever
sufficient data is accumulated in the FEL controller memory (512Mb for BDH
Channel 0, 1, 2 & 64 Mb for Channel 3)
• During playback, slots are generated and data will be transferred from the
memory board to MMC.
• MMC serializes and differentially encodes the data before transferring to X-
Band data transmitter

21. Hardware Architecture (SMC)
• The Slave Memory Controller is designed to handle 6 banks of memory, each
of 8 Gb capacity
• Slave memory controller has functional blocks like SPI slave, SDRAM
Controller, FIFO & EDAC. SPI slave interfaces with Master Memory Controller
• It receives signals Master-Out-Slave-In (MOSI), SPI_CLK, and SPI_CS signals
from MMC and communicates to MMC via Master-In-Slave-Out (MISO) signal
• Other signals received by SMC are Record, Playback, Channel ID and Refresh.
These slots arrive in cyclic fashion where two adjacent slots occupied by
record, followed by play and then refresh

22. Hardware Architecture (SMC)
• During record or playback SMC generates control signals for SDRAM namely
RAS, CAS, WEN, CS signals to memory banks for proper reading and writing of
data
• Refresh activity of SDRAM is carried out during refresh slot

23. Memory Organization
• 4 Boards (each 48 Gb + 12 Gb EDAC)
• 12 Logical Banks (6 Physical Banks)
• Each Physical Bank = 16 segments
• Each Segment = 512 Mb
• Physical Bank invalidation
• Intersegment addressing for 64 Mb

24. Memory Board

25. SSR INTERFACES

26. Interfaces

27. REVIEWS

28. Hardware Configuration changes from PDR
• In PDR, it was projected that playback data from SSR is received in BDH and given to RF
after differential encoding. Since there is no real time transmission of data from BDH and
only playback data is getting transmitted, committee recommended that RF interface can
be implemented in SSR instead of BDH. Hence playback data is directly sent to RF after
differential encoding from SSR itself.
• DC/DC Converter changed from MDI to IR M3G. Compatibility with respect to electrical
and mechanical specifications were reviewed and found satisfactory.
• New 41 mm DC/DC tray is used to accommodate IR M3G DC/DC converters in place of 36
mm tray so package height is increased by 5 mm.
• New mother board (RS2SSR10MB001) is introduced with buffer ICs (LVTH244) to improve
signal integrity issues seen in AS-SSR10MB001 card during Resourcesat-2 testing.

29. # Action Recommendations Status
1 Fuse for selected supply is not advisable.
Explore whether resistor can be used
instead of fuse, in the individual cards
Since current requirement is high in the order
of 400mA, resistor drop will substantially
decrease supply voltage of ICs. Hence Fuse is
preferred.
-
2 Capability of DC-DC verses demand for in-
rush current to be demonstrated
Current characteristics are captured during
bench test.
Complied
3 Consolidate the power requirements New power requirements are circulated to
Thermal & Project Team
Complied
4 EMI shield to be provided mandatorily Mother board cover is provided to package. Complied
PDR Action Item Closeouts for Hardware

30. S.No Action Items Generated Closeouts
1 Maximum data rate supported for all the channels in various modes
have to be clearly indicated in the Design document.
Complied and updated
the FRS and FDD
document in Ver1.0
2 Should contain details regarding how the major cycle and minor cycle
timings are arrived at, and how the following requirements with
respect to Large FIFO are met without any data loss during various
modes of operations
Complied and updated
the FRS and FDD
document in Ver1.0
3 Design document to indicate input FIFO depth and detail how this
depth is arrived at based on Read/ write rates.
Complied and updated
the FRS and FDD
document in Ver1.0
4 The details of clock buffers used for the various clocks have to be
brought out in the document.
Complied and updated
the FRS and FDD
document in Ver1.0
5 FPGAs and all its external interfaces should be clearly indicated in
the design document.
Complied and updated
the FRS and FDD
document in Ver1.0
FEL FPGA Design Reviews

31. Presentation Overview

32. SOFTWARE REQUIREMENTS

33. SSR Data Input Channels
• ASTROSAT Payloads & SSR Input Data:
• Ultra Violet Imaging Telescope (UVIT)
• UVIT Visible bands (350-600nm) (VIS)
• UVIT Near Ultra Violet (180-300nm) (NUV)
• UVIT Far Ultra Violet (130-180nm) (FUV)
• Large area Xenon proportional Counter (LAXPC)
• Soft X‐ray Telescope (SXT)
• Cadmium Zinc Telluride Imager (CZT)
• Scanning Sky Monitor (SSM)
• Spacecraft Aux Data (AUX)
• Charge Particle Monitor (CPM)
← SSR Input Channel 0
← SSR Input Channel 1
← SSR Input Channel 2
← SSR Input Channel 3
← Directly to LBT (OBC)

34. Mission Requirements
• Capacity: 144 Gb (BOL) for storing science data of ~120 Gb (BOL)
• 48 Gb provided as spare Memory Board
• Record: Formatted payload data stored in SSR
• Recording ‘always On’
• Record Pause & Resume (for spacecraft orientation)
• No Real-Time Playback
• Simultaneous Record & Playback required
• Playback: Data from SSR routed directly to X-band system
• 2 Output ports
• Any Channel Data : Playback in any output port
• Playback Pause & Resume
• Configurable Playback Offset (re-dump data & data stitching)
• File Management: 4 configurable (size) Circular buffers for Payload Data
• 1 for each Input Channel

35. SOFTWARE DESIGN

36. Software Features & Design
• New design implemented on 8086 assembly language (2.66 MHz CPU clock)
• Scheduler based architecture
• Software enters the Scheduler Routine after the initialization of the
required S/W & H/W variables and 1553 SµMMIT chip
• Diagnostics: Device, Bus, Memory
• System Fault management:
• SDRAM Memory isolation at Board and Bank level
• Modified hamming code (39,32) in memory board for payload data
• Processor Fault management:
• WDT FDIR
• Majority Voting Logic in software for SRAM variables
• Playback Queuing

37. Software Cycle
Clock Low Clock High
TaskManager
Clock High Clock Low
Ref1553DT
PatrolScrub
ResetWDT
WDT2bitOC_Rst
TaskManager
Ref1553DT ResetWDT
PatrolScrub WDT2bitOC_Rst
• 16 ms Cycle (derived by polling a Hardware Timer IO mapped port)
• 50% duty cycle (at edge transitions, activities are performed sequentially)
• Clock High usage: 3 ms of 8 ms (constant)
• Clock Low usage: 5 ms of 8 ms used (worst case)

38. Software Modes

39. Mode Transitions

40. Configuration Mode
• Default POR State
• SSR Configuration to be carried out
• System Settings:
• WDT
• EDAC
• Unlock Administrator Access & commands (for hardware debugging)
• Safe Mode
• Board & Bank Configuration
• From EEPROM
• Manual commanding
• Memory Partitioning

41. Maintenance Mode
• Device Diagnostics
• 24 locations in 96 segments per board with AAAA5555 & 5555AAAA
• Memory Diagnostics with PN 215-1 sequence
• Board-wise
• Results in Telemetry (no auto reconfiguration)
• Refresh always On

42. Operational Mode
• Refresh always On (Retention)
• Record & Playback operations: simultaneous/independent
• Record & Playback Pause/Resume
• Playback Offset configuration
• Playback Queuing on both Ports for any Channel (up to 16 Playbacks per Port)

43. General Routines
• Scheduler & Task Manager
• 1553 Services (Telecommand/Telemetry/Mode Codes)
• Segment Search Routines (Linear/Circular Positive & Negative)
• SPI Transmit/Receive Services
• Memory Board Initialization
• Record/Playback Segment Address read/write
• Memory Board monitoring
• TMR for Processor SRAM

44. File Management
• Memory Partitioning
• Involves searching the commanded number of free segments, and
allocating them to the Channel
• Skips invalidated banks & boards
• Channel Partition can span over multiple boards
• Partition should always be in sequence
• Repartitioning is not allowed in Operation Mode
• Minimum partition size required is 1 segment (512 Mb) per Channel
e.g.

45. Record Operations

46. Playback Operations

47. Thank You

48. SUPPORT SLIDES

49. Mission Requirements (contd.)
• Mechanical Specifications
• Dimensions (L-B-H): 290 x 230 x 203 mm
• Mass: <7 kg
• Thermal: 0 ° to +50° C (ETLSC document)
• Power
• Bus voltage (Min-Nom-Max): 28 V, 35 V, 42 V
• EMI/EMC
• Compliance of ISRO standard (461C tailored for IRS missions)

50. SDRAM Addressing
Bit Number … 38 37 36 35 34 33 32 31 30 29 28 27 26 25 … 5 4 … 0
Weight … 256Gb 128Gb 64Gb 32Gb 16Gb 8Gb 4Gb 2Gb 1Gb 512Mb 256Mb 128Mb 64Mb 32Mb … 32b 16b … 1b
Definition x
Size Calculation x
Dependencies x
H/W Interface x
S/W Usage x
8 x 64Mb = 512Mb
Board CS Autostop LengthSegment Address Intersegment Address x
4 x 48Gb = 192Gb 12 x 4Gb = 48Gb (Bank 0 - 11 only) 8 x 512Mb = 4Gb
MMC SMC Bus Port Width
Software & Hardware Hardware Only
Memory Addressing in ASTROSAT
Boards in 1 Package Banks in 1 Board Segments in 1 Bank 64 Mb Length
• Bus Port width = 32 (5 bit)
• Burst = 8 (3 bit)
• RAS/CAS = (17 bit)
• 64 Mb Ch3 in 512Mb SMC segment = 8 (3 bit)
• 512 Mb segments in 1 Phy Bank = 16 (4 bit)
• Phy Banks in 1 Board = 6 (3 bit)
• Boards in Package = 4 (2 bit)

51. Software Functionality

52. File Management
21
20 LSB
19 x MSB
18
17 MSB
16 LSB
15 MSB
14 LSB
13
12
11 MSB
10 LSB
9 MSB
8 LSB
7 MSB
6 LSB
5 MSB
4 LSB
3 MSB
2 LSB
1
0 Partition Init. Partition On x Partition Val. Rec. Init. Rec. Resume
Byte bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
x
x
9-bit Playback Stop Segment Pointer
9-bit Playback Segment Pointer (Playback Resume Segment Address)
9-bit File Size (Channel Partition Size)
9-bit Start of File Segment Pointer (Channel Partition Start)
9-bit Current Record Segment Pointer (Record Resume Segment Address)
9-bit Next Record Segment Pointer
9-bit End of File Segment Pointer (Channel Partition End)
x
x
x
x
x
File Metadata ASTROSAT
31-bit Record Counter MSB
31-bit Record Counter LSB
22-31
Playback Auto-Stop Length (multiples of 64Mb)
x
x
x
x

53. Playback Queuing Scheme
Channel 0 Channel 1 Channel 2 Channel 3
Negative -C0a -C1a -C2a -C3a
Positive +C0a +C1a +C2a +C3a
Channel 0 Channel 1 Channel 2 Channel 3
Negative -C0b -C1b -C2b -C3b
Positive +C0b +C1b +C2b +C3b
SRAMOffset Settings at time = a
SRAMOffset Settings at time = b
Initial Value: E = 0; D = 15
Command EnQue @ E
Queuefull @ D = E
Command DeQue @ (D+1)
Queueempty @ (D+1) = E

54. Thank You