2. Data Communications
• Data communications refers to the ability of one computer to
exchange data with another computer or a peripheral
• Physically, the data comm. path may be a short, 5 to 10 feet ribbon
cable connecting a microcomputer and parallel printer; or it might
be a high speed telecommunications port connecting two
computers thousands of miles apart.
• Standard data communication interfaces and standards are needed
• e.g. parallel printer interface, RS232, RJ45.
• 8251 USART (Universal Synchronous/Asynchronous
Receiver/Transmitter) is the key component for converting parallel
data to serial form and vice versa
• Two types of serial data communications are widely used
– Asynchronous communications
– Synchronous communications
4. Asynchronous Communications
• Eliminates the need for a clock signal between
two microprocessor based systems
System 1 System 2
Transmit data
Receive data
Signal common
5. Asynchronous Communications
• Data to be transmitted is sent out one
character at a time and the receiver end of the
communication line synchronization is
performed by examining synchronization bits
that are included at the beginning and at the
end of each character
6. Synchronous Communications
System 1 System 2
Transmit data
Receive data
Signal common
clk
BISYNC: Each block of data
has synch characters. The
size of block data can be 100
or more bytes. BCC checks
for errors.
Serial Data Link Control: Developed by
IBM used for computer networking (Token
Ring). After Flag byte the network address
is sent. Control Byte stores information
about sequence of data etc. Data is
thousands of bits. 16 bit field is used for
error checking.
7. USART
• It is possible to use either of the two methods.
• There are special IC chips for serial data communication
• UART: universal asynchronous receiver transmitter
• USART: universal Synchronous/Asynchronous Receiver/Transmitter
• COM port in the original IBM PC uses 8250 UART
• INTEL has USART 8251
• National Semiconductor’s improved version of 8250A is 16450.
• 16450, 16550, 16552 (dual 16550)
• Data Transmission
– simplex
– half duplex
– full duplex
10. Arch - details
• The functional block diagram of 825 1A
consists five sections.
They are:
• Read/Write control logic
• Transmitter
• Receiver
• Data bus buffer
• Modem control.
11. Read/Write control logic
• The Read/Write Control logic interfaces the 8251A
with CPU, determines the functions of the 8251A
according to the control word written into its control
register.
• It monitors the data flow.
• This section has three registers and they are control
register, status register and data buffer.
• The active low signals RD, WR, CS and C/D(Low) are
used for read/write operations with these three
registers.
12. Read/Write control logic
• When C/D(low) is high, the control register is
selected for writing control word or reading status
word.
• When C/D(low) is low, the data buffer is selected for
read/write operation.
• When the reset is high, it forces 8251A into the idle
mode.
• The clock input is necessary for 8251A for
communication with CPU and this clock does not
control either the serial transmission or the
reception rate.
13. Transmitter
• The transmitter section accepts parallel data from
CPU and converts them into serial data.
• The transmitter section is double buffered, i.e., it has
a buffer register to hold an 8-bit parallel data and
another register called output register to convert the
parallel data into serial bits.
• When output register is empty, the data is
transferred from buffer to output register. Now the
processor can again load another data in buffer
register.
14. Transmitter
• If buffer register loads the data in O/P register amd
becomes empty, then TxRDY goes to high.
• If output register is empty then TxEMPTY goes to high.
• The clock signal, TxC (low) controls the rate at which the
bits are transmitted by the USART.
• The clock frequency can be 1,16 or 64 times the baud
rate.
15. Receiver
• The receiver section accepts serial data and convert
them into parallel data
• The receiver section is double buffered, i.e., it has an
input register to receive serial data and convert to
parallel, and a buffer register to hold the parallel
data.
16. Receiver
• The CPU reads the parallel data from the buffer register.
• When the input register loads a parallel data to buffer register
and becomes empty, the RxRDY line goes high.
• The clock signal RxC (low) controls the rate at which bits are
received by the USART.
• During asynchronous mode, the signal SYNDET/BRKDET will
indicate the break in the data transmission.
• During synchronous mode, the signal SYNDET/BRKDET will
indicate the reception of synchronous character.
17. Modem control
• The MODEM control unit allows to interface a MODEM to 8251A and to
establish data communication through MODEM over telephone lines.
• This unit takes care of handshake signals for MODEM interface.
• The 8251A can be either memory mapped or I/O mapped in the system.
• 8251A in I/O mapped in the system is shown in the figure.
• Using a 3-to-8 decoder generates the chip select signals for I/O mapped
devices.
• The address lines A4, A5 and A6 are decoded to generate eight chip select
signals (IOCS-0 to IOCS-7) and in this, the chip select signal IOCS-2 is used
to select 8251A.
• The address line A7 and the control signal IO / M(low) are used as enable
for decoder.
• The address line A0 of 8085 is connected to C/D(low) of 8251A to provide
the internal addresses.
19. Modem control
• The data lines D0 - D7 are connected to D0 - D7 of the
processor to achieve parallel data transfer.
• The RESET and clock signals are supplied by the processor.
Here the processor clock is directly connected to 8251A. This
clock controls the parallel data transfer between the
processor and 8251A.
• The output clock signal of 8085 is divided by suitable clock
dividers like programmable timer 8254 and then used as clock
for serial transmission and reception.
20. Modem control
DSR- Data Set Ready: Checksif the Data Set is
device is ready to accept data when the 8251is
communicating withamodem.
to transmit the serial data provided the enablebit in
the command byte is set to ‘1’.
the modem that the receiver is ready to receive a
data byte from the modem.
DSR - Data Set Ready : Checks if the Data
Set is ready when communicating with a
modem.
DTR - Data Terminal Ready : Indicates that
the device is ready to accept data when the
8251 is communicating with a modem.
CTS - Clear to Send : If its low, the 8251A is
enabled to transmit the data.
RTS - Request to Send Data : Low signal
indicates the modem that the receiver is ready
to receive a data byte from the modem.
21.
22.
23.
24.
25.
26. Initializing the 8251
• To implement serial communication the MPU must inform the 8251
about the mode, baud, stop bits, parity etc. A set of control words
must be loaded.
– Mode Words
• Specifies general characteristics of the operation.
– Command Words
• Enables the data transmission and/or reception
– Status Word provides the information concerning register status and
transmission errors.
• Any control word written into the control register after a mode
word is interpreted as a command word; that means a command
word can be changed anytime, however 8251 should be reset prior
to writing a Mode word.
• 8251 can be reset internally by using the Internal Reset Bit D6.
27. 8251 A Serial Communication
Interface
•The 8251A internally interprets the C/D,RD and WR
signals as follow:
•Whether the mode, control or sync character register is
selected depends on the accessing sequence.
•A flowchart of the sequencing is given in Fig.
28. Format
of the
mode
register
What value must be written
into the mode control register
with baud rate divided by 16,
char. Size 16 bits, odd parity,
one stop bit ?
------------------------------------
01011110 b = 5Eh
30. •A program sequence which initializes the mode register and
gives a command to enable the transmitter and begin an
asynchronous transmission of 7-bit characters followed by an
even-parity bit and 2 stop bits is:
MOV AL,11111010B
OUT 51H,AL
MOV AL,00110011B
OUT 51H,AL
Example 1
