The document discusses the Universal Synchronous Asynchronous Receiver Transmitter (USART) and Analog-to-Digital Converter (ADC) components in PIC microcontrollers. It describes how USART can be configured for synchronous or asynchronous communication and the functions of its TXSTA and RCSTA registers. It also explains the steps for ADC conversion, including configuring the ADC module, selecting the input channel, starting conversion, and reading the result registers.

1. UNIVERSAL SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER(USART)

2. USART:
• To communicate with external components such as
computers or microcontrollers, the PIC micro uses a
component called USART - Universal Synchronous
Asynchronous Receiver Transmitter.This component can be
configured as:
• a Full-Duplex asynchronous system that can communicate
with peripheral devices, such as CRT terminals and personal
computers
• a Half-Duplex synchronous system that can communicate
with peripheral devices, such as A/D or D/A integrated
circuits, serial EEPROMs, etc.

3. To enable the serial communication with PIC micro we must set different parameters within two
registers:
1. TXSTA - Transmit Status and Control Register
2. RCSTA - Receive Status and Control Register

4. TXSTA Description:-
The size of this register is one byte (8 bits). Each bit has an important role in
the definition of the component. Here's a breakdown of the bit roles:
CSRC: Clock Source Select bit – this bit is meaningful only in Synchronous
communication in Half-Duplex mode. It “determines” if the component is Master
(transmitter) or Slave (receiver). It does not matter in the case of Full-Duplex mode.
Asynchronous mode:
Don’t care.
Synchronous mode:
1 = Master mode (clock generated internally from BRG)
0 = Slave mode (clock from external source)
TX9: 9-bit Transmit Enable bit - this bit lets select the transmitted frame size 8 or
9-bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission

5. TXEN: Transmit Enable bit
1 = Transmit enabled
0 = Transmit disabled
SYNC: USART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode

6. BRGH - High Baud Rate Select bit – setting this bit “determines” the transmission
speed (High / Low). The setting of this bit valid only for asynchronous mode, and not
used for synchronous mode:
Asynchronous mode:
1 = High speed
0 = Low speed
Synchronous mode:
Unused in this mode.
TRMT - Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
TX9D - Place for a 9th bit, in the case of transmitting 9-bits.

7. RCSTA Description:-
The size of this register is also 8 bits. The role of each bit is discussed below:
SPEN: Serial Port Enable bit
1 = Serial port enabled (configures pin RC7/RX/DT for receiving the information into the PIC, and pin RC6/TX/CK
for transmitting the information from PIC)
0 = Serial port disabled
RX9: 9th -bit Receive Enable bit
1 = enables reception of 9 bit
0 = enables reception of 8 bit
SREN - Single Receive Enable bit - this bit enables or cancels transmission of packets. In the asynchronous
mode - this bit is not important. The importance of this bit is only in the synchronous mode (Half-Duplex) and
only when PIC is Master.

8. Asynchronous mode:
Don’t care.
Synchronous mode – Master:
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronous mode – Slave:
Don’t care.
CREN - Continuous Receive Enable bit
Asynchronous mode:
1 = Enables continuous receive
0 = Disables continuous receive
Synchronous mode:
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disables continuous receive

9. ADDEN - Address Detect Enable bit - this bit enables interrupt only when the frame size is 9-bit. It does not matter, when the
size of the frame is 8-bit.
Asynchronous mode 9-bit (RX9 = 1):
1 = Enables address detection, enables interrupt and load of the receive buffer when RSR[8] is set
0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit
FERR – Framing Error bit
Logic level “1” – means the STOP bit was not received. In serial communication we use START bit and STOP bit when
transmitting the information.
1 = Framing error (can be updated by reading RCREG register and receive next valid byte)
0 = No framing error
OERR - Overrun Error bit
Logical level “1” means that new byte of data was received, while there is still previous data that did not proceed into the PIC.
In this case, the new received information is lost.
1 = Overrun error (can be cleared by clearing bit CREN)
0 = No overrun error
RX9D: 9th bit of Received Data, in the case of receiving 9-bits.

10. Synchronous communication
• When using the synchronous communication – the information is transmitted
from the transmitter to the receiver:
• in sequence
• bit after bit
• with fixed baud rate
• and the clock frequency is transmitted along with the bits
• That means that the transmitter and the receiver are synchronized between
them by the same clock frequency. The clock frequency can be transmitted along
with the information, while it is encoded in the information itself, or in many
cases there is an additional wire for the clock.
• This type of communication is faster compare to the asynchronous
communication since it is "constantly transmitting” the information, with no
stops.

11. Asynchronous communication
• When using the asynchronous communication - the transmitter and the
receiver refraining to transmit long sequences of bits because there isn't
a full synchronization between the transmitter, that sends the data, and
the receiver, that receives the data.
• In this case, the information is divided into frames, in the size of byte.
Each one of the frame has:
“Start” bit marks the beginning of a new frame.
“Stop” bit marks the end of the frame.
• Frames of information must not necessarily be transmitted at equal time
space, since they are independent of the clock.

12. ANALOG-TO-DIGITAL CONVERTER(ADC)
• The A/D module has four 8 bit registers. These registers are:
• ADCON0 - A/D Control Register 0; determines the behavior of the A/D
• ADCON1 - A/D Control Register 1; determines the configuration of the
PORTA and PORTE and how the result of conversion of A/D will be
store
• ADRESH - A/D Result High Register
• ADRESL - A/D Result Low Register

13. The size of this register is one byte (8 bits). Each bit has an important role in the definition of the component. Here's
a breakdown of the bits role:

14. GO/DONE: A/D Conversion Status bit
If ADON = 1:
1 = A/D conversion in progress (setting this bit starts the A/D conversion)
0 = A/D conversion not in progress (this bit is automatically cleared by hardware when the A/D conversion is complete)

15. ADON: A/D On bit
1 = A/D converter module is operating
0 = A/D converter module is shut-off and consumes no operating current

16. ADFM: A/D Result Format Select bit
1 = Right justified. 6 Most Significant bits of ADRESH are read as ‘0’.
0 = Left justified. 6 Least Significant bits of ADRESL are read as ‘0’.
As we said, the A/D converter has a resolution of ten bits, i.e., the result of the conversion can not be stored in one register of
eight bits.
Therefore, the result is stored in two registers: ADRESL and ADRESH. The size of each register is 8 bits long, so that we have 16
(2*8) bits all together. We can store the result of the conversion which is 10 bits long using the two registers ADRESL and
ADRESH in the following 2 ways:
• alignment to the left
• alignment to the right
Alignment to the left – the eight MSB bits are stored in the ADRESH, and the two LSB bits are stored in ADRESL. In this case, the
remaining six bits appear as - "0".
Alignment to the right – the eight LSB bits are stored in ADRESL, and two MSB bits are stored in the ADRESH. In this case six
highest bits appear as - "0".
Right justified(ADFM =1) XXXXXX1111111111
Left Justified(ADFM =0) 1111111111XXXXXX.

17. PCFG3:PCFG0: A/D Port Configuration Control bits:
With these bits we can control the pins of PORTA or PORTE. We can decide an analog (A) or digital (D) mode.

18. • If we want to work with the PORTA and PORTE as analog ports, then we select
the option PCFG3: PCFG0 = 0000; If we want to work with ports as digital,
then we select the option PCFG3: PCFG0 = 011x.
• In general, after the specified desired behavior of the A/D converter unit and
before we start the conversion operation, we have to set up channel through
which the analog information will be received using TRIS command. To begin
making the conversion, we have to set the GO/DONE =1. This is done by using
the command ADGO = 1. When the conversion ends, the result will be loaded
into 2 registers ADRESH: ADRESL. Status bit GO/DONE (the register ADCON0)
will be set to zero and the ADIF flag is set.

19. Analog to Digital BLOCK DIAGRAM

20. To summarize, the following steps should be followed for doing an A/D Conversion:
1. Configure the A/D module:
• Configure analog pins/voltage reference and digital I/O (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D conversion clock (ADCON0)
• Turn on A/D module (ADCON0)
2. Configure A/D interrupt (if desired):
• Clear ADIF bit
• Set ADIE bit
• Set PEIE bit
• Set GIE bit
3. Wait the required acquisition time.
4. Start conversion:
• Set GO/DONE bit (ADCON0)
5. Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared(with interrupts enabled); OR
• Waiting for the A/D interrupt
6. Read A/D result register pair (ADRESH:ADRESL), clear bit ADIF if required.
7. For the next conversion, go to step 1 or step 2, as required.