unit-3 feild effect transisitors

1. unit3
Field effect transistors

2. JFET
• IT IS A JUNCTION EILD EFFECT TRANSISTOR
• VOLTAGE CONTROLLED TRANSISTOR
• IT IS A UNIPOLAR DEVICE
• FET IS A DEVICE IN WHICH THE FLOW OF
CURRENT THROUGH THE CONDUCTING
REGION IS CONTROLLED BY AN ELECTRIC
FIELD.

3. TYPES

4. SYMBOL

5. N-channel JFET

6. Circuit diagrams n- channel

7. CONSTRUCTION
• OHMIC CONTACTS(P-
TYPE,GATE,SOURCE,DRAIN)
• The Ohmic contact is a low resistance
junction (non-rectifying) provides current
conduction from metal to semiconductor .
• SILICON BAR(N-TYPE).

8. UNDERSTANDING METHODOLOGIES
• TAP

9. OPERATION
• VGS=0 AND VDS=0
• NO VOLTAGE APPLIED BETWEEN THE DRAIN
AND SOURCE,GATE AND SOURCE
• THE THICKNESS OF DEPLETION REGIONS
ROUND THE PN JUNCTION IS UNIFORM

10. VGS=0 AND VDS INCREASED ROM
ZERO
• Drain is positive with respect to the source
with vgs=0.
• Now the majority cariers(electrons)flow
through the N- channel from source to drain.

11. Vgs is negative and vds is increased
• When the gate is maintained at a negative
voltage less than the negative cutoff voltage,
reverse voltage across the junction is further
increased.
• JFET is suitable for voltage amplifier similr to
transistor amplifier
• Vds=vp the drain curent is not reduced to
zero.

12. OPERATION
• A negative supply VGS is connected between the gate
and the source. This reverse bias sets up a depletion
layer or transition layer around the P-region and this
makes the conducting channel thin dipicted.
• As the reverse bias across the gate junction is
increased, the width of the channel will be decreased
because the depletion layer gets increased.
Accordingly, for a fixed drain to source voltage (VDS),
the drain current ID will be a function of the
reversebiasing voltage across the gate junction.

13. Effect of reverse bias

14. Drain characteristics of n-channel JFET

15. condition
• AS VDS INCREASED FROM ZERO,ID INCREASES ALONG
OP,AND THE RATE OF INCREASE OF ID WTH VDS
DECREASES.THE REGION FROM VDS=0V TO VDS=VP IS
CALLED OHMIC REGION.THIS IS UEFUL FOR VOLTAGE
VARIABLE RESISTOR(VVR).
• WHEN VDS=VP,ID BECOMES MAXIMUM.WHEN VDS IS
INCREASED BEYOND VP,THE LENGTH OF PINCH OFF OR
SATURATION REGION INCREASES.
• AT A CERTAIN VOLTAGE CORRESPONDING TO THE POINT
B,ID SUDDENLY INCREASES.THIS EFFECT IS DUE TO THE
AVALANCHE MULTIPLICATION OF ELECTRONS CAUSED BY
BREAKING OF COVALENT BOND OF SILICON ATOMS IN THE
DEPLETION REGION BETWEEN THE GATE AND DRAIN.

16. CHARACTERISTIC PARAMETER OF THE
JFET