The document discusses computer architecture and digital logic circuits. It begins by defining a digital computer as a system that performs computational tasks using binary numbers. It describes the two main components of a computer as hardware and software. It then defines computer architecture as the set of rules and methods that describe the functionality, organization, and implementation of computer systems. The document discusses the two main types of computer architecture: Von Neumann and Harvard architectures. It provides details on each architecture and their differences. Finally, it discusses Boolean algebra and its role in designing logic circuits for computer systems.
3. Introduction
Prof. K. Adisesha (Ph. D)
3
Introduction to Digital Computer:
A Digital computer can be considered as a digital system that performs various
computational tasks.
➢ The first electronic digital computer was developed in the late 1940s and was used
primarily for numerical computations.
➢ The digital computers use the binary number system, which has two digits: 0 and 1.
➢ The digital computers consists of two functional entities:
❖ Hardware
❖ Software
4. Computer Architecture
Prof. K. Adisesha (Ph. D)
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Computer Architecture:
Computer architecture is a set of rules and methods that describe the functionality,
organization, and implementation of computer systems.
➢ Architecture define it as describing the capabilities and programming model of
a computer but not a particular implementation.
➢ It includes the following:
❖ Information
❖ Formats
❖ Instruction Set
❖ Addressing Modes
5. Computer Architecture
Prof. K. Adisesha (Ph. D)
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Types of Computer Architecture:
Computer architecture consists of rules and methods or procedures which describe the
implementation, functionality of the computer systems.
➢ Given below are the types of Computer Architecture:
❖ Von-Neumann Architecture
❖ This architecture is proposed by john von-neumann.
❖ Now a day’s computer we are using are based on von-neumann architecture.
❖ Harvard Architecture
❖ Harvard architecture is used when data and code is present in different memory
blocks.
6. Computer Architecture
Prof. K. Adisesha (Ph. D)
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Von-Neumann Architecture:
Von Neumann Architecture is a digital computer architecture whose design is based on
the concept of stored program computers where program data and instruction data are
stored in the same memory.
This Architecture is composed of the following Components:
❖ Arithmetic Logic Unit (ALU)
❖ Main memory (RAM)
❖ Control Unit (CU)
❖ Interface Components (I/O)
7. Computer Architecture
Prof. K. Adisesha (Ph. D)
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Harvard Architecture:
Harvard Architecture is the digital computer architecture whose design is based on the
concept where there are separate storage and separate buses (signal path) for
instruction and data.
➢The instruction address zero is not the same as
data address zero.
➢Instruction address zero identifies 24-byte value
and data address zero identifies 8-byte value which
is not the part of the 24-byte value.
8. Computer Architecture
Prof. K. Adisesha (Ph. D)
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Difference between Von Neumann and Harvard Architecture:
VON NEUMANN ARCHITECTURE HARVARD ARCHITECTURE
It is ancient computer architecture based on stored
program computer concept.
It is modern computer architecture based on Harvard
Mark I relay based model.
Same physical memory address is used for
instructions and data.
Separate physical memory address is used for
instructions and data.
There is common bus for data and instruction
transfer.
Separate buses are used for transferring data and
instruction.
CPU can not access instructions and read/write at
the same time.
CPU can access instructions and read/write at the
same time.
It is used in personal computers and small
computers.
It is used in micro controllers and signal processing.
9. Introduction
Prof. K. Adisesha (Ph. D)
9
Introduction to Boolean Algebra:
An algebra that deals with binary number system is called “Boolean Algebra”.
➢ It is very power in designing logic circuits used by the processor of computer system.
➢ The logic gates are the building blocks of all the circuit in a computer.
➢ Boolean algebra deals with truth table TRUE and FALSE.
➢ If result of any logical statement or expression is always TRUE or 1, it is called
Tautology and if the result is always FALSE or 0, it is called Fallacy
➢ It is also called as “Switching Algebra”.
10. Introduction
Prof. K. Adisesha (Ph. D)
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Introduction to Boolean Algebra
A variable used in Boolean algebra or Boolean equation can have only one of two variables.
The two values are FALSE (0) and TRUE (1)
➢ A Sentence which can be determined to be TRUE or FALSE are called logical statements or
truth functions and the results TRUE or FALSE is called Truth values.
➢ Boolean Expression consists of
❖ Literal: A variable or its complement
❖ Product term: literals connected by •
❖ Sum term: literals connected by +
➢ A truth table is a mathematical table used in logic to computer functional values of logical
expressions.
11. Boolean Algebra
Prof. K. Adisesha (Ph. D)
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Truth Table
A variable used in Boolean algebra or Boolean equation can have only one of two variables.
The two values are FALSE (0) and TRUE (1)
➢ A truth table is a mathematical table used in logic to computer functional values of logical
expressions.
➢ A truth table is a table whose columns are statements and whose rows are possible scenarios.
➢ Example: Consider the logical expression
❖ Logical Statement: Sports = “Sunny can Play Cricket OR Football”
❖ Y = A OR B (Logical Variables: Y, A, B, Logical Operator OR)
A=Cricket B=Football Y=A OR B
0 0 0
0 1 1
1 0 1
1 1 1
12. Boolean Algebra
Prof. K. Adisesha (Ph. D)
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Logical Operators
There are three logical operator, AND, OR and NOT.
➢ These operators are now used in computer construction known as switching circuits.
➢ B = {0, 1} and two binary operators, ‘+’ and ‘.’
➢ The rules of operations: AND, OR and NOT.
❖ Complement: ~X (opposite of X)
❖ AND : X × Y
❖ OR : X + Y
13. Logical Operators
Prof. K. Adisesha (Ph. D)
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AND Operator
The operation performed by AND operator is called logical multiplication.
➢ The AND operator is read as “If and Only If”. This operator operates on two or more variables.
➢ The symbol we use for it is ‘.’
➢ Example: X . Y can be read as X AND Y
➢ The Truth table, Venn diagram and the Circuit diagram for the AND operator is.
14. Logical Operators
Prof. K. Adisesha (Ph. D)
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OR Operator
The operation performed by OR operator is called logical addition.
➢ The OR operator is read as “If at-least One”. This operator operates on two or more variables.
➢ The symbol we use for it is ‘+’.
➢ Example: X + Y can be read as X OR Y
➢ The Truth table, Venn diagram and the Circuit diagram for the OR operator is.
15. Logical Operators
Prof. K. Adisesha (Ph. D)
NOT Operator
The operation performed by Not operator is called complementation.
➢ The Not operator is a unary operator. This operator operates on single variable.
➢ The symbol we use for it is bar.
❖ ~𝐗 means complementation of X
❖ If X=1 then ~X =0 If X=0 then, ~X =1
➢ The Truth table, Venn diagram and the Circuit diagram for the NOT operator is.
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18. Boolean Theorems
Prof. K. Adisesha (Ph. D)
Principle of duality
The principle of duality states that every algebraic expression deducible from the postulates of
Boolean algebra, remains valid if the operators identity elements are interchanged:
➢ To form the dual of an expression, replace all + operators with . operators, all . operators with
+ operators, all ones with zeros, and all zeros with ones.
➢ Form the dual of the expression
❖ (A+1)=(A.0)
❖ a + (b.c) = (a + b).(a + c)
➢ Following the replacement rules:
❖ a(b + c) = a.b + a.c
➢ Take care not to alter the location of the parentheses if they are present.
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19. Boolean Theorems
Prof. K. Adisesha (Ph. D)
Idempotences Law:
Idempotences Law states that when a variable is combines with itself using OR or AND
operator, the output is the same variable”.
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20. Boolean Theorems
Prof. K. Adisesha (Ph. D)
Identity Law:
Identity Law states that when a variable is combines with 0 or 1 itself using OR or AND
operator, the output is the 0 or 1”.
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21. Boolean Theorems
Prof. K. Adisesha (Ph. D)
Absorption Law:
“This law enables a reduction of complicated expression to a simpler one by absorbing
common terms”.
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22. Boolean Theorems
Prof. K. Adisesha (Ph. D)
De-Morgan’s Theorem:
Stated by De-Morgan has two theorems:
➢ Theorem 5(a): “When the OR sum of two variables is inverted, this is same as inverting each
variable individually and then AND ing these inverted variables”
❖ (x + y)’ = x’y’
➢ Theorem 5(b): “When the AND product of two variables is inverted, this is same as
inverting each variable individually and then OR ing these inverted variables”
❖ (xy)’ = x’ + y’
➢ Can be proved by means of:
❖ Truth table or Algebraically
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23. Boolean Theorems
Prof. K. Adisesha (Ph. D)
De-Morgan’s Theorem:
Stated by De-Morgan has two theorems:
➢ Proof by means of truth table:
❖ (x + y)’ = x’y’ (xy)’ = x’ + y’
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x y x’ y’ x+y (x+y)’ x’y’ xy x’+y' (xy)’
0 0 1 1 0 1 1 0 1 1
0 1 1 0 1 0 0 0 1 1
1 0 0 1 1 0 0 0 1 1
1 1 0 0 1 0 0 1 0 0
24. Boolean Theorems
Prof. K. Adisesha (Ph. D)
De-Morgan’s Theorem:
➢ Proof by means of Algebraically:
❖ (x + y)’ = x’y’
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25. Boolean Theorems
Prof. K. Adisesha (Ph. D)
De-Morgan’s Theorem:
➢ Proof by means of Algebraically:
❖ (xy)’ = x’ + y’
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26. Boolean Expression
Prof. K. Adisesha (Ph. D)
Boolean Functions:
➢ A Boolean function consists of various constraints:
❖ Binary variables
❖ Binary operators OR and AND
❖ Unary operator NOT
❖ Parentheses
➢ Examples
❖ F1= x y z'
❖ F2 = x + y'z
❖ F3 = x' y' z + x' y z + x y'
❖ F4 = x y' + x' z
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27. Boolean Expression
Prof. K. Adisesha (Ph. D)
Simplification of Boolean Expression:
Simplification of Boolean expression can be achieved by two popular methods:
➢ Algebraic Manipulation
➢ Karnaugh Maps (K Map)
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28. Boolean Expression
Prof. K. Adisesha (Ph. D)
Operator Precedence
The operator precedence for evaluating Boolean Expression is:
➢ Parentheses
➢ NOT
➢ AND
➢ OR
➢ Examples
❖ x z’ + y
❖ (x y + z)'
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29. Boolean Expression
Prof. K. Adisesha (Ph. D)
Evaluation of Boolean Expression using Truth Table
To create a truth table, follow the steps given below.
➢ Step 1: Determine the number of variables, for n variables create a table with 2n rows.
❖ For two variables i.e. X, Y then truth table will need 2^2 or 4 rows.
❖ For three variables i.e. X, Y, Z, then truth table will need 2^3 or 8 rows.
➢ Step 2: List the variables and every combination of 1 (TRUE) and 0 (FALSE) for the given
variables
➢ Step 3: Create a new column for each term of the statement or argument.
➢ Step 4: If two statements have the same truth values, then they are equivalent.
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30. Boolean Expression
Prof. K. Adisesha (Ph. D)
Evaluation of Boolean Expression
Consider the following Boolean Expression F=X+Y.
➢ Step 1: This expression as two variables X and Y, then 2^2 or 4 rows.
➢ Step 2: List the variables and every combination of X and Y.
➢ Step 3: The final column contain the values of F=X+ Y.
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31. Boolean Expression
Prof. K. Adisesha (Ph. D)
Evaluation of Boolean Expression
Consider the following Boolean Expression:
➢ The truth table for the Boolean function:
is shown at the right.
➢ To make evaluation of the Boolean function easier,
the truth table contains extra (shaded) columns to hold
evaluations of subparts of the function.
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32. Boolean Expression
Prof. K. Adisesha (Ph. D)
Simplification of Boolean Expression:
Algebraic Manipulation:
➢ To minimize Boolean expressions
❖ Literal: single variable in a term (complemented or uncomplemented ) (an input to a gate)
❖ Term: an implementation with a gate
❖ The minimization of the number of literals and the number of terms → a circuit with less
equipment
❖ It is a hard problem (no specific rules to follow)
➢ Example 2.1
❖ x(x'+y) = xx' + xy = 0+xy = xy
❖ x+x'y = (x+x')(x+y) = 1 (x+y) = x+y
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33. Boolean Expression
Prof. K. Adisesha (Ph. D)
Simplification of Boolean Expression by Algebraic Manipulation:
➢ Example:
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34. Boolean Expression
Prof. K. Adisesha (Ph. D)
Simplification of Boolean Expression by Algebraic Manipulation:
➢ Example:
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35. Boolean Expression
Prof. K. Adisesha (Ph. D)
Simplification of Boolean Expression by Algebraic Manipulation:
➢ Example:
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36. Boolean Expression
Prof. K. Adisesha (Ph. D)
Canonical and Standard Forms :
The two canonical forms of Boolean algebra are basic forms that one obtains from
reading a given function from the truth table.
➢ We do not use it, because each minterm or maxterm must contain, by definition, all
the variables, either complemented or uncomplemented.
➢ Standard forms: the terms that form the function may obtain one, two, or any number
of literals.
❖ Sum of products: F1 = y' + xy+ x'yz'
❖ Product of sums: F2 = x(y'+z)(x'+y+z')
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37. Boolean Expression
Prof. K. Adisesha (Ph. D)
Canonical and Standard Forms :
Minterms and Maxterms
➢ Boolean expression expressed as sum of Minterms or product of Maxterms are called
canonical forms.
❖ The Minterm canonical expression is the Sum of all products (SOP)
❖ The maxterm canonical expression is the product of all Sum terms (POS).
➢ For example, the following expressions are the Minterm canonical form and Maxterm
canonical form of two variables X and Y.
❖ Minterm Canonical = f(X, Y) = X’Y’ + X’ Y +X Y’+ X Y
❖ Maxterm Canonical = f(X, Y) = (X+Y).(X +Y’).(X’+Y’)
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38. Boolean Expression
Prof. K. Adisesha (Ph. D)
Canonical and Standard Forms :
Minterms and Maxterms
➢ The minterms that produce a (0)
❖ f1' = m0 + m2 +m3 + m5 + m6 = x'y'z'+x'yz'+x'yz+xy'z+xyz'
❖ f1 = (f1')' = m’0 . m’2 . m’3 . m’5 . m’6 (Complement of minterms)
➢ The maxterms that produce a (1)
❖ = (x+y+z)(x+y'+z) (x+y'+z') (x'+y+z')(x'+y'+z) = M0, M2, M3, M5, M6
❖ f2 = (x+y+z)(x+y+z')(x+y'+z)(x'+y+z)=M0, M1, M2, M4
➢ Any Boolean function can be expressed as
❖ A sum of minterms (“sum” meaning the ORing of terms).
❖ A product of maxterms (“product” meaning the ANDing of terms).
❖ Both Boolean functions are said to be in Canonical form.
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39. Boolean Expression
Prof. K. Adisesha (Ph. D)
Minterms and Maxterms:
Each maxterm is the complement of its corresponding minterm, and vice versa
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41. Boolean Expression
Prof. K. Adisesha (Ph. D)
Minterms and Maxterms:
Any Boolean function can be expressed by:
➢ A truth table
➢ Sum of minterms
➢ f1 = x'y'z + xy'z' + xyz = m1 + m4 +m7
= S(1, 4, 7) (Minterms)
➢ f2 = x'yz+ xy'z + xyz'+xyz = m3 + m5 +m6 + m7
=P(3,5,6,7) (Minterms)
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42. Boolean Expression
Prof. K. Adisesha (Ph. D)
Minterms or Sum of Products (SOP):
The Minterm canonical expression is the Sum of all products (SOP)
➢ Sum of minterms: there are 2n minterms
➢ Example 4: Express F = A+B’C
as a sum of minterms.
➢ F(A, B, C) = Σ(1, 4, 5, 6, 7)
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43. Boolean Expression
Prof. K. Adisesha (Ph. D)
Maxterms or Product of Sum (POS):
The maxterm canonical expression is the product of all Sum terms (POS)
➢ Product of Sum terms : there are 2n minterms
➢ Example : F = xy + x'z as a product of maxterms.
➢ F(x, y, z) = Π(0, 2, 4, 5)
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44. Boolean Expression
Prof. K. Adisesha (Ph. D)
Conversion between Canonical Forms:
The complement of a function expressed as the sum of minterms equals the sum of minterms
missing from the original function.
➢ Minterm Canonical
❖ F(A, B, C) = Σ(1, 4, 5, 6, 7)
❖ Thus, F'(A, B, C) = Σ(0, 2, 3) = m0 + m2 +m3
➢ By De-Morgan's theorem
➢ Maxterm Canonical
❖ F(A, B, C) = (m0 + m2 +m3)' = M0 M2 M3 = Π(0, 2, 3)
❖ F'(A, B, C) =Π (1, 4, 5, 6, 7)
➢ Interchange the symbols Σ of 1’s and Π of 0’s and list those numbers missing from the original form.
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45. Boolean Expression
Prof. K. Adisesha (Ph. D)
Conversion between Canonical Forms:
Two different ways to specify the same function f of three variables.
➢ Minterm Canonical
❖ SOP Form
❖ f(x,y,z) = Σ m(1, 3, 6, 7)
➢ Maxterm Canonical
❖ POS Form
❖ f(x,y,z) = Π M(0, 2, 4, 5)
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46. Boolean Expression
Prof. K. Adisesha (Ph. D)
Conversion of SOP into Canonical form:
Convert the Boolean function f(X, Y) = X + X Y into canonical form.
➢ Solution:
❖ The given Boolean function f(X, Y) = X + X Y ------ (i)
❖ It has two variables and sum of two Minterms. The first term X is missing one variable.
❖ So to make it of two variables it can be multiplied by (Y+Y’)=1.
❖ Therefore, X = X (Y+Y’) =XY+XY’
❖ Substitute the value of X in (i) we get f(X, Y) = X Y+X Y’ + X Y
❖ Here, the term X Y appear twice, it is possible to remove one of them. f(X, Y) = X Y+X Y’
❖ Therefore: SOP Expression is f(X, Y) = Σ (2, 3)
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47. Boolean Expression
Prof. K. Adisesha (Ph. D)
Conversion of POS into Canonical form:
Convert the Boolean function F(X, Y, Z) = X+Y (Y+Z) into canonical form.
➢ Solution:
❖ The given Boolean function F(X,Y,Z) = (X+Y).(Y+Z) ------(i)
❖ It has three variables and product of two Maxterms. Each Maxterm is missing one variable.
❖ The first term can be written as X+Y = (X+Y+Z. Z ) Since Z. Z =0
❖ Using distributive law (X + YZ) = (X + Y) (X + Z), we can write X+Y = (X+Y+Z) (X+Y+ Z ) ---(ii)
❖ The Second term can be written as Y + Z = (Y+Z+X. X ) Y+Z = (Y+Z+X) (Y+Z+X ) ----(iii)
❖ Substitute (ii) and (iii) in (i) we get
F(X, Y, Z) = (X+Y+Z) (X+Y+ Z ) (Y+Z+X) (Y+Z+X )
❖ Therefore: POS Expression is F(X, Y, Z) = π (0, 1, 4)
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48. Karnaugh Map
Prof. K. Adisesha (Ph. D)
Karnaugh Map:
A graphical display of the fundamental products in a truth table.
➢ Fundamental Product: The logical product of variables and complements that produces a high
output for a given input condition.
➢ The map method provides simple procedure for minimizing the Boolean function.
➢ The map method was first proposed by E.W. Veitch in 1952 known as “Veitch Diagram”.
➢ In 1953, Maurice Karnaugh proposed “Karnaugh Map” also known as “K-Map”.
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49. Karnaugh Map
Prof. K. Adisesha (Ph. D)
Construction of K-Map :
The K-Map is a pictorial representation of a truth table made up of squares.
➢ Each square represents a Minterm or Maxterm.
➢ The Karnaugh map is completed by entering a '1‘(or ‘0’) in each of the appropriate cells.
➢ A K-Map for n variables is made up of 2n squares.
❖ Single Variable K-Map: The map consists of 2 squares (i.e. 2n square, 21
= 2 square)
❖ Two Variable K-Map : The map consists of 4 squares (i.e. 2n
square, 22
= 4 square)
❖ Three Variable K-Map: The map consists of 8 squares (i.e. 2n square, 23
= 8 square)
❖ Four Variable K-Map : The map consists of 16 squares (i.e. 2n
square, 24
= 16 square)
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50. Karnaugh Map
Prof. K. Adisesha (Ph. D)
Construction of K-Map :
Karnaugh maps, or K-maps, are often used to simplify logic problems with 2, 3 or 4
variables.
➢ Within the map, adjacent cells containing 1's (or 0’s) are grouped together in twos, fours, or
eights.
➢ For the case of 2 variables, we form a map consisting of 22
=4 cells
➢ as shown in Figure .
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51. Karnaugh Map
Prof. K. Adisesha (Ph. D)
Construction of K-Map :
Karnaugh maps, or K-maps, are often used to simplify logic problems with 3 or 4
variables.
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AB
C 00 01 11 10
0
1
CBA CBA CAB CBA
CBA BCA ABC CBA
0 2 6 4
531 7
3 Variables Cell = 23=8
52. Digital Logic Gates
Prof. K. Adisesha (Ph. D)
52
Logic Gates:
A logic gate is an idealized model of computation or physical electronic device
implementing a Boolean function.
➢ A logical operation performed on one or more
binary inputs that produces a single binary output.
➢ Types of Logic Gates:
➢ Basic Gates
➢ Universal Gates
➢ Exclusive Gates
53. Types of Logic Gates:
Basic Gates:
Digital Logic Gates
Prof. K. Adisesha (Ph. D)
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54. Types of Logic Gates:
Universal Gates:
Digital Logic Gates
Prof. K. Adisesha (Ph. D)
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55. Types of Logic Gates:
Exclusive Gates:
Digital Logic Gates
Prof. K. Adisesha (Ph. D)
55
56. NAND Gate is a Universal Gate
Prof. K. Adisesha (Ph. D)
56
To prove that any Boolean function can be implemented using only NAND gates, we will show that the
AND, OR, and NOT operations can be performed using only these gates
57. NOR Gate is a Universal Gate
Prof. K. Adisesha (Ph. D)
57
To prove that any Boolean function can be implemented using only NOR gates, we will show that the
AND, OR, and NOT operations can be performed using only these gates
58. Realization of Basic Gates using Universal Gates:
NAND Gates:
Digital Logic Gates
Prof. K. Adisesha (Ph. D)
58
59. Realization of Basic Gates using Universal Gates:
NOR Gates:
Digital Logic Gates
Prof. K. Adisesha (Ph. D)
59
60. Realization of Exclusive Gates using Universal Gates:
Using NAND Gates: Using NOR Gates:
Digital Logic Gates
Prof. K. Adisesha (Ph. D)
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61. Types of Digital Logic Circuits:
A digital logic circuit is defined as the one in which voltages are assumed to be
having a finite number of distinct value.
➢ These are the basic circuits used in most of the digital electronic devices like
computers, calculators, mobile phones.
➢ Types of digital logic circuits are:
❖ Combinational logic circuits
❖ Sequential logic circuits..
Digital Logic Circuits
Prof. K. Adisesha (Ph. D)
61
62. Combinational logic circuit:
A digital logic circuit is defined as the one in which voltages are assumed to be
having a finite number of distinct value.
➢ Combinational digital logic circuits are basically made up of digital logic gates
like AND gate, OR gate, NOT gate and universal gates (NAND gate and NOR
gate)
➢ Classification of Combinational logic circuits:
❖ Arithmetic & logic circuits.
❖ Data Transmission circuits.
❖ Code Converters.
Digital Logic Circuits
Prof. K. Adisesha (Ph. D)
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63. Binary Adder:
In many computers and other kinds of processors adders are used in the
arithmetic logic units or ALU.
➢ An adder is a device that will add together two bits and give the result as the
output.
➢ There are two kinds of adders –
❖ Half adders: A half adder just adds two bits together and gives a two-bit
output
❖ Full adders: A full adder adds two inputs and a carried input from another
adder, and also gives a two-bit output.
Digital Logic Circuits
Prof. K. Adisesha (Ph. D)
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64. Realization of Half Adder Circuits using Logic Gates:
Half adders: A half adder just adds two bits together and gives a two-bit output
Digital Logic Circuits
Prof. K. Adisesha (Ph. D)
64
65. Realization of Full Adder Circuits using Logic Gates:
Full adders: A full adder adds two inputs and a carried input from another adder,
and also gives a two-bit output.
Digital Logic Circuits
Prof. K. Adisesha (Ph. D)
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66. Multiplexer using Logic Gates:
The multiplexer is a combinational logic circuit designed to switch one of several input
lines to a single common output line.
➢ The multiplexer (MUX) are also known as data selectors because they can select
individual data or signal lines simply by turning its inputs “ON” or “OFF”.
Digital Logic Circuits
Prof. K. Adisesha (Ph. D)
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67. Demultiplexer using Logic Gates:
The demultiplexer is a combinational logic circuit designed to switch one common input
line to one of several separate output line.
➢ The demultiplexer (DEMUX) takes one single input data line and then switches it to
any one of a number of individual output lines one at a time.
Digital Logic Circuits
Prof. K. Adisesha (Ph. D)
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68. ENCODER/DECODER:
Encoders is a combinational logic circuit take all of their data inputs one at a time and
converts them into an equivalent binary code at its output.
Binary Decoder is the exact opposite to that of an Encoder
➢ The demultiplexer (DEMUX) takes one single input data line and then switches it to
any one of a number of individual output lines one at a time.
Digital Logic Circuits
Prof. K. Adisesha (Ph. D)
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69. Sequential digital logic circuits:
In sequential circuit the output of the logic device is not only dependent on the
present inputs to the device, but also on past inputs.
➢ The sequential circuits have memory devices in order to store the past outputs.
➢ In fact sequential digital logic circuits are nothing but combinational circuit with
memory.
➢ Types of Sequential logic circuits are:
❖ Flip- Flops
❖ Registers
❖ Counters
Digital Logic Circuits
Prof. K. Adisesha (Ph. D)
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70. Flip- Flops in Digital Logic:
In sequential circuit, A flip flop is an electronic circuit with two stable states that can be
used to store binary data. .
➢ Flip-flops and latches are used as data storage elements.
➢ It is the basic storage element in sequential logic.
➢ Types of Flip- Flops are:
❖ S-R Flip- Flops
❖ J-K Flip- Flops
❖ D Flip- Flops
❖ T- Flip- Flops
Digital Logic Circuits
Prof. K. Adisesha (Ph. D)
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71. S-R Flip- Flops:
A SR flip flop is also called as Set Reset flip flop an electronic circuit with two stable
states that can be used to store binary data. .
➢ This simple flip flop circuit has a set input (S) and a reset input (R).
➢ In this circuit when you Set “S” as active the output “Q” would be high and “Q‘‘” will
be low.
➢ Truth table and Circuit of SR Flip- Flops:
Digital Logic Circuits
Prof. K. Adisesha (Ph. D)
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S R Q Q’
0 0 0 1
0 1 0 1
1 0 1 0
1 1 ∞ ∞
72. J-K Flip- Flops:
JK flip-flop is the modified version of SR flip-flop. It operates with only positive clock
transitions or negative clock transitions..
➢ The JK flip flop is an improvement on the SR flip flop where The input condition of
J=K=1, gives an output inverting the output state.
➢ Truth table and Circuit of SR Flip- Flops:
Digital Logic Circuits
Prof. K. Adisesha (Ph. D)
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J K Q Q’
0 0 0 1
0 1 0 1
1 0 1 0
1 1 1 0
73. D Flip- Flops:
D flip flop is a better alternative that is very popular with digital electronics. They are
commonly used for counters and shift-registers and input synchronization.
➢ The D flip flop is also call Delay or Data flip flop.
➢ Truth table and Circuit of D Flip- Flops:
Digital Logic Circuits
Prof. K. Adisesha (Ph. D)
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Clock D Q Q’
↓ » 0 0 0 1
↑ » 1 0 0 1
↓ » 0 1 0 1
↑ » 1 1 1 0
74. T Flip- Flops:
These are basically a single input version of JK flip flop. This flip-flop has only one
input along with the clock input..
➢ The T flip flop is called Toggle flip-flop because of their ability to complement its
state.
➢ Truth table and Circuit of D Flip- Flops:
Digital Logic Circuits
Prof. K. Adisesha (Ph. D)
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Clock T Q
Q
(t+1)
↓ » 0 0 0 0
↑ » 1 1 0 1
↓ » 0 0 1 1
↑ » 1 1 1 0
75. Register in Digital Logic:
The group of flip-flops, which are used to store the binary data is known as register.
➢ If the register is capable of shifting bits either towards right hand side or towards left
hand side is known as shift register.
➢ An ‘N’ bit shift register contains ‘N’ flip-flops.
➢ Types of shift registers based on applying inputs and accessing of outputs:
❖ Serial In − Serial Out shift register
❖ Serial In − Parallel Out shift register
❖ Parallel In − Serial Out shift register
❖ Parallel In − Parallel Out shift register
Digital Logic Circuits
Prof. K. Adisesha (Ph. D)
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76. Counters in Digital Logic:
Counter is a device which stores (and sometimes displays) the number of times a
particular event or process has occurred, often in relationship to a clock signal.
➢ Counters are used in digital electronics for counting purpose, they can count specific
event happening in the circuit.
➢ Counters are broadly divided into two categories:
❖ Asynchronous counter: Also called Ripple counter, it doesn't use universal clock,
only first flip flop is driven by main clock
❖ Synchronous counter: synchronous counter has one global clock which drives
each flip flop so output changes in parallel
Digital Logic Circuits
Prof. K. Adisesha (Ph. D)
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77. Difference between Combinational & Sequential logic circuits:
Digital Logic Circuits
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Combinational circuits Sequential circuits
The circuit whose output, depends only on the
input present at that instant only is known as a
combinational circuit.
The circuit whose output depends not only on
the input present but also on the past output, is
known as sequential circuit
These types of circuits have no memory unit.
These types of circuits have a memory unit to
store the past output.
It is Faster. It is Slower.
These are easy to design. These are difficult to design.
Examples are a half adder, full adder, magnitude
comparator, multiplexer, demultiplexer, etc.
Examples of sequential circuits are flip-flop,
register, counter, clocks, etc.
78. Memory Unit
Prof. K. Adisesha (Ph. D)
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Computer Memory:
A collection of one or more sets of chips that stores data / program instructions, either
temporarily or permanently in silicon chip is called Computer Memory.
➢ Memory chips are classified as:
❖ RAM – Random Access Memory
❖ ROM- Read Only Memory
➢ Based on access time, Memory chips are:
❖ RAM-Random Access Memory
❖ SAM – Sequential Access Memory
79. Memory Unit
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Random Access Memory:
RAM is the main memory in a computer. It is much faster to read from and write to
than other kinds of storage, such as a hard disk drive (HDD), solid-state drive (SSD) or
optical drive.
➢ Random Access Memory is volatile.
➢ Memory chips are classified as:
❖ Static Random Access Memory (SRAM)
❖ Dynamic Random Access Memory (DRAM)
80. Memory Unit
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ROM- Read Only Memory:
ROM is memory containing hardwired instructions that the computer uses when it
boots up, before the system software loads..
➢ ROM is non-volatile, not requiring power to store data.
➢ ROM Memory chips are classified as:
❖ Mask-Programmed Memory (MROM)
❖ Programmable Read Only Memory (PROM)
❖ Erasable PROM (EPROM)
❖ Electrically Erasable PROM (EEPROM)
❖ Electrically Alterable ROM (EAROM)
81. Difference main memory storage units:
Digital Logic Circuits
Prof. K. Adisesha (Ph. D)
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Unit & Description
Bit (Binary Digit): A binary digit is logical 0 and 1 Kilobyte (KB): 1 KB = 1024 Bytes
Nibble: A group of 4 bits is called nibble Megabyte (MB): 1 MB = 1024 KB
Byte: A group of 8 bits is called byte. A byte is the
smallest unit
GigaByte (GB): 1 GB = 1024 MB
Word: A computer word, is a group of fixed number
of bits processed as a unit, which varies from
computer to computer but is fixed for each computer
TeraByte (TB): 1 TB = 1024 GB
PetaByte (PB): 1 PB = 1024 TB
82. Logic IC Families :
A collection of one or more gates fabricated on a single silicon chip is called an
integrated circuit (IC).
❖ RTL: Resistor Transistor Logic
❖ DTL: Diode Transistor Logic
❖ TTL: Transistor-Transistor Logic
❖ ECL: Emitter – Coupled Logic
❖ CMOS: Complementary Metal
Oxide Semiconductor
Logic Integrated Circuits
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83. Logic Integrated Circuits
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Integrated Circuits:
A collection of one or more gates fabricated on a single silicon chip is called an
integrated circuit (IC).
➢ ICs were classified by size:
❖ SSI - small scale integration - 1~20 gates
❖ MSI - medium scale integration - 20~200 gates
❖ LSI - large scale integration - 200~200,000 gates
❖ VLSI - very large scale integration - over 1M transistors
➢ Pentium-III - 40 million transistors
88. Boolean Functions
88
Positive and Negative Logic
The XOR and XNOR gates are commutative and associative.
➢ Positive and Negative Logic
❖ Two signal values <=> two logic values
❖ Positive logic: H=1; L=0
❖ Negative logic: H=0; L=1
Prof. K. Adisesha (Ph. D)