1. ZEYU BU Phone: (737) 834 1792 | Email:zeyubu@umich.edu
Address: 1654 Mcintyre Drive, Ann Arbor, Michigan,48105
OBJECTIVE
Seeking an fulltimeposition as an electrical engineer with a specialization in digital circuitsdesign and verification
EDUCATION
Univer sit y O f Mich igan , An n Ar bo r - Master in Electrical Engineering - Overall GPA: 4.0 - Sept 2014 - Apr 2016
● Courses:VLSI DesignI (427), Computer Architecture (470), Logic Circuit Synthesis& Optimization(478), Digital Integration
Technology(523), Digital System Testing (579).
Sh angh ai Jiao To ng Un ive rsity - Bachelor in Electrical Engineering - Overall GPA: 3.61 - Sept 2010 - July 2014
● Courses: Digital System Simulation& VHDL Design, Embedded SystemTheory& Lab, RF Circuit Design, Analog Electronics
Technology, Digital Electronics Technology.
WORK EXPERIENCE
Inter im En gineer - QualcommTechnologies, Inc.- San Diego, CA - May 2015 - Present
● Got familiar withthe flowof Power Analysis andStatic Timing Analysis byPrime Time, PX(PTPX) and Prime Time, SI (PTSI)
● Used PTPX to analyze the power inanalog and digitalcircuits of DDR PHY
● Run Layout Parasitic Extraction (LPE) byCadence andusedthe result to doSPICE power simulation
● Wrote TCL and Perl to get the Wire VS Cell power byPTPXand SPICE, thencorrelated the result
RESEARCH AND PROJECTS
RTL Design of R10k OoO Microproce ssor with 2-Way Superscalar & Simultaneou s Multithreading
● Designedinstruction cache with prefetching and2-wayassociative non-blocking data cache with victimcache
● Used LocalBranchPredictor, Branch Target Buffer (BTB) and Return Address Stackto reduce the branchmispredictionrate
● Used Load& Store Queue (LSQ)to enable data forwardingand out-of-order load execution
● Achieved average CPI of 1.6 andclock periodof 8.2 ns, whichis the best inthe class
Layo ut Le vel De sign of a Lo w P ower 8 T SRA M
● Got familiar withSRAMdesign and low power technologies.
● Appliedclock gating, innovative Dynamic Voltage Scaling(DVS) mechanism and read process to reduce power consumption
● Assembledan8 Kb 8T SRAMwith memorycell, amplifier and controller
Layout Level Design of a 16 -bit RISC Microproce ssor
● Got familiar withCMOS fabrication technology, NCVerilog and HSPICE simulation
● Finished the schematic and layout designof Register File, Arithmetic Logic Unit, Shifter
● SynthesizedbehavioralVerilogand used automatic placement androuting (APR)with Encounter to generate Program Counter,
Decoder andController
● Assembleda 16 bit pipelined RISCmicroprocessor
Fast Simulation Method of VLSI Interconnect System
● Verifiedthe feasibilityof interconnect temperature distributionandcrosstalkmodels
● Originallyusedthe Laguerre basis functions to better solve heat diffusion equations
● AppliedFDTDandLIMto simulate the voltage and temperature ofinterconnect system
SKILLS
Language: Verilog, VHDL, Perl,Bash,Matlab, C, C++, Java,Python
Application: Cadence, SPICE, Altium Designer, ADS
OS: Windows,Linux, UNIX, Mac OS X