Oindree Basu is pursuing a Master's degree in Electrical and Computer Engineering at Purdue University, having previously earned a Bachelor's degree in Electronics and Communication Engineering from National Institute of Technology Durgapur in India. The document provides details of Basu's education background, research experience including projects on digital circuit design and FPGA implementation of neural networks, as well as technical skills in hardware description languages, software tools, and programming languages.

1. Oindree Basu
obasu@purdue.edu +1 (765)-7759593
Education
PurdueUniversity,WestLafayette August 2019-present
Master of Science GPA: 3.9/4.0
Electrical and Computer Engineering Major: VLSI and Circuit Design
Relevant Coursework: MOS VLSI Design, System-on-Chip Design, Advanced VLSI Design, Computational
Models and Methods, Digital Systems Design Automation
National Institute of Technology Durgapur, India August 2015-June 2019
Bachelor of Technology GPA: 9.20/10.0
Electronics and Communication Engineering
Relevant Coursework: Digital Electronics, Analog Electronics, Introduction to VLSI, Microprocessors and
Microcontrollers, Computer Architecture
Data Structures and Algorithms, Object Oriented Programming
Research Experience
Summer Intern-Indian Institute of Technology Madras
Digital Systems Design Laboratory May 2018-July 2018
GuidedbyProf.VinitaVasudevan
• Developed an algorithm to determine maximum propagation delays of each of the ISCAS ’85 benchmark
circuits using HSPICE simulations.
• The algorithm was able to avoid drawbacks of the STA method of delay calculation (false path
sensitization and overestimation).
Research Assistant- National Institute of Technology Durgapur January 2017-May2019
Guided byDr. Hirok Chaudhuri
• Located anomalies present in a time series representing Rn-222 concentration at Bakreshwar geothermal area
by applying Multifractal Detrended Fluctuation Analysis (MFDFA) using MATLAB.
• Analysed relations between occurrence of anomalies and seismic events around the area.
Projects
Design and Simulation of 4-bit Wallace Tree Multiplier November 2019-December 2019
• Designed a high frequency, area-optimized 4-bit Wallace Tree Multiplier on Cadence Virtuoso and performed
Synthesis and Automatic Place & Route using Cadence Innovus to compare area and power with hand layout.
• Achieved a highest working frequency of 3 GHz with a multiple-stage pipelined design.
Neural Network Inference Acceleration on Altera FPGA October 2019-December 2019
• Accelerated the inference process of two neural networks (MLP & CNN) by designing hardware accelerator
and multi-cycle extended custom instruction and implementing on a Nios II processor based FPGA.
• Achieved a speedup of 6x for MLP and 12x for CNN as compared to baseline software implementation.
Hardware Accelerator and extended Custom Instruction Set for CRC computation September 2019
• Designed a 32-bit hardware accelerator and multi-cycle extended custom instruction for speeding up CRC
computation in MAC protocol.
• Implemented them on a Nios II processor based FPGA and achieved a speed up of 2.85x as compared to the
software implementation.
Analytical Modelling of LDMOSwithaSingle-stepBuriedOxideLayer January 2019-May 2019
Undergraduate Thesis – Guided by Prof. Rajat Mahapatra
• Developed analytical models and studied characteristics for Single-Step Buried Oxide Silicon on Insulator
LDMOS.
• Observed and analysed electric field distribution as a function of thickness and length of the buried oxide,
using MATLAB.
Simulation of ADC, UART with ATmega 16 microcontroller using Proteus December 2016
• Simulated Timer, ADC, UART, Keypad and 7-segment display with Proteus as simulation software and
Embedded C as programming language.
Technical Skills
HDL and Programming Languages: Verilog, C, C++, Bash, Java
Software: HSPICE, MATLAB
Tools: Quartus, Cadence Virtuoso, Cadence Innovus, QuestaSim