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Zhou Yu
601E 32ND ST APT#201 • Chicago, IL 60616 • (312) 340-8556 • zyu27@hawk.iit.edu
https://www.linkedin.com/pub/zhou-yu/106/679/839
PROFESSIONAL SUMMARY
Seeking a hardware design Engineer Position. Major in Electronic Engineering and specializing in hardware design. Strong
experience in VLSI design, computer architecture, image processing, digital signal processing, etc with good research ability.
EDUCATION
ILLINOIS INSTITUTE OF TECHNOLOGY Chicago, IL 2014-2015
Master degree of Electrical Engineering; GPA:4.0/4.0
SOUTH CHINA UNIVERSITY OF TECHNOLOGY Guangzhou, CHN 2009-2013
B.S.E Information Engineering (Electronics and Communications Engineering) GPA:3.0/4.0
RELEVANT COURSES
Signal & Image Processing : Digital Signal Processing, Image Processing
Computer Systems & VLSI : VLSI Introduction with laboratory course , Advanced VLSI Design, Advanced Computer
Architecture, Basic Digital Circuit Design
Electronics & Electromagnetic: Microwave circuits and systems, Nano devices Technology
SKILLS
PROGRAMMING: C, C++, VHDL, MATLAB, VERILOG
OPERATION SYSTEMS: WINDOWS, LINUX
APPLICATIONS: MS OFFICE, VISUAL STUDIO, MATLAB, CADENCE, AUTOCAD, HSPICE, MODLESIM
KNOWLEDGE: SIGNAL PROCESSING, IMAGE PROCESSING, FPGA, VLSI,
EXPERIENCE
CHINA COMSERVICE HUAXIN CONSULTING CO., LTD Hangzhou , CHN 2013-2014
Intern, 3G Design Institute
• Assisted to draw cable routing graphics of the computer room, utilized CAD to complete work in
collaboration with team colleagues
• Helped to revise the proposal for publishing, familiarized with standard format of publications
• Translated a paper (to be published) about communication technology of power grid
PROJECTS
ULTRASONIC SIGNAL ESTIMATION USING T-F DOMAIN ANALYSIS Chicago, IL March.2015-December.2015
• Work in Embedded Computing and Signal Processing Research Laboratory at IIT
• Algorithm design concentrating on signal reconstruction with short-time Fourier transform and Wigner
distribution.
• Writing algorithm for ellipse estimation, which is used for calculating parameters of input signal.(Matlab)
• The algorithm can estimate a signal with 5dB SNR WGN.
SIMULATION OF CPU, CACHE, BUS, AND MEMORY DATA PATH Chicago, IL March.2015-May.2015
• Simulate the basic computer architecture.
• Structure is combined by ALU, Memory, Cache(data and instruction), Bus, Control Unit(FSM).
• RTL design with single cycle MIPS structure, which have 5 stage structure(IF, ID, ALU, MEM, WB).
(VHDL)
• Write a test bench, which provide clock and reset signal(instruction is stored in memory), simulation result
shows the design ran correctly.
ALU COMPONENT DESIGN SIMULATION Chicago, IL November.2014-
December.2014
• Design adder using Carry Ripple Adder, Carry Lookahead Adder, Carry Skip Adder and Carry Select Adder
• Add a comparator to the ALU and write the test bench in Verilog
• Complete the post-synthesis simulation and the post P&R simulation, measure delay of several instructions.
• Under Linux Environment, tool used: Cadence SimVision, Synopsys Design Compiler, Formality ESP, Enconter,
Virtuoso.
OBJECT CLASSIFICATION METHOD Chicago, IL April.2014-May.2014
• Perform segmentation and region labeling of provided set of images about nuts and bolts.
• Implement a Fisher discriminant for these two classes
• Use the discriminant obtained to classify nuts and bolts in a mixed image.
• All complete in Matlab environment
SIMULATION OF AN ANTENNA. Guangzhou, CHN 2013-2013
• an approach based on HFSS software with a conical radiation pattern omni-directional circularly polarized
antenna design simulation program
• Design a 3-D model of the antenna and perform simulation.

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Zhou Yu Resume

  • 1. Zhou Yu 601E 32ND ST APT#201 • Chicago, IL 60616 • (312) 340-8556 • zyu27@hawk.iit.edu https://www.linkedin.com/pub/zhou-yu/106/679/839 PROFESSIONAL SUMMARY Seeking a hardware design Engineer Position. Major in Electronic Engineering and specializing in hardware design. Strong experience in VLSI design, computer architecture, image processing, digital signal processing, etc with good research ability. EDUCATION ILLINOIS INSTITUTE OF TECHNOLOGY Chicago, IL 2014-2015 Master degree of Electrical Engineering; GPA:4.0/4.0 SOUTH CHINA UNIVERSITY OF TECHNOLOGY Guangzhou, CHN 2009-2013 B.S.E Information Engineering (Electronics and Communications Engineering) GPA:3.0/4.0 RELEVANT COURSES Signal & Image Processing : Digital Signal Processing, Image Processing Computer Systems & VLSI : VLSI Introduction with laboratory course , Advanced VLSI Design, Advanced Computer Architecture, Basic Digital Circuit Design Electronics & Electromagnetic: Microwave circuits and systems, Nano devices Technology SKILLS PROGRAMMING: C, C++, VHDL, MATLAB, VERILOG OPERATION SYSTEMS: WINDOWS, LINUX APPLICATIONS: MS OFFICE, VISUAL STUDIO, MATLAB, CADENCE, AUTOCAD, HSPICE, MODLESIM KNOWLEDGE: SIGNAL PROCESSING, IMAGE PROCESSING, FPGA, VLSI, EXPERIENCE CHINA COMSERVICE HUAXIN CONSULTING CO., LTD Hangzhou , CHN 2013-2014 Intern, 3G Design Institute • Assisted to draw cable routing graphics of the computer room, utilized CAD to complete work in collaboration with team colleagues • Helped to revise the proposal for publishing, familiarized with standard format of publications • Translated a paper (to be published) about communication technology of power grid PROJECTS ULTRASONIC SIGNAL ESTIMATION USING T-F DOMAIN ANALYSIS Chicago, IL March.2015-December.2015 • Work in Embedded Computing and Signal Processing Research Laboratory at IIT • Algorithm design concentrating on signal reconstruction with short-time Fourier transform and Wigner distribution. • Writing algorithm for ellipse estimation, which is used for calculating parameters of input signal.(Matlab) • The algorithm can estimate a signal with 5dB SNR WGN. SIMULATION OF CPU, CACHE, BUS, AND MEMORY DATA PATH Chicago, IL March.2015-May.2015 • Simulate the basic computer architecture. • Structure is combined by ALU, Memory, Cache(data and instruction), Bus, Control Unit(FSM). • RTL design with single cycle MIPS structure, which have 5 stage structure(IF, ID, ALU, MEM, WB). (VHDL) • Write a test bench, which provide clock and reset signal(instruction is stored in memory), simulation result shows the design ran correctly. ALU COMPONENT DESIGN SIMULATION Chicago, IL November.2014- December.2014 • Design adder using Carry Ripple Adder, Carry Lookahead Adder, Carry Skip Adder and Carry Select Adder • Add a comparator to the ALU and write the test bench in Verilog • Complete the post-synthesis simulation and the post P&R simulation, measure delay of several instructions.
  • 2. • Under Linux Environment, tool used: Cadence SimVision, Synopsys Design Compiler, Formality ESP, Enconter, Virtuoso. OBJECT CLASSIFICATION METHOD Chicago, IL April.2014-May.2014 • Perform segmentation and region labeling of provided set of images about nuts and bolts. • Implement a Fisher discriminant for these two classes • Use the discriminant obtained to classify nuts and bolts in a mixed image. • All complete in Matlab environment SIMULATION OF AN ANTENNA. Guangzhou, CHN 2013-2013 • an approach based on HFSS software with a conical radiation pattern omni-directional circularly polarized antenna design simulation program • Design a 3-D model of the antenna and perform simulation.