1. EE27
Project Title: Electrical characterization of semiconductor-insulator
interfaces in VLSI/ULSI technology
by
Dang Mai Trang1
1
NUS High School of Mathematics and Science
Teacher Advisor
Ms. Li Lina1
1
NUS High School of Mathematics and Science
External Mentors
Dr. Singh Navab2
and Shen Nansheng2
2
Institute of Microelectronics, A*STAR
Date: 26th
November 2009
100 words summary of the project
Metal-Oxide-Silicon (MOS) structures are fabricated using high dielectric constant (k-value)
hafnium oxide ( ) in combination with tantalum nitride as metal. The use of high-k
dielectric instead of normal material with k-value of 3.9, is to increase the gate
capacitance without reducing gate dielectric thickness, a requirement of scaling down the
device size. Including SiO2/Poly-silicon reference wafers, six 8” silicon wafers were fabricated
with varied dielectric thickness. Each of them contains different sizes capacitor and contact
area. After taking into account the fringing effect and leakage current through the dielectric
layer, the experimental k-value of HfO2 was found to be 19.35567345, very close to the
reported k-value of 18-25. This technology can be applied to decrease the size of capacitors to
about 5x while keeping the capacitance unchanged hence can build more capacitors/transistors
in one computer chip to increase the amount of information stored and computer speed.

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Electrical characterization of semiconductor-insulator interfaces in VLSI/ULSI technology
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Abstract
Capacitance-voltage (C-V) characterization was done on silicon dioxide (SiO2)
and high-k hafnium oxide (HfO2) gate dielectric MOS capacitors. This paper discusses on
the effects of different gate dielectric thicknesses, capacitor areas, metal contact areas and
fringing effects, on overall capacitor performance.
Based on physical thickness of the fabricated Metal-Oxide-Silicon (MOS)
capacitor, the k-value for SiO2 is extracted and compared with 3D simulations in such a
way that the measured data matches with the ideal C-V curves. This method of k-value
extraction without any accompanying equivalent oxide thickness (EOT) has never been
presented before. This EOT determination method provides an important basis for future
high-k dielectric device characterization.
Fixed oxide charges and dielectric interface charges were studied using C-V
measurement as a diagnostic tool. Fixed oxide charges were found to shift the flat-band
voltage as seen in the gathered C-V measurements and also from simulation results. Net
interface charge was found to change from positive to negative as gate voltage sweeps
from accumulation to inversion condition. Compared to SiO2, HfO2 was found to have
suffered severely from interface charge trapping.
1. Background
The device-scaling concept has driven transistors miniaturization for over the past
few decades. MOS performance is based on its channel length and width, gate capacitance,
contact resistances to name a few. In order to improve metal–oxide–semiconductor field-effect
transistor (MOSFET) performance, gate oxide is required to be as thin as possible. However the
continuous scaling of MOSFETs with the improvement of technology has led us to deposit gate
silicon dioxide gate dielectrics in Armstrong thicknesses. Although device current is increased,
other issues such as gate leakage current or reliability problems such as gate dielectric
breakdown have surfaced.
High-k dielectrics is known and demonstrated to be a promising replacement for
silicon dioxide gate dielectric, for its high-k value allows thicker dielectric thickness to be used,
while at the same time not compromising device performance.

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2. Purpose of Research
While it is known that the advantages of high-k dielectrics, the lack of data has
prevented us from fabricating promising MOSFET devices having high-k dielectric layer. In
this project, the student is guided on fabricating MOS capacitors with various high-k
thicknesses. To have a complete comparison, conventional MOS capacitors with silicon
dioxide are also fabricated. Complete characterization with the means of C-V measurements is
required finally. This would allow accurate extraction of the effective fabrication.
In this project, HfO2 is used as the high-k dielectric material to be characterized.
The reported effective k-value is 18-25. The k-value for SiO2 has been extensively researched
and found to be a stable value of 3.9. Such is the large difference between the two materials. To
further understand the importance of high-k dielectric, the capacitance-dielectric thickness
relation is presented:
Cdielectric =
εo × k
tdielectric
Cdielectric =
εo × k
tdielectric
where Cdielectric is the capacitance of the dielectric, is the permittivity of free space (8.85 x
10‐12 F/m), k is the dielectric constant and tdielectric is the thickness of the dielectric layer.
In MOS capacitor or transistor fabrication, a thinner dielectric layer (smallertdielectric ) would
result in a larger capacitance, which contributes to better device characteristics. However,
thinner dielectric would also lead to reliability issues and fabrication difficulties. Therefore a
simpler method of improving the capacitance is to use high-k dielectrics.
Supposing, hypothetically, we have SiO2 (k = 3.9, tSiO2 = 10nm) and HfO2 (k = 25),
with the same capacitance such that:
CSiO2 =CHfO2
⇔
ε0 × kSiO2
tSiO2
=
ε0 × kHfO2
tHfO2
⇔
kSiO2
tSiO2
=
kHfO2
tHfO2
⇒ tHfO2
=
kHfO2
kSiO2
× tSiO2
⇒ tHfO2
=
25
3.9
×10nm ⇒ tHfO2
= 64nm
This means that the thickness of HfO2 dielectric layer can be at least 6
times thicker than conventional SiO2 dielectric layer. Also, if with the same dielectric layer
thickness, HfO2 dielectric MOS capacitor can obtain a capacitance of at least 6 times larger
than conventional SiO2 dielectric MOS capacitor, thus underlining the importance of high-k
dielectrics.

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3. Hypothesis
We hypothesize that using a high-k value material in fabricating the dielectric
capacitor will help to reduce penetrating current hence increase the efficiency of the capacitor
while the capacitance is kept constant.
4. Experiment
There are two main parts to this project, one part being the fabrication of MOS
capacitors and the other part being the characterization of fabricated MOS capacitors. First we
would fabricate standard dielectric thickness SiO2 dielectric and high-k dielectric MOS
capacitors. From these devices, we will be able to extract some information on dielectric
constants of the fabricated devices and change the dielectric thickness of the next MOS
capacitor to be fabricated. This works out to be a feedback loop, where results are fed back and
implemented back into the process cycle for optimization.
Here we will highlight the fabrication of silicon dioxide dielectric MOS capacitor
and high-k dielectric MOS capacitor:
a. Silicon Dioxide MOS capacitor
Starting with silicon p-type doped test-wafers, the wafers are sent for pre-gate
oxidation clean. This clean is intended to remove any native oxide due to exposure to the
atmosphere and to remove the particles that may contaminate the furnace during processing.
Next would be the growth of the SiO2 dielectric, also known as gate oxidation. Here, two
methods can be used to grow the required SiO2. One being growth by furnace and the other is
Rapid Thermal Oxidation (RTO). Difference between the two is that furnace has slow ramp up
rate, and rapid thermal oxidation is a very much shorter process. Both of these methods will be
implemented in this project.
Upon growth of the SiO2 dielectric, amorphous silicon is deposited in the furnace.
This is the gate layer which will act as the metal in a MOS capacitor, although amorphous
silicon is not a metal. Amorphous silicon by itself is non-conductive; therefore it has to be
implanted with Phosphorous dopants. Implantation is followed by activation of the dopants to
free conductive electrons from their rigid atomic structure. The capacitor is next defined

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through capacitor lithography by spinning a layer of photo resist and exposure with the
prepared mask. In this mask set, there will be three sets capacitors. In each set, there are nine
capacitors with sizes ranging from 10µm by 10µm to 100µm by 100µm squares. Difference
between these three sets of capacitors is the contact-hole design between the gates to the metal
layer. One set of capacitors has one contact-hole each, one set has four contact-holes each and
one set has a long contact-hole each.
After capacitor lithography, the amorphous silicon is dry-etched and the capacitor
is defined. A layer of thick pre-metal deposition (PMD) oxide is deposited on top of the
capacitors to serve two purposes: one is to provide a layer of protection, and the other is to
provide isolation with metal lines. Upon deposition of the PMD layer, contact lithography is
carried out followed by contact hole dry etch. These contact holes are designed to be 2µm by
2µm squares. Next would be metal layer deposition followed by metal line lithography. The
last process would be the metal definition by dry etching. The device is ready for
characterization now.
b. High-K Dielectric MOS capacitor
In this project, the high-k material used is HfO2. The reported k-value is around 18-
25. By comparison, the k-value for SiO2 is 3.9. The fabrication of high-k dielectric MOS
capacitor is very similar to that of SiO2 MOS capacitor. Main difference is the different type of
material used.
Starting with the same type of silicon p-type doped test-wafers, HfO2 is deposited
using Plasma Vapor Deposition (PVD) systems. Next the metal gate is deposited using the
same machine with tantalum nitride (TaN). The following steps such as capacitor lithography,
contact hole etch and metal etch are the same as those for SiO2 MOS capacitor fabrication.
5. Results and Discussion:

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Fig.1: 4-Contact Capacitor viewed from 45 degree.
The data of 4-contact capacitor is used for the entire calculations in this report.
For the first three wafers, the effect of current trapped at the surface is negligible
due to the similarity between 2 materials. Therefore fringing effect and leakage current are the
greatest impact on the capacitors. Let us denote “fringe” of the capacitance have the width of
x , the total fringing area is given by this formula 4ax + πx2
where a is the side length of a
particular capacitor. Solving a series of equation
Ca
a2
+ 4ax + πx2
=
Cb
b2
+ 4bx + πx2
where
a,b combinations are as the table below
a ( µm ) 50 50 50 50 60 60 60 70 70 80
b ( µm ) 60 70 80 100 70 80 100 80 100 100
are the capacitance measured of those respective sizes. After finding x , all Cox are
normalized, encountering the effect of current leakage. k-value of SiO2 is calculated to be
3.898982967, which is very close to the theoretical value of 3.9-4.0. Similar method is applied
to wafer 100A and 40A RTO, the k-value were found to be 4.060962466 and 3.939331101

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respectively. These results show that without current trapped, the impact of fringing effect
outweighs other factors we may encounter.
Fig. 2: Normalized C-V graph of 40Å SiO2 . The 4 graphs match completely.
For high-k dielectric material, current trapped is not negligible. It contributes
significantly in calculating k-value. The graph below shows the current trapped on wafer 7 –
250Å HfO2 .
Fig. 3: Graph of interface trapped vs. voltage swept through 250Å HfO2 .

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Instead of calculating x value of fringing effect directly, we need to find the effect
of current trapped first then find x . Unlike the previous wafers, the current leaked through the
capacitor is negligible in this case.
Voltage sweeps through the capacitor every 30ms, or 0.03s. Taking
Current × Time
Voltage × Area
+
Cox
Area
we will have the capacitance over area. This is applied to the data of
50µm x 50µm capacitor and 100µm x100µm capacitor to normalize the graphs.
Fig. 4: The normalized C-V graph of 250A HfO2 . The graphs match well as Voltage change
from -15V to -12V. This is during accumulation period.
Fringing effect was calculated x = 2.87549µm using similar method of SiO2 wafer.
k =
Cox × Thickness
εo
= 20.28640397.
A similar method is applied for wafer 6 – 100Å, the x value obtained is 1.7309µm
and the k − valuefound is 19.35567345. Take the average value, we obtain k=19.35567345,
which is adequately acceptable compare to the theoretical value of k from 18 to 25.

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Fig. 5. Normalized C-V graph of 100Å HfO2 .
6. Conclusion
By using the high-k HfO2 , we can increase the thickness of the dielectric layer
while keeping the same value of capacitance. By increasing the thickness, the amount of
current leaked through the dielectric layer was minimized. The calculated k-values match with
the theoretical value, which shows that the method of fabricating and characterizing are suitable
for further researching in future. The fringing effect, current leakage and interface trapped are
also encountered to get the best result.
The only disadvantage of using HfO2 is that it attracts the charges on the surface
due to the change in bonding structure of Si and HfO2 .
7. Further Improvement
To avoid this to happen again, the combination of Si (the wafer),SiO2 thin layer and
HfO2 layer will be laid together. A series of combined dielectric layer are in process of
fabricating but due to the condition of equipment, they cannot be finished on time for the report
submission. Once those wafers are done, we will have chance to compare directly the effect of
interface trapped.

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Reference
1. Ben G. Streetman. Solid State Electronic Devices, 6th
Edition. Prentice Hall 1995.
2. Betty Lise Anderson and Richard L. Anderson. Fundamentals of semiconductor
devices. McGraw-Hill Professional, 2005.
3. David J. Roulston. An introduction to the physics of semiconductor devices. Oxford
University Press, 1999.
4. Donald A. Neamen. Semiconductor Physics and Devices – Basic Principles, 3rd
Edition. McGraw-Hill Professional, 2003.
5. Jean-Pierre Colinge and Cynthia A. Colinge. Physics of semiconductor devices.
Springer, 2002.
6. S M Sze. Semiconductor Devices: Physics and Technology, 2nd Edition. John Wiley
& Sons 2001.
7. Y.-Y. Fan, S. Mudanai, W. Qi, J. C. Lee, A. F. Tasch, L. F. Register, and S. K.
Banerjee, Modeling High K Gate Current from p-type Si Inversion Layers.
Microelectronics Research Center, The University of Texas at Austin, R9950, Austin,
TX 787582.
Statement of contribution
Dr. Navab Singh came up with the initial ideas for this research and Mr. Shen
Nansheng and I worked together to finalize the details of the research. Mr. Shen Nansheng and
I carried out all of the experimental work and the numerical analysis. Dr. Navab Singh
provided assess to the institute’s equipment. Mr. Shen Nansheng assisted me with the
experiments. All authors discussed the results and commented on the manuscript.
Acknowledgement
I would like to thank Dr. Navab Singh to provide me this project and thank him for
his wonderful advices every time I encounter the difficulties.
Besides, I would like to thank Mr. Shen Nansheng – my direct mentor of the project
– for accompanying me along with the project all the time and teaching me the specific

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knowledge that I have not learnt in school. Without him, the project will never been processed
and completed.
Also, I would like to thank Ms. Li Lina – my school mentor – for taking care of my
project and me. She has always been a great teacher who always shows care and always
reminds me of the deadlines for submission.
Lastly yet importantly, I would like to thank Institute of Microelectronic, A*STAR
for providing the opportunity to do the research for 5 months with the full privilege of an
attaché. Also, I would like to thank my school – NUS High School – for being a great support.