1. A Seminar on
Semiconductor
Guided By:-
Name:-
memories
Submitted By:-
Name:- Shakti Prasad Dash
Regd. No. :- 1121221008
Branch:- Electronics &
Telecommunication Engg.

2. OVERVIEW
1) Introduction
2) Requirements
3) Configuration of Memory Chip
4) Semiconductor memory classification
5) Periphery
 Decoders
 Sense Amplifiers
 Input/output Buffers
 Control Timing Circuitry
6) Reliability & Yield
7) Conclusion

3. introduction
1. Data storage essential for processing.
2. Binary storage.
3. Switches.
4. Random & Efficient access to all memory location.
5. Data access is fast so less data access time.
6. Data accessed by means of binary memory address
applied to chip’s address pins.
'0'
'1'
Read
Write

4. Requirements
1. Easy reading.
2. Easy Writing.
3. High density.
4. Speed, more speed and still more speed.
5. Bulkier data processing.
6. Minimizing the amount of error.

5. Memory Chip
Configuration
RowDec
Memory Cell Array
Row Address
N bits
Complete Address
N+M Bits
2
M
Cells
Din
Dout
I/O Control
din
dout
Column Dec.
2
N
Cells
WL
DL
Cell
Control
Signals
I/OInterface
Column Address
M Bits

6. Semiconductor Memory
Classification
Read-Write Memory
Non-Volatile
Read-Write
Memory
Read-Only Memory
EPROM
E2
PROM
FLASH
Random
Access
Non-Random
Access
SRAM
DRAM
Mask-Programmed
Programmable (PROM)
FIFO
Shift Register
CAM
LIFO

7. RAM
1. Random write and read operation for any cell
2. Volatile data
3. Most of computer memory
4. DRAM
 Low Cost
 High Density
 Medium Speed
5. SRAM
 High Speed
 Ease of use
 Medium Cost

8. 1-Transistor DRAM Cell
CS
M1
BL
WL
CBL
WL
X
BL
VDD VT
VDD/2
VDD
GND
Write "1" Read "1"
sensing
VDD/2
V VBL VPRE– VBIT VPRE–
CS
CS CBL+
------------------------= =
Write: CS is charged or discharged by asserting WL and BL.
Read: Charge redistribution takes places between bit line and storage capacitance
Voltage swing is small; typically around 250 mV.

9. 6-transistor CMOS SRAM Cell
VDD
Q
Q
M1 M3
M4M2
M5
BL
WL
BL
M6

10. ROM
1. Non-volatile Data
2. Method of Data Writing
3. Mask ROM
 Data written during chip fabrication
4. PROM
 Fuse ROM: Non-rewritable
 EPROM: Erase data by UV rays
 EEPROM: Erase and write through electrical means
o Speed 2-3 times slower than RAM
o Upper limit on write operations
o Flash Memory – High density, Low Cost

11. Examples of ROM
Fuse ROM EEPROM
WL
DL
WL
DL
Floating Gate

12. Characteristics of Different NVM

13. Non-Volatile Memories
The Floating-gate transistor
(FAMOS)
Floating gate
Source
Substrate
Gate
Drain
n+ n+_
p
tox
tox
Device cross-section Schematic symbol
G
S
D

14. Floating-Gate Transistor
Programming
0 V
- 5 V 0 V
DS
Removing programming
voltage leaves charge trapped
5 V
- 2.5 V 5 V
DS
Programming results in
higher VT.
20 V
10 V 5 V 20 V
DS
Avalanche injection

15. Periphery
 Decoders
 Sense Amplifiers
 Input/output Buffers
 Control / Timing Circuitry

16. Row Decoders
Collection of 2M complex logic gates
Organized in regular and dense fashion
(N)AND Decoder
NOR Decoder

17. Hierarchical Decoders
• • •
• • •
A 2A 2
A 2A 3
WL 0
A 2A 3A 2A 3A 2A 3
A 3 A 3A 0A 0
A 0A 1A 0A 1A 0A 1A 0A 1
A 1 A 1
WL 1
Multi-stage implementation improves performance
NAND decoder using
2-input pre-decoders

18. Sense Amplifiers
tp
C V
Iav
----------------=
make V as small
as possible
smalllarge
Idea: Use Sense Amplifer
outputinput
s.a.
small
transition

19. Sense Amplifiers Operation
DV (1)
V(1)
V (0)
t
VPRE
V BL
Sense amp activated
Word line activated

20. Differential Sense Amplifier
Directly applicable to
SRAMs
M4
M1
M5
M3
M2
VDD
bitbit
SE
Outy

21. Latch-Based Sense Amplifier
VDD
BL
SE
SE
BL
EQ
Initialized in its meta-stable point with EQ
Once adequate voltage gap created, sense amp enabled with SE
Positive feedback quickly forces output to a stable operating point.

22. Reliability and Yield

23. CONCLUSION
 Use of microprocessor controlled items has
increased with time, so the requirement of
semi conductor memory has increased.
 It is the additional driver, that has made the
software associated with computers more
sophisticated .

24. REFERENCES
1) Sedra & Smith, Microelectronic Circuits, 4th
Edition, Chapter 13
– Section 13.9, 13.10, 13.11, 13.12
2) VLSI Memory Chip Design, Kiyoo Itoh

25. THANK’S
FOR
PATIENCE
HEARING
ANY QUERY??