EC6601 - VLSI Design Question bank Anna University

1. The Kavery Engineering College,
Mecheri, Salem District.
DEPARTMENT RECORDS
DOC.NO. :
TKEC/ECE/ACADEMIC/9
DEPARTMENT OF ELECTRONICS AND
COMMUNICATION ENGINEERING
ACADEMIC YEAR: 2016 - 2017
DATE : 19.12.0216
PAGE : OF 10
YEAR/SEM/SEC: III / VI / -
QUESTION BANK
SUBJECT CODE & NAME: EC6601 – VLSI DESIGN STAFF INCHARGE:
UNIT - I (TWO MARKS)
S.NO QUESTIONS
REMARKS
1. Draw the DC transfer characteristics of CMOS transistor.
Apr / May-2015
Nov / Dec-2013
2. Define lambda based design rules used for layout. Apr / May-2015
3. What is meant by body effect? Nov / Dec-2015
4. What is the need for design rules? Nov / Dec-2013
5. What are the non-ideal I-Veffects? May / June-2014
6. Discuss any two layout rules. May / June-2014
7. Define lambda layout rules May / June 2013
8. Draw four characteristics of MOS transistor. May / June 2012
9. Brief the different operating region of MOS system May / June 2012
10.
Why the tunneling current is higher for NMOS transistor than PMOS transistors with
silica gate?
Nov/Dec -2012
11. What is objective of layout rules? Nov/Dec -2012
12. Draw the band diagram of the components that makeup the MOS system Apr / May -2011
13. What is the body effect coefficient? Apr / May -2011
14.
Determine whether an NMOS transistor with a threshold voltage of O.7 V is
operating in the saturation region if =2v and Vds=3v
Nov/Dec -2011
15.
Write down the equation for describing the channel length modulation effect in the
NMOS transistors.
Nov/Dec -2011
16. Compare nMOS and pMOS transistor.
17. Summarize the different types of scaling technique.
18. Illustrate latch up condition in CMOS circuits? How to prevent it?
19.
What is stick diagram? Sketch the stick diagram for 2 input NAND
gate.
20.
Implement a 2:1 Mux using pass transistor
Apr / May-2015

2. The Kavery Engineering College,
Mecheri, Salem District.
DEPARTMENT RECORDS
DOC.NO. :
TKEC/ECE/ACADEMIC/9
DEPARTMENT OF ELECTRONICS AND
COMMUNICATION ENGINEERING
ACADEMIC YEAR: 2016 - 2017
DATE : 19.12.0216
PAGE : OF 10
YEAR/SEM/SEC: III / VI / -
QUESTION BANK

3. The Kavery Engineering College,
Mecheri, Salem District.
DEPARTMENT RECORDS
DOC.NO. :
TKEC/ECE/ACADEMIC/9
DEPARTMENT OF ELECTRONICS AND
COMMUNICATION ENGINEERING
ACADEMIC YEAR: 2016 - 2017
DATE : 19.12.0216
PAGE : OF 10
YEAR/SEM/SEC: III / VI / -
QUESTION BANK
UNIT - I (SIXTEEN MARKS)
S.NO QUESTIONS
REMARKS
1.
Explain the DC transfer characteristics CMOS inverter [16- mark]
Apr / May-2015
2.
Explain in detail with neat diagram the steps involved in the fabrication of n-well
process. [16-Mark]
Apr / May -2015
3.
(i) Derive drain current of MOS device in different operating regions [10 -Marks]
(ii) Describe with neat diagram the well and channel formation in CMOS process.
[6-Marks]
Nov / Dec -2014
4.
(i). Describe on CMOS process enhancements. [8-Marks]
(ii). With the processing steps involved, explain copper dual damascene interconnect.
[8-Marks]
Nov / Dec -2014
5. Discuss CV characteristics and dc characteristics of the CMOS. [16- Marks] May / June 2014
6.
Briefly discuss about the CMOS process enhancements and layout design rules.
[16- Marks]
May / June 2014
7. Explain the electrical properties of MOS transistor in detail. [16- Marks] Nov / Dec -2013
8.
Derive an expression of Vin of a CMOS inverter to achieve the condition Vin = Vout.
What should be the relation for βn=βp. [16 - Marks]
Nov / Dec -2013
9.
Explain in detail about the I-V characteristics and non- ideal I-V characteristics of a
NMOS and PMOS devices [16 - Marks] May / June 2013
10.
Explain in detail about the body effect and its effect in NMOS and PMOS devices
[8 - Marks]
Derive the expression for DC transfer characteristics of CMOS INVERTER
[8 - Marks]
May / June 2013

4. The Kavery Engineering College,
Mecheri, Salem District.
DEPARTMENT RECORDS
DOC.NO. :
TKEC/ECE/ACADEMIC/9
DEPARTMENT OF ELECTRONICS AND
COMMUNICATION ENGINEERING
ACADEMIC YEAR: 2016 - 2017
DATE : 19.12.0216
PAGE : OF 10
YEAR/SEM/SEC: III / VI / -
QUESTION BANK
UNIT - II (TWO MARKS)
S.NO QUESTIONS
REMARKS
1. State the types of power dissipation. Apr / May -2015
2. Define scaling. What is the advantage of scaling? Apr / May -2015
3.
Give the expression for Elmore delay and state the various parameters associated with
it.
Nov / Dec -2014
4. List different types of scaling. Nov / Dec -2014
5. Define transistor sizing problem. May / June-2014
6. What do you mean by design merging May / June -2014
7. Define power dissipation. Nov / Dec -2013
8. Define scaling. Mention the types of scaling Nov / Dec -2013
9. What is mean by design merging? May / June -2013
10. How do you define the term “Device Modelling”? May / June -2013
11. Draw the equivalent circuit structure of level-1 MOSFET model spice. May / June -2012
12. Brief about the variation fringing field factor with the interconnect geometry May / June -2012
13.
Give the effect of supply voltage and temperature variation on the CMOS system
performance.
Nov / Dec -2012
14. What are the factors that cause static power dissipation in CMOS circuits? Nov / Dec -2012
15. What is the influence of voltage scaling on power and delay? Apr / May – 2011
16. Express Tphl and Tplh in terms of . Apr / May – 2011
17. Write the expression for the logical effort and parasitic delay of n input NOR gate Nov / Dec -2011
18. Why does interconnect increase the circuit delay. Nov / Dec -2011
19. Write the threshold voltage equation for nMOS and for pMOS transistor?
20. Design a 3 input NAND gate.

5. The Kavery Engineering College,
Mecheri, Salem District.
DEPARTMENT RECORDS
DOC.NO. :
TKEC/ECE/ACADEMIC/9
DEPARTMENT OF ELECTRONICS AND
COMMUNICATION ENGINEERING
ACADEMIC YEAR: 2016 - 2017
DATE : 19.12.0216
PAGE : OF 10
YEAR/SEM/SEC: III / VI / -
QUESTION BANK
UNIT - III (TWO MARKS)
UNIT - II (SIXTEEN MARKS)
S.NO QUESTIONS
REMARKS
1.
Explain the various techniques to reduce static and dynamic power dissipation.
[10- Marks]
Derive an expression for the NMOS inverter pair delay whose transistor size is 4:1.
[6- Marks]
Apr / May - 2015
2.
Derive an expression for the rise time, fall time and propagation delay of CMOS
inverter. [16- Marks] Apr / May - 2015
3.
Derive expressions for effective resistance and capacitance estimation using RC delay
models [8- Marks]
Discuss on transistor and inter connect scaling [8- Marks]
Nov / Dec -2014
4.
Derive the final expressions and explain path logical effort, path electrical effort, path
effort and branching effort. [8- Marks ]
Size the transistor of CMOS three input NAND gate for logic ratio of 3/1.
[8- Marks]
Nov / Dec -2014
5.
Explain the following [16- Marks]
(a) Device models and device characterization
(b) Power dissipation in CMOS circuits
May / June - 2014
6.
(a) Describe the simulation of circuit inter connects [8 - Marks]
(b) Write about spice based circuit simulation. [8 - Marks] May / June - 2014
7.
Derive an expression for the rise time ,fall time and propagation delay of a CMOS
inverter. [16- Marks] Nov / Dec -2013
8.
Explain the various ways to minimize the static and dynamic power dissipation.
[16- Marks]
Nov / Dec -2013
9.
Explain in detail about the scaling concept and reliability concept. [8 - Marks]
Describe in detail about the transistor sizing for the performance in combinational
networks. [8 - Marks]
May / June - 2013
10.
Discuss in detail about the resistive and capacitive delay estimation of a CMOS
inverter circuit. [16- Marks]
May / June - 2013

6. The Kavery Engineering College,
Mecheri, Salem District.
DEPARTMENT RECORDS
DOC.NO. :
TKEC/ECE/ACADEMIC/9
DEPARTMENT OF ELECTRONICS AND
COMMUNICATION ENGINEERING
ACADEMIC YEAR: 2016 - 2017
DATE : 19.12.0216
PAGE : OF 10
YEAR/SEM/SEC: III / VI / -
QUESTION BANK
S.NO QUESTIONS
REMARKS
1.
Design a 1 transistor DRAM cell. Apr / May -2015
2.
What is complementary pass transistor logic? state its advantages over CVSL Nov / Dec-2014
3.
Differentiate latch and flip-flop Nov / Dec -2014
4.
What are synchronizers? May / June-2014
5.
State any two criteria for low power logic design? May / June -2014
6.
Design a 1bit dynamic register using pass transistor. Nov / Dec -2013
7.
Implement a 2:1 Mux using pass transistor Nov / Dec -2013
8.
Enumerate the features of synchronizers May / June -2013
9.
List the various power losses in CMOS circuits. May / June -2013
10. Compare CMOS combinational logic gates with reference to the equivalent NMOS
depletion load gates with reference to the area requirement.
May / June -2012
11.
What are the advantages of using a pseudo NMOS gate instant of a full CMOS gate May / June -2012
12.
State the reasons for the speed advantage of CVSL family. Nov / Dec -2012
13.
Mention the qualities of an ideal sequencing method Nov / Dec -2012
14.
Draw the circuit diagram of a CMOS Bi-stable element and its time domain behavior. Apr / May -2011
15.
Write a note on CMOS transmission gate logic. Apr / May -2011
16.
Draw a pseudo NMOS inverter. Nov / Dec -2011
17.
What are the advantages of differential flip-flops? Nov / Dec -2011
18.
Explain simple synchronizer circuit.
19.
Summarize the operation modes of NORA logic.
20.
Determine the property of clock overlap in the registers.

7. The Kavery Engineering College,
Mecheri, Salem District.
DEPARTMENT RECORDS
DOC.NO. :
TKEC/ECE/ACADEMIC/9
DEPARTMENT OF ELECTRONICS AND
COMMUNICATION ENGINEERING
ACADEMIC YEAR: 2016 - 2017
DATE : 19.12.0216
PAGE : OF 10
YEAR/SEM/SEC: III / VI / -
QUESTION BANK
UNIT - III (SIXTEEN MARKS)
S.NO QUESTIONS
REMARKS
1. (i) Explain the sequencing methods of Flip flops and latches. [10 Marks]
(ii) Write short notes on Pulsed latches and its timing metrics. [6 Marks]
2.
(i) Discuss in detail about the synchronous and asynchronous pipelining concepts
used in sequential circuits. [10 Marks]
(ii) Explain briefly the concept of NORA CMOS pipelined structures. [6 Marks]
3. List the methodology of sequential circuit design of latches and flip-flops and
Explain it. [16 Marks]
4.
i) What are the Klass semi dynamic flip flops and differential Flip flops? [8 Marks]
ii) Illustrate the problem of meta stability and its expressions with neat diagrams.
[8 Marks]
5.
i) Design a D-latch using transmission gate. [8 Marks]
ii) Evaluate a 1-bit dynamic inverting and non-inverting register using pass transistor.
[8 Marks]
6.
i) Draw and explain the operation of conventional CMOS pulsed and resettable
latches. [8 Marks]
ii) Write a brief note on sequencing dynamic circuits. [8 Marks]
7.
i) Compare the sequencing in traditional Domino and Skew tolerant Domino circuit
with neat diagrams. [8 Marks]
ii) Illustrate a floating gate transistor and its programming methodology. [8 Marks]
8. i) Describe in detail about memory architectures and its building blocks. [10 Marks]
(ii) Explain in detail about 4T and 6T SRAM Cell structures. [6 Marks]
9.
Give a brief note on:
(i) CMOS 4T and 6T - SRAM cell [8 Marks]
(ii) Dynamic RAM cell. [8 Marks]
10.
i) Consider a flip flop built from a pair of transparent latches using non overlapping
clocks. Determine the set-up time, hold time and clock-to-Q-delay of the flip flops in
terms of the latch timing parameters and t non-overlap. [8 Marks]
ii) Design a 2 input CVSL AND/NAND gate and a 3 input CVSL OR/NOR gate.
[8 Marks]

8. The Kavery Engineering College,
Mecheri, Salem District.
DEPARTMENT RECORDS
DOC.NO. :
TKEC/ECE/ACADEMIC/9
DEPARTMENT OF ELECTRONICS AND
COMMUNICATION ENGINEERING
ACADEMIC YEAR: 2016 - 2017
DATE : 19.12.0216
PAGE : OF 10
YEAR/SEM/SEC: III / VI / -
QUESTION BANK
UNIT - IV (TWO MARKS)
S.NO QUESTIONS
REMARKS
1. Design a logic to reduce the number of generated partial products by
half for Multiplication.
2.
Describe Vector merging adder.
3.
What is Wallace tree multiplier?
4.
Give a note on barrel Shifters.
5. Create a partial product selection table using modified booth’s
recoding.
6.
Identify the Arithmetic circuits in the design of processors.
7. Compare constant throughput/latency and variable throughput latency
in active & leakage mode.
8.
List the Advantages of dual supply approach.
9.
Analyze the Dynamic voltage scaling and list its advantages.
10.
List the uses of Clock gating?
11. Create a schematic for Sleep transistors used on both supply and
ground.
12.
Compare DVS & DTS.
13.
Explain Bit sliced data path organization.
14.
Explain the inverting property of full adder.
15.
Illustrate Clock delayed domino logic?
16.
What are the Arithmetic structures derived from a full adder?
17.
Examine Power minimization techniques in design and sleep mode.
18.
Define Clustered voltage scaling technique.
19.
Give a neat sketch on Manchester carry gates.
20.
Explain the Concept of logarithmic look-ahead adder.

9. The Kavery Engineering College,
Mecheri, Salem District.
DEPARTMENT RECORDS
DOC.NO. :
TKEC/ECE/ACADEMIC/9
DEPARTMENT OF ELECTRONICS AND
COMMUNICATION ENGINEERING
ACADEMIC YEAR: 2016 - 2017
DATE : 19.12.0216
PAGE : OF 10
YEAR/SEM/SEC: III / VI / -
QUESTION BANK
UNIT - IV (SIXTEEN MARKS)
S.NO QUESTIONS
REMARKS
1.
(i) Describe ripple carry adder and derive the worst case delay
with example. [12 Marks]
(ii)Describe the inversion property of full adder. [4 Marks]
2.
Classify circuit design considerations of full adder and explain
i) Mirror adder [8 Marks]
ii) Transmission gate adder [8 Marks]
3.
List the logic design considerations of binary adder and explain
i) Carry skip adder [8 Marks]
ii) Carry save adder [8 Marks]
4. Illustrate the concepts of monolithic and logarithmic look-ahead adder.
[16 Marks]
5.
Define shifter and give a short note on
i) Barrel shifter [8 Marks]
ii) Carry save multiplier [8 Marks]
6.
(i) Demonstrate how to reduce the number of generated partial products by
half. [8 Marks]
(ii) Show the method to accumulate partial products in array form. [8 Marks]
7.
(i) Design the arithmetic logic unit (ALU) of 64 bit high end microprocessor
and arithmetic operators involved in design. [12 Marks]
(ii) Give a short note on Logarithmic shifter. [4 Marks]
8. (i)Summarize the methods involved in run time power management. [12 Marks]
(ii)Compare the difference between DVS and DTS. [4 Marks]
9.
(i)Explain the implementation of a look ahead adder in dynamic logic.
[10 Marks]
(ii)Explain the advantages of Carry bypass adder compared to other adders.
[6 Marks]
10. (i) Give a note on linear carry select adder. [10 Marks]
(ii) Discuss the data paths in digital processor architectures. [6 Marks]

10. The Kavery Engineering College,
Mecheri, Salem District.
DEPARTMENT RECORDS
DOC.NO. :
TKEC/ECE/ACADEMIC/9
DEPARTMENT OF ELECTRONICS AND
COMMUNICATION ENGINEERING
ACADEMIC YEAR: 2016 - 2017
DATE : 19.12.0216
PAGE : OF 10
YEAR/SEM/SEC: III / VI / -
QUESTION BANK
UNIT - V (TWO MARKS)
S.NO QUESTIONS
REMARKS
1. Define Control module of DSP processor.
2. Classify the implementation approaches for digital integrated circuits.
3. List Advantages and disadvantages of cell based design methodology.
4. Demonstrate Programmable logic array.
5. Classify the types of Macro cells.
6. Give a note on Tape out of chip.
7. Define Gate array Logic.
8. Compare semi-custom and full custom design.
9. What are the advantages of FPGA?
10. Define Fuse based FPGA.
11. Distinguish between PAL and PLA.
12. Develop an array based architecture used in Altera MAX series.
13. Design a primitive gate array cell.
14. Explain configurable logic block.
15. Summarize the functions of Programmable Interconnect Points in FPGA.
16. Identify the issues in implementing Boolean functions on array of cells.
17. Summarize the design steps of Semicustom design flow.
18. Illustrate Composition of generic digital processor.
19. Outline the steps for ASIC design flow.
20. Sketch the Overview implementation of digital ICs.

11. The Kavery Engineering College,
Mecheri, Salem District.
DEPARTMENT RECORDS
DOC.NO. :
TKEC/ECE/ACADEMIC/9
DEPARTMENT OF ELECTRONICS AND
COMMUNICATION ENGINEERING
ACADEMIC YEAR: 2016 - 2017
DATE : 19.12.0216
PAGE : OF 10
YEAR/SEM/SEC: III / VI / -
QUESTION BANK
UNIT - V (SIXTEEN MARKS)
S.NO QUESTIONS
REMARKS
1.
List and explain the components that makeup the cell based design
methodology. [10 Marks]
Give a short note on programming of PAL. [6 Marks]
2.
(i) Describe the Steps involved in semicustom design flow. [8 Marks]
(ii) Explain the concepts of programmable interconnect. [8 Marks]
3.
(i) Describe the Blocks involved in digital processor. [8 Marks]
(ii) Define and explain the approaches of programmable wiring. [8 Marks]
4.
(i) Illustrate the concepts of Mask programmable arrays. [12 Marks]
(ii) Identify the components involved in constructing a voltage output
macrocell. [4 Marks]
5. Classify the types of FPGA routing techniques and explain. [16 Marks]
6.
Explain the interconnect architectures of
i) Altera Max series [8 Marks]
ii) Xilinx XC40XX series [8 Marks]
7.
(i)Describe the FPGA block structure and its components. [8 Marks]
(ii)Describe the techniques involved in Switch box programmable wiring.
[8 Marks]
8.
(i)Discuss the types of FPGA routing techniques. [8 Marks]
(i)Demonstrate the types of ASICS. [8 Marks]
9.
(i)Design an LUT-Based Logic Cell. [8 Marks]
(ii)Discuss the Classification of prewired arrays. [8 Marks]
10.
(i) Compare two types of macrocells. [8 Marks]
(ii) Illustrate the datapaths in digital processor architectures. [8 Marks]
PREPARED BY
Staff in charge
APPROVED BY
Teaching Coordinator HOD Principal
Revision No: 00 Revision History:
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