This is an extended version of the paper published on IEEE Transactions on EMC, October 2016. PEEC modeling is a well established technique for obtaining a circuit equivalent for an electromagnetic problem. The time domain solution of such models is usually performed using nodal voltages and branch currents, or sometimes charge and currents. The present paper describes a possible alternative approach which can be obtained expressing and solving the problem in the waves domain. The digital wave theory is used to find an equivalent representation of the PEEC circuit in the wave domain. Through a pertinent continuous to discrete time transformation, the constitutive relations for partial inductances, capacitances and resistances are translated in an explicit form. The combination of such equations with Kirchhoff laws allows to achieve a semi-explicit resolution scheme. Three different physical configurations are analyzed and their extracted Digital Wave PEEC models are simulated at growing sizes using the general-purpose Digital Wave Simulator (DWS). The results are compared to those obtained by using standard SPICE simulators in both linear and nonlinear cases. When the size of the model is manageable by SPICE, an excellent accuracy and a speed-up factor of up to three orders of magnitude are observed with much lower memory requirements. PEEC model sizes manageable by DWS are also an order of magnitude larger than SPICE. A comparative analysis of results including the effect of parameters like the simulation time step choice is also presented.

1. 1
Digital Wave Simulation of Quasi-Static Partial
Element Equivalent Circuit Method
Luigi Lombardi, Piero Belforte, Member, IEEE , Giulio Antonini, Senior Member, IEEE
Abstract—PEEC modeling is a well established technique for
obtaining a circuit equivalent for an electromagnetic problem.
The time domain solution of such models is usually performed
using nodal voltages and branch currents, or sometimes charge
and currents. The present paper describes a possible alternative
approach which can be obtained expressing and solving the
problem in the waves domain. The digital wave theory is used
to find an equivalent representation of the PEEC circuit in the
wave domain. Through a pertinent continuous to discrete time
transformation, the constitutive relations for partial inductances,
capacitances and resistances are translated in an explicit form.
The combination of such equations with Kirchhoff laws allows
to achieve a semi-explicit resolution scheme. Three different
physical configurations are analyzed and their extracted Digital
Wave PEEC models are simulated at growing sizes using the
general-purpose Digital Wave Simulator (DWS). The results are
compared to those obtained by using standard SPICE simulators
in both linear and nonlinear cases. When the size of the model
is manageable by SPICE, an excellent accuracy and a speed-up
factor of up to three orders of magnitude are observed with much
lower memory requirements. PEEC model size manageable by
DWS are also an order of magnitude larger than SPICE.
A comparative analysis of results including the effect of
parameters like the simulation time step choice is also presented.
Index Terms—Delay free loop (DFL), digital wave approach,
digital wave simulator (DWS), free oscillations (FO), wave digital
network (WDN), partial element equivalent circuit (PEEC),
transient analysis.
I. INTRODUCTION
Virtual prototyping at the industrial level has become a very
effective approach which prevents the realization of physical
prototypes, saving money and time-to-market. Engineers can
quickly explore the performance of thousands of design al-
ternatives without investing the time and money required to
build physical prototypes. In the design of electronic/electrical
systems and devices, circuit simulation is nowadays considered
as a powerful environment to perform virtual prototyping,
provided equivalent circuits for the systems of interest. With
the increase of frequency, the modeling cannot neglect the
role of interconnections and parasitics anymore. Physical in-
terconnects therefore constitute a dominant factor affecting the
overall system performance. Hence, in order to compensate
their effects in earlier stages of design, it is important to
Manuscript received July 23, 2016.
Luigi Lombardi and Giulio Antonini are with the UAq EMC Laboratory,
Dipartimento di Ingegneria Industriale e dell’Informazione e di Economia,
Universit`a degli Studi dell’Aquila, Via G. Gronchi 18, 67100, L’Aquila, Italy,
e-mail: giulio.antonini@univaq.it.
Piero Belforte is an independent researcher at Via G. C. Cavalli 28 bis,
10138 Turin, Italy, e-mail: piero.belforte@gmail.com, Research Gate account:
https://www.researchgate.net/profile/Piero Belforte.
correctly characterize the interconnects and incorporate their
models in the same circuit environment where the design is
performed. A very popular environment for circuit simulation
is represented by SPICE [1] and all the SPICE-like transient
simulators which have been developed over the years.
Interconnect modeling and parasitic extraction has been
often performed using 3-D electromagnetic solvers which then
pose the problem of being integrated in a circuit environment.
Among them, a well-known approach which naturally gener-
ates accurate circuit models for 3-D electromagnetic structures
is the partial element equivalent circuit (PEEC) approach [2].
The PEEC method is based on the mixed potential integral
equation (MPIE) and the continuity equation. It provides a
circuit interpretation of the electric field integral equation
(EFIE) and continuity equation [3] in terms of partial ele-
ments, namely resistances, partial inductances and coefficients
of potential. Hence, the resulting equivalent circuit can be
directly embedded in a circuit environment allowing an easy
integration with other circuit models and the entire problem
be described by means of the circuit theory and solved in
both the time and frequency domain. Time domain solutions
are especially advantageous and the unique possibility, if
there are nonlinearities in the circuit environment. Over the
years, several improvements of the PEEC method have been
performed allowing to handle complex problems involving
both circuits and electromagnetic fields [2], [4]–[14]. The
drawback of this approach is related to the extremely large
size of the PEEC circuits which results in slow time-domain
simulations.
When the propagation delay is neglected and, thus, magnetic
and electric field interactions are assumed to be instantaneous,
the application of the PEEC method returns an equivalent
RLC circuit. Enforcing Kirchoff’s laws in the time domain
leads to a set of differential algebraic equations (DAEs) which
can be solved by resorting to standard solution schemes [15]
involving, e.g., backward (BD1) and forward Euler schemes,
the Gear (BD2) integration method, the trapezoidal scheme
[16]. Implicit methods have much better stability over their
explicit counterparts.
In the early 1970s, Alfred Fettweis formulated the wave
digital filter (WDF) framework as a technique for designing
digital filter structures that mimic the properties of analog
reference circuits, which had well-studied behavior and well-
established design principles [17], [18]. The WDF concept
provides an elegant framework for creating digital models of
analog reference circuits (or any lumped reference system).
Wave digital structures (WDS) establish models in the discrete
time domain; they can be used to describe both linear and

2. nonlinear systems. Due to their numerical properties, WDS
are well suited for hardware implementation.
Also in the early ’70s, at the CSELT Labs of Turin, the digi-
tal wave approach was conveniently applied for the first time to
model and simulate the interconnects among high-speed digital
devices of advanced Telecom systems [19]. Fettweis concepts
were extended to distributed ideal transmission line (TL)
elements while z-transform principles were utilized to develop
digital wave models of active components (drivers, receivers)
extracted from TDR measurements. To clearly differentiate
Fettweis WDF from these TL computer simulation-oriented
developments, the term Digital Wave (DW) was always used
instead of Wave Digital (WD). Up to mid ’80s several
specialized programs were developed to model and simulate
lossy interconnects, crosstalks and nonlinear drivers [20], [21].
Based on this experience, a general topology program, with
emphasis to wideband signal integrity (SI), power integrity
(PI) and electromagnetic compatibility (EMC) applications,
was developed by the company HDT founded by the inventors.
This simulator, called SPRINT, solved the well known DFL
(Delay Free Loop) issue affecting digital wave structures,
included time-variant, nonlinear elements and S-parameters
behavioral blocks described in time domain [22]. An early DW
application to PEEC is described in [23]. The input network
description was a SPICE-like netlist. The latest version of this
tool is DWS 8.5 [24]. A complete overview of the applications
fields of the digital wave simulator DWS is reported in [25]
along with a specific application to lossy transmission lines in
the multi-gigabit speed range.
Recently, the digital wave approach has been also applied
to the microwave filter field to model microstrip structures
with discontinuities, short-circuited and open stubs [26], [27]
assuming the model of uniform transmission lines.
The aim of this paper is to present in a systematic way
a digital wave formulation of quasi-static PEEC models. A
preliminary work describing the digital wave formulation of
the PEEC method has been presented in [28] where the
formulation has been shortened for lack of space. All the
details are provided in this work along with extensive extensive
tests and related numerical results. Since magnetic and electric
field couplings are described by full matrices, a critical point
is to translate them in the wave domain in an efficient way.
The paper is organized as follows. Section II briefly summa-
rizes the PEEC method. The WDF framework is introduced in
Section III while Section IV presents the concept of adaptors.
A possible representation in the wave domain of the couplings
is presented in Section V. The solution algorithm used within
DWS is outlined in Section VI. The numerical results along
with the comparisons between DWS and SPICE are presented
in Section VII. The conclusions are drawn in Section IX.
II. BASIC PEEC FORMULATION FOR CONDUCTIVE
MATERIALS
The PEEC method is based on an integral equation for-
mulation of the geometry that is interpreted in terms of
circuit elements [2]. The main difference between PEEC and
other integral equation based methods is that it provides a
circuit interpretation of the electric field integral equation in
terms of partial elements (e.g., partial inductances and partial
capacitances) [29]. The resulting circuit can be analyzed using
SPICE-like circuit solvers in both time and frequency domain.
In the following, a short summary is presented for conductors
only for the sake of simplicity.
The PEEC model is developed starting from the electric
field integral equations and the continuity equation. The vol-
umes of the geometry under analysis is discretized using
parallelepipeds or, more in general, hexahedra, while the
surfaces are tesselated using rectangles or quadrilaterals. The
electrical unknowns, typically current densities and charge
density are expanded using pulse basis functions, meaning
they are assumed uniform within each elementary volume
the former, elementary surface the latter. Then, the standard
Galerkin’s testing approach is used to discretize the equations
leading to topological entities like nodes and branches which
are the typical of lumped circuits and are related by a con-
nectivity matrix A. Magnetic field coupling is modeled by
partial inductances Lp and electric field coupling is modeled
by coefficients of potentials P. Partial resistances are also
introduced to represent power dissipation. The definition for
coefficient of potential implies that the charges reside only on
the surface of the conductors. Short-circuit capacitances Cs
are obtained directly from the coefficients of potential P [29].
The enforcement of Kirchoff Voltage and Current Laws (KVL
and KCL, respectively) to the equivalent circuit leads to the
following sets of equations
AT
φ (t) + Ri (t) + Lp
d
dt
i(t) = −vs (t) (1a)
P−1 d
dt
φ (t) + Gleφ(t) − Ai (t) = is (t) (1b)
where the relation φ (t) = Pq (t) between charge and poten-
tials has been used and where Gle denotes the memory-less
lumped elements matrix. Vector vs (t) denotes the voltage
sources due to incident fields [30], vector is (t) represents
lumped current sources.
Equations (1) represent a set of Nn + N equations in
Nn + N unknowns (Nn and N being the number of nodes
and edges, respectively, of the equivalent circuit), that can be
written in a matrix form as follows
R + Lp
d
dt AT
−A Cs
d
dt + Gle
·
i
φ
=
−vs
is
(2)
By assuming matrices P and Lp frequency independent, the
system (2) can be re-written in time-domain as follows
C
dx(t)
dt
= −Gx(t) + Bu(t) (3)

3. Re(s)
Im(s)
|z| = 1
Re(z)
Im(z)
Fig. 1. Spectral mapping resulting from trapezoidal rule or, equivalently, from
bilinear trasform.
where
C =
Lp 0
0 Cs
(4a)
G =
R AT
−A Gle
(4b)
B =
I 0
0 I
(4c)
x(t) = [i(t) φ(t)]
T
(4d)
u(t) =
−vs(t)
is(t)
. (4e)
The previous equations are only slightly modified if dielectrics
are included. The interested reader can refer to [12], [29], [31].
III. DIGITAL WAVE ELEMENTS AND CONNECTIONS
Digital wave circuits are the result of a conversion per-
formed on an analog circuit using a particular discretization
scheme.
A. The bilinear transform
The discretization is carried out using the trapezoidal rule in
the time domain or, equivalently, the bilinear transform in the
frequency domain. Such discretization can be regarded as the
mapping between the continuous frequency s and the discrete
frequency ψ [32]. The new discrete frequency and the analog
frequency are related by
ψ
2
T
1 − e−sT
1 + e−sT
. (5)
From standard digital filtering theory e−sT
= z−1
can be
interpreted as the unit delay of duration T, hence
ψ
2
T
1 − z−1
1 + z−1
. (6)
If we look at the real part of ψ, we have
Re(ψ) =
2
T
1 − e−2Re(s)T
|1 + e−sT |2
=
2
T
1 − |z|2
|1 + z−1|2
. (7)
Equation (7) shows that, when the real part of the analog
frequency s is positive (negative), the real part of the discrete
frequency ψ is positive (negative) as well and |z| > 1
(|z| < 1). Hence, as it can be seen from Fig. 1, a stable and
causal transfer function in the continuous domain will stay
such also in the discrete domain.
B. Wave variables
For a port with voltage v and a current i, incident and
reflected voltage waves are defined by
a = v + iR0 (8a)
b = v − iR0 (8b)
It is straightforward to extend wave digital filtering principles
to the vector case (this has been outlined by Nitsche [33] and
appeared in the context of DWNs [34]). For a q-component
vector one port element voltage v = [v1, v2, · · · , vq]T
, and
current i = [i1, i2, · · · , iq]T
, it is possible to define wave
variables a and b by
a = v + iR0 (9a)
b = v − iR0 (9b)
C. Digital wave elements
We will now present the digital wave equivalents of the
circuit elements mentioned in the previous Section II, namely
inductances, capacitance, resistances, current sources and volt-
age sources.
Under the bilinear transform (5), or (6), the steady state
equation for an inductor becomes
ˆv =
2L
T
1 − z−1
1 + z−1
ˆi (10)
or, in the discrete-time domain
v (n) + v (n − 1) =
2L
T
(i (n) − i (n − 1)) (11)
If we apply the definition of wave variables (8), we get, in the
discrete time domain
a(n) + b(n) + a(n − 1) + b(n − 1) =
=
2L
RLT
(a(n) − b(n) − a(n − 1) + b(n − 1) (12)
where RL is the reference resistance for the inductance L.
If we set
R0 = RL =
2L
T
(13)
then (12) simplifies to
b (n) = −a(n − 1) (14)
Hence, the input wave a undergo a time-step delay T and sign
inversion before it is output as b.
The construction of the digital wave one-ports correspond-
ing to the resistor and capacitor is similar. For the capacitance,
assuming
R0 = RC =
T
2C
(15)
It leads to
b (n) = a(n − 1) (16)
assuming a reference resistance RC = T/2C and
b (n) = 0 (17)
for the resistance, assuming a reference resistance RR = R.

4. TABLE I
DIGITAL WAVE CONSTITUTIVE RELATIONS FOR R, L, C UNDER THE
BILINEAR TRANSFORM.
Lumped element Value Port impedance Wave relation
Resistor R R b(n) = 0
Capacitor C
T
2C
b(n) = a(n − 1)
Inductor L
2L
T
b(n) = −a(n − 1)
The digital wave constitutive relations for R, L, C under the
bilinear transform are summarized in Table I.
It is worth noting that the use of an implicit integration
method, like the trapezoid rule, to discretize the time derivative
of the inductance and capacitance constitutive laws usually
entails decisive numerical advantages but at the cost of the
lost of the local computability, meaning that it leads to the
solution of a linear system. When the electrical quantities are
expressed by wave quantities, it leads to an explicit scheme,
provided a proper choice of the reference resistance is done.
It is to be remarked that the DWF is applicable also to
circuits which do not admit an impedance or admittance
representation, like ideal transformers which are often used
in the design.
IV. ADAPTORS
In a circuit environment, we can connect the basic lumped
elements by means of series and parallel connections. When
we move to digital wave domain, the same function is per-
formed by adaptors. While the mathematical description of
a connection is given by a set of equation (usually voltage-
current relation for the considered elements), for the adaptors
the description is represented by scattering parameters, which
are completely defined by the port impedances of the adaptor.
A. Series Adaptors
A
B
B
A
Fig. 2. Series connection in a circuit environment and the equivalent series
adaptor.
It follows that a series connection will be represented in the
wave domain by means of a series adaptor. Figure 2 shows
the representations of a two element series. The 3-port series
adaptor obtained will be described by the scattering matrix
SSA =


1 − γ1 −γ1 −γ1
−γ2 1 − γ2 −γ2
−γ3 −γ3 1 − γ3

 (18)
where
γ1 =
2 · Rport1
Rport1 + Rport2 + Rport3
, (19a)
γ2 =
2 · Rport2
Rport1
+ Rport2
+ Rport3
, (19b)
γ3 =
2 · Rport3
Rport1
+ Rport2
+ Rport3
. (19c)
Rporti , i = 1, 2, 3 is the impedance port for the i-th port.
B. Parallel Adaptors
A
B
B
A
Fig. 3. Parallel connection in a circuit environment and the equivalent parallel
adaptor.
The same applies to the parallel connection. Figure 3 shows
the case of a two elements parallel connection. The 3-port
parallel adaptor obtained is described by the scattering matrix
SP A =


δ1 − 1 δ2 δ3
δ1 δ2 − 1 δ3
δ1 δ2 δ3 − 1

 (20)
where
δ1 =
2 · Gport1
Gport1 + Gport2 + Gport3
, (21a)
δ2 =
2 · Gport2
Gport1
+ Gport2
+ Gport3
, (21b)
δ3 =
2 · Gport3
Gport1
+ Gport2
+ Gport3
. (21c)
Gporti , i = 1, 2, 3 is the admittance port for the i-th port.
C. Reflection-Free Port
If we better analyze the scattering matrix for both series and
parallel adaptors, we easily realize that, with a proper choice
of the n-th impedance, we can stamp out the reflection on the
same port. As a consequence, we can obtain that the reflected
wave at the n-th port does not depend instantaneously on the
incident wave at that port (snn = 0) . For example if we
consider the case of a 3-port series adaptor we will have:
SSA =


1 − γ1 −γ1 −γ1
γ1 − 1 γ1 γ1 − 1
−1 −1 0

 (22)
if we choose the reference port 3 impedance such that
Rport3 = Rport1 + Rport2 . (23)
Similarly for a 3-port parallel adaptor,
SP A =


δ1 − 1 1 − δ1 1
δ1 −δ1 1
δ1 1 − δ1 0

 (24)

5. if we choose the reference port 3 admittance such that
Gport3 = Gport1 + Gport2 . (25)
It can be noticed that the impedances of the Reflection Free
Port (RFP) is exactly the equivalent impedances seen from the
A and B terminals if we consider the hybrid representation
in Fig. 4, or the circuit representation in Figs. 2 and 3.
The enforcement of the RFP criterion allows to decouple the
computation between the waves propagating from the leaves
to the root and the ones propagating in the inverse direction in
the chain of adaptors. This could lead to an explicit scheme,
as we will see in the first example of the section VI, or to a
semi-explicit scheme as we will see in the second example of
the section VI. It must be noticed that the effectiveness of this
approach depends on the way the elements are connected to
each other, more the network graph has triconnected elements
more the solution becomes implicit because of the presence
of Delay Free Loop (DFL) needed to represent complex
instantaneous connections.
B
A
B
A
Fig. 4. Hybrid representation for series and parallel adaptors.
V. COUPLING REPRESENTATION
In this section we will see some possible way for managing
the coupling as DWS does in order to obtain a performance
improvement.
A. The ”Marx” Π Model
k
L1 L2
D
C
A
B
L11
L12
L22
D
C
A
B
Fig. 5. Coupled inductors and their ”Marx” Π representation.
As seen in the previous section, in the conversion process
from analog to digital network, a one-by-one replacement
can be performed for resistors, capacitors and inductors.
Unfortunately, we can not do the same for inductive coupling
coefficients, hence we need to find some kind of equivalent
representation admitting a simple substitution in the digital
network. We can represent the inductive behavior using the
Marx, or Π, equivalent for the inductive couplings as shown in
Fig. 5 [24], in this way we replace the coupling coefficients in
the models with inductors. Hence, starting from inductors and
coupling factors we can compute a pure inductive equivalent
representation which admits an immediate representation in
the digital wave domain. For the case shown in Fig. 5, if we
name the two inductors L1 and L2 and M = k
√
L1L2, we
can compute the value of the Π equivalent by
L11 =
L1L2 − M2
L2 − M
(26)
L22 =
L1L2 − M2
L1 − M
(27)
L12 =
L1L2 − M2
M
(28)
In case of three or more coupled inductors, this represen-
tation requires the inversion of the partial inductance matrix.
The partial inductance matrix Lp may easily become quite
large for PEEC models with a number of branches exceeding
hundred thousands. Anyway, several techniques are available
to accelerate the inversion (e.g., see [35]).
N1
T
-1
AS12
T
-1
N2
T
-1
A B C D
Fig. 6. Stub model for circuit in Fig. 5.
B. Link Model for Inductors
N1
T
-1
A B C D
N2
T
-1
T
T
Fig. 7. Link model for circuit in Fig. 5.
Once the Π model for coupled inductors is computed,
we can quite easily obtain two possible equivalent networks
based on the ”stub” and ”link” models of inductors, shown
in Fig. 6 and Fig. 7, respectively. The most accurate one
is the ”stub” representation [36], in which (see Fig. 6) we
replace the inductance by means of a stub having characteristic
impedance:
ZC =
2 · L
TSTEP
. (29)
Unfortunately, the resulting equivalent digital network leads
to a more implicit scheme, because we need to preserve the
series adaptors between the two parallel adaptors. In order to
improve the computation performances we can use the ”link”

6. model (see Fig. 7) for the mutual inductances that makes
the computation explicit within each inductive branch of the
PEEC model and, at the same time, retains the stub model
for the self-inductances. The link model of inductor is the
representation of an inductor by means of a transmission line
[24], [36], [37] having characteristic impedance:
ZC =
L
TSTEP
. (30)
It can be proved that the error, assuming the same time step, is
four times larger than the one obtained from the stub model.
Due to the relation between errors [36] and time step, both link
and stub models are characterized by the same error simply
using a time step for the link model equal to half the time
step for the stub model. Moreover, since the error can be
regarded as a shunted capacitor, for both representation, the
global model is still passive.
C. Electric Coupling
In the PEEC context, the electric field coupling can be
represented by either coefficients of potential or capacitors.
Thus it is possible to represent the electric coupling in the
digital wave domain exploiting the capacitors representation.
VI. SIMPLE EXAMPLES AND DISCUSSION
In this section two simple examples are presented in order
to give more insight on DWS operation and some observations
are given to better explain the features of the proposed
approach.
A. RLC Series Circuit
e
R1 L3
R5C2 C4
Fig. 8. Simple RLC circuit.
The first example is the RLC circuit shown in Fig. 8. Using
the transformations described in the previous sections and the
equivalent wave representation for the real voltage source, it
is easy to obtain the equivalent DWN, Fig. 9,including the
scattering parameters for each adaptor. At this stage we can
start the computation going back and forth from the borders to
the middle of the circuit and viceversa. In this way we define
N1 SA1 N2
e
Ts Ts
−1
Ts
0
Fig. 9. Equivalent wave digital network for the circuit in Fig. 8.
a)
SA1
N1 N2
b)
ROOT
SARLi
SANLi
SACi
Fig. 10. Solution tree for the wave digital network in Fig.9 (a) and Fig. 12
(b) .
R1 L1
R2 L2
RloadRS
C1
C4
αj4v(Cj ) αj3v(Cj )
C3
C2
αj2v(Cj )αj1v(Cj )
IS
1 2
34
Fig. 11. Analog two cell PEEC.
the solution tree in Fig. 10. For this circuit the solution scheme
is fully explicit and thanks to the computational scheduling
adopted within DWS we have a very fast solving algorithm.
If the circuit becomes larger the solution tree becomes deeper
and/or wider and the scheme stays explicit, as long as we do
not have free delay loop in the wave digital network [38].
B. PEEC 2 cell
The second example consists of a simple PEEC model that
allows us to take all the significant elements into account
that are also found in larger problems. For the sake of
explanation, we will use the representation in Fig. 11 and we
will use delayed controlled sources for the VCVS. Every other
representation is fine as well although the WDN may result
to be different and even more complex. For the considered
representation, the equivalent digital network is described in
Fig. 12. As in the previous example we can solve the network
from the border to the middle but at a certain stage we
encounter the delay free loop in Fig. 13, hence we need to
solve it implicitly. The exposed procedure define the solution
tree in Fig. 10 (b) where ROOT is the DFL that is to be
solved in some way. A possible approach for the solution of the
solution of the ”root” is given by the definition of an equivalent
circuit composed by resistors and controlled sources. The
definition of such network is completely specular respect to the
computation of the equivalent digital network determination.

7. SAS
iS · RS
SAL
0
N4
SAc4
T
αj4v(Cj )
SA2
0
SARL2
N3
SAc3
T
αj3v(Cj )
NL2
-1
T
-1
T
NL1
SARL1
T T
N2
SAc2
T
αj2v(Cj )
SA1
0
N1
SAc1
T
αj1v(Cj )
Fig. 12. Equivalent digital network for the 2 cell PEEC.
SAS
iS · RS
SAL
0
N4 SA2 N3
N2SA1N1
Fig. 13. ”Root” of the equivalent digital network for the 2 cell PEEC.
+
−iS RS
RS
R2
1
GL2
+
−
aL2
RL
R1
1
GL1
+
−
aL1
+
−aN1
RN1
+
−aN4
RN4
+
−aN3
RN3
+
−aN2
RN2
Fig. 14. Circuital representation for the root problem.
In the case of this example the circuit representation of the
”root” is shown in Fig. 14 and can be solved by nodal analysis.
VII. NUMERICAL RESULTS
The proposed digital wave formulation has been experi-
mented using the tool DWS [24] while the traditional Nodal
Analysis has been performed using both Ngspice [39] and
Pspice [40]. Ngspice has been used to compare the simulation
times and RAM size requirements in a free oscillations config-
uration. Pspice has been used to compare the numerical results
in specific termination conditions specified in the examples.
The digital wave simulator DWS is completely circuit-
oriented and, thus, can be considered as an alternative to
standard SPICE-like solvers. All the simulations have been
performed on an Intel Quad-Core i7-2630QM 2.00 GHz CPU
machine.
Three different physical structures have been chosen to
compare DWS to SPICE results. The effect of growing size
of the PEEC model is evaluated using different pitches of
spatial discretization. The PEEC model has been generated
by using an in-house tool, then a SPICE-like netlist has been
synthesized and analyzed using both Ngspice [39] and Pspice
[40]. The same RLC and coupled inductor PEEC netlist can be
simulated by all the tools simply modifying the .TRAN control
statement according to DWS and SPICE syntax respectively.
The tests have been carried out using a stimulus and termina-
tion configuration suitable to pinpoint results differences with
a bandwidth resolution much higher than the bandwidth of the
PEEC model itself. An ideal fast ramp voltage (10 ps total rise
time) source is connected to the input port while the output
port(s) are left open. This configuration is able to generate
free oscillations of the circuit under test. Observing the output
waveforms for a suitable number of free oscillations it is easy
to point out issues like late-time numerical instabilities, delay
differences and spurious losses due to the simulation method
used.
Using DWS, the most important control parameter is the
simulation time step (TSTEP). This choice directly conditions

8. the parameters of the generated DWN, the integration error and
the equivalent bandwidth of the simulation. Using the default
semi-explicit method for PEEC couplings, the TSTEP value
is also directly related to the stability of the simulated model.
Typically picosecond or sub-picosecond TSTEP values are
required with a 10 ps input stimulus to get good stability for
the chosen test circuits. SPICE typically works at variable time
step and in order to get results with an accuracy/ bandwidth
comparable to DWS the maximum allowed value of time step
(TMAX) was chosen as main control parameter, leaving the
other options to their default value.
A. Interconnect
In the first example, a five conductor interconnect is con-
sidered. The length, width and thickness of the conductors
are 5 cm, l50 µm and 100 µm, respectively. The edge-to-
edge spacing is l50 µm. The geometry of the interconnect is
shown in Fig. 15. In the first test, the first two conductors are
terminated on 1 pΩ resistance and driven by a voltage step
with 10 ps rise-time. All the other ports are left open. Figure
16 shows the output port voltage on the two driven conductors.
Figures 17-18 shows the input and output port voltages on the
last two open-ended conductors.
0
0.02
x [m]
0.04
0
0
×10-3
y [m]
1
0.5
×10-4
z[m]
0.061
1.5
2
Fig. 15. Five conductor interconnect.
In the second test, the first port is driven by a fast voltage
ramp (10 ps rise time and 1 V of amplitude) while all the other
ports are left open. The comparative performances of Ngspice
and DWS solvers are reported in Table II.
B. Power divider
In the second example, a three-port microstrip power-divider
circuit has been modeled. The structure is shown in Fig. 19
(P1, P2 and P3 denote the ports). The dimensions of the circuit
are [20, 20, 0.5] mm in the [x, y, z] directions and the width of
the microstrips is set as 0.8 mm. Furthermore the dimensions
lX1, lY 1, and lY 3 are 9, 7.2 and 7.2 mm, respectively. The
relative dielectric constant is εr = 2.2. In the first test, port 1
is excited by a 2 V finite ramp with a rise-time 10 ps. All the
0 0.2 0.4 0.6 0.8 1
Time [s] 10
-8
-0.5
0
0.5
1
1.5
2
2.5
V2
[V]
Pspice
DWS
Fig. 16. Interconnect port 2 voltage.
0 0.2 0.4 0.6 0.8 1
Time [s] 10
-8
-0.14
-0.12
-0.1
-0.08
-0.06
-0.04
-0.02
0
V5
[V]
Pspice
DWS
Fig. 17. Interconnect port 5 voltage.
0 0.2 0.4 0.6 0.8 1
Time [s] 10
-8
-0.2
-0.15
-0.1
-0.05
0
0.05
V6
[V]
Pspice
DWS
Fig. 18. Interconnect port 6 voltage.
ports are terminated on 50 Ω resistances. In the second test,
the first port is driven by a fast voltage ramp (10 ps rise time
and 1 V of amplitude) while all the other ports are left open.

9. TABLE II
PERFORMANCE COMPARISON OF PEEC-SPICE AND PEEC-DWS FOR THE 5 CONDUCTOR MTL CASE.
Netlist lines Edges Nodes DWS MAX TSTEP [ps] DWS TSTEP [ps] Ngspice [s] DWS [s] Speed-up
11k 180 100 10 10 1096 1.6 685
11k 180 100 10 0.1 4200 65 64.6
30k 300 160 10 10 5400 6.8 794.1
30k 300 160 10 0.1 11700 468 25
114k 620 300 0.5 0.5 NA 708 NA
114k 620 300 0.5 0.1 NA 3111 NA
wP1
P3P2
lX,1
lY,1 lY,3
lY
lX
Fig. 19. The three-port microstrip power-divider circuit.
0 1 2 3 4 5
Time [s] 10
-9
0
0.2
0.4
0.6
0.8
1
1.2
V1
[V]
Pspice
DWS
Fig. 20. Power divider port 1 voltage.
0 1 2 3 4 5
Time [s] 10
-9
-0.2
0
0.2
0.4
0.6
0.8
V2
[V]
Pspice
DWS
Fig. 21. Power divider port 2 voltage.
0 1 2 3 4 5
Time [s] 10
-9
-0.2
0
0.2
0.4
0.6
0.8
1
V3
[V]
Pspice
DWS
Fig. 22. Power divider port 3 voltage.
The comparative performances of Ngspice and DWS solvers
are reported in Table III.
C. Coplanar striplines
In the third example, two coplanar striplines are embedded
in a dielectric, as shown in Fig. 23 and backed by two metallic
planes. The conductivity of striplines and planes is σ = 5.7 ·
107
S/m. The relative permittivity of the dielectric is εr = 4.
The blue lines represent the ports. Following are the geometric
parameters shown in Fig. 23 : 1 = 40 mm, 2 = 14 mm, s1 =
5 mm, s2 = 2 mm, wc = 1 mm, vs = 10 mm, hd = 20.95
mm and tc = 50 µm. A voltage ramp of amplitude 2 V is
applied to port 1. Port 1 has a 50 Ω resistance while port 2 is
left open. The transient voltages are observed at ports 1 and
2. In the second test, the first port is driven by a fast voltage
ramp (10 ps rise time and 1 V of amplitude) while all the other
ports are left open. The comparative performances of Ngspice
and DWS solvers are reported in Table IV. Then, in a third
test, the coplanar striplines have been terminated on a diode
(CJO=1 pF, Tt=100 ps) with in parallel a 100 fF capacitor.
The input port of the striplines is driven by a voltage ramp
with 10 ps rise time and 0.5 V amplitude. Figure 26 presents
the voltage across the diode as evaluated by the digital wave
simulator (DWS) and Ngpice. The performances are reported
in Table V.

10. TABLE III
PERFORMANCE COMPARISON OF PEEC-SPICE AND PEEC-DWS FOR THE POWER DIVIDER CASE.
Netlist lines Edges Nodes DWS MAX TSTEP [ps] DWS TSTEP [ps] Ngspice DWS [s] Speed-up
35k 436 86 0.5 0.5 480 min 55 523
100k 720 149 0.5 0.5 67 h 360 670
100k 720 149 0.5 0.2 NA 660 NA
200k 1008 212 0.2 0.2 NA 1260 NA
TABLE IV
PERFORMANCE COMPARISON OF PEEC-SPICE AND PEEC-DWS FOR THE COPLANAR STRIPLINE CASE
(*ESTIMATED SIMULATION TIME WITH TMAX = 1 ps).
Netlist Lines Edges Nodes DWS MAX TSTEP [ps] DWS TSTEP [ps] Ngspice DWS [s] Speed-up
18k 300 72 0.2 0.2 5760 50 115
18k 300 72 0.2 0.1 NA 88 NA
18k 700 144 0.2 0.2 34h * 574 213
96k 700 144 0.2 0.1 34h * 1050 116
255k 1150 264 0.05 0.05 NA 5800 NA
TABLE V
PERFORMANCE COMPARISON OF PEEC-SPICE AND PEEC-DWS FOR THE COPLANAR STRIPLINE CASE TERMINATED ON A DIODE
(*ESTIMATED SIMULATION TIME WITH TMAX = 0.2 ps).
Netlist Lines Edges Nodes DWS MAX TSTEP [ps] DWS TSTEP [ps] Ngspice DWS [s] Speed-up
18k 300 72 0.2 0.2 366 min 41 549
96k 700 144 0.2 0.2 253 h* 574 1500
225k 1150 264 0.05 0.05 NA 5800 NA
494k 1500 288 0.2 0.2 NA 6450 NA
2
1
hd
tc
tc
s1
vs
vs
tc
wc s2 wc
vs
vs
tc
s1
1
2
Fig. 23. Structure of the coplanar striplines circuit.
0 0.2 0.4 0.6 0.8 1
Time [s] ×10
-8
0
0.5
1
1.5
2
2.5
V1
[V]
Pspice
DWS
Fig. 24. Coplanar striplines port 1 voltage.
0 0.2 0.4 0.6 0.8 1
Time [s] ×10
-8
-0.5
0
0.5
1
1.5
2
2.5
3
V2
[V]
Pspice
DWS
Fig. 25. Coplanar striplines port 2 voltage.
VIII. ANALYSIS OF RESULTS
A. DWS simulations
It has been observed from the tests that the default DWS
model of magnetic couplings leads to a semi-explicit wave
model that imposes some constraints of the maximum allowed
simulation time step (MAX TSTEP). To insure late-time
stability of the simulation a sufficiently small TSTEP has
to be chosen. The value of the maximum allowed tstep has
been determined experimentally and depends on the specific
model and on the size of the circuit. Larger circuit size usually
requires smaller time steps. The multiconductor transmission
line of Fig. 15 allows a time step up to 10 ps for the
smaller model sizes (11K and 30K netlist lines), while 500

11. 0 0.2 0.4 0.6 0.8 1
Time [s] ×10
-8
-0.2
0
0.2
0.4
0.6
0.8
Voltage[V]
DWS
Ngpice
Fig. 26. Voltage across the diode (example of coplanar striplines).
fs is required for the 114K netlist lines model. The three-
port splitter of Fig. 19 and the coplanar stripline of Fig. 23
show MAX TSTEP values ranging from 500 fs down to 50 fs
depending of the netlist size. The calculation speed is linearly
dependent on time step while the bandwidth resolution is
inversely proportional. Using sub-picosecond time steps the
simulation bandwidth exceeds the requirement imposed by the
10 ps transition time of the stimulus and by the extracted
PEEC model itself. RAM size requirements are not dependent
on time step and depends only on circuit size. 22.5 MB are
required for a 18K lines coplanar stripline model, while 263
MB are required to run the largest models (400K lines). The
required RAM is constant during the simulation run. The
analysis of free oscillations has also pointed out that no energy
losses are due to the simulator even for relatively long times
(tens of nanoseconds). This lossless behavior is expected due
to the use of wave models equivalent to the trapezoidal rule
of integration for capacitors and inductors and for the link
transmission line model of the magnetic coupling.
B. SPICE simulations
Three SPICE versions has been used during the tests:
Ngspice, Pspice and Ltspice. While Ngspice and Pspice give
practically the same results, LTspice is affected by a strong
damping of high-frequency components if default settings
of inductor parameters are used. To avoid this effect, the
additional default resistances must be set to zero [41]. Ngspice
and Pspice simulation time is strongly affected by circuit size
and this dependence is not linear, so that PEEC models with
size in the order of tens of thousands netlist lines are very
difficult to be managed because of prohibitive run times (hours
to tens of hours). RAM requirement grows during run time and
is in the order of 462 MB for a 18K lines model (Coplanar
line with diode clamp).
C. DWS vs SPICE
The comparison of DWS and SPICE (Ngspice, Pspice,
LTspice) simulations shows a very good matching between
numerical results even in the wideband configuration used for
the tests. A slight phase shift of persistent free oscillations
can be observed especially after a consistent number of
oscillations. This phase shift grows linearly with time and
is due to the one-step delay of the link model of magnetic
coupling used in DWS. For this reason it is more significant
when using larger time steps. In practical configurations where
resistive sources and loads are used, this effect is negligible.
The most evident difference is on the speed-up achieved
by DWS with respect to SPICE. The observed speed-up is
ranging from 65X for the simplest MTL model to 1500X
(extrapolated) for the medium size Coplanar stripline with
a nonlinear termination. The speedup is 4 times larger for
a nonlinear situation with respect the linear one. DWS can
manage PEEC models up to a 500K lines netlist complexity
with a simulation time in the order of a couple of hours while
SPICE is practically limited to about 20K lines. With larger
size circuits DWS is affected by a significant amount of time
spent for building up the DWN from the netlist. In the case of
Coplanar line largest model, this setup time is about the 60%
of the total elapsed time.
Despite its speed, DWS also requires a smaller amount
of RAM with respect to SPICE. A typical 20X RAM size
reduction has been observed in the tests. A main reason of the
slow simulation speed of SPICE is the variable simulation
time step. This requires a matrix inversion at each step
in a situation where the matrix is dense. The situation is
exacerbated when the circuit is nonlinear, because at each step
a number of Newton-Raphson iterations is required. In DWS
these iterations are confined only to the nonlinear elements or
are not required in case of piecewise linear elements [24], so
that the time required for a non linear circuit can be about
the same of the linear situation. The same applies for time-
variant terminations [42]. Several additional technical reports
regarding DWS-PEEC trials are reported in [43].
IX. CONCLUSIONS
In this paper a Digital Wave formulation of quasi-static
PEEC method (PEEC-DWS) has been presented. This for-
mulation is used within the general purpose simulator DWS.
Despite DWS has been conceived mainly to deal with prop-
agation and delay effects typical of wideband SI, PI and
EMC problems, it has been demonstrated that it can be also
conveniently utilized for highly interconnected RLC lumped
electrical networks typical of PEEC models. Using a Marx
equivalent of coupled inductors, DWS builds up a semi-
explicit wave domain equivalent of the PEEC model starting
from its Spice-like netlist. Stable simulations of the PEEC
model connected to a linear, time-variant or even nonlinear
network, can be achieved if a sufficiently small simulation
time step is used. Comparative tests with Ngspice or Pspice
simulations, carried out using very fast ramp stimulus and
open terminations, have shown an excellent agreement with
a speed-up factor of up to 3 orders of magnitude and a much
lower requirement of memory. The larger the PEEC model,
the larger is the achievable speed-up and the speed gain is
higher in nonlinear situations. While SPICE is practically

12. limited to deal with PEEC models showing a netlist size
in the order of ten thousand lines, DWS can be used to
simulate models up to 50-100 times this size. Being the
DWN used by DWS essentially composed by unit-delay TL
and adaptors (series and parallel) no additional loss is added
within the wave model. This lossless behavior can be easily
verified by observing the free oscillations generated by the
test configurations: they are persistent if the no resistive part is
included within the PEEC model. Another major advantage of
using the PEEC-DWS modeling is the ability to mix traditional
PEEC models with lossless/lossy distributed-parameters TLM
or behavioral time models that are very fast and accurate.
A further step toward higher performance can be achieved
using alternative modeling techniques of basic elements like
capacitors and inductors in order to get stable responses even
using larger time-steps. Another interesting development is the
utilization of different alternatives by modeling the couplings
by means of delayed controlled sources well supported by
DWS and/or including behavioral frequency dependent losses
within the PEEC-DWS cells.
These alternative solutions will be the object of future
research work.
REFERENCES
[1] L. W. Nagel, “SPICE: A computer program to simulate semiconductor
circuits,” University of California, Berkeley, Electr. Res. Lab. Report
ERL M520, May 1975.
[2] A. E. Ruehli, “Equivalent circuit models for three dimensional mul-
ticonductor systems,” IEEE Transactions on Microwave Theory and
Techniques, vol. MTT-22, no. 3, pp. 216–221, Mar. 1974.
[3] C. A. Balanis, Advanced Engineering Electromagnetics. John Wiley
and Sons, New York, 1989.
[4] A. E. Ruehli, “Inductance calculations in a complex integrated circuit
environment,” IBM Journal of Research and Development, vol. 16, no. 5,
pp. 470–481, Sep. 1972.
[5] A. E. Ruehli, P. A. Brennan, “Efficient capacitance calculations for three-
dimensional multiconductor systems,” IEEE Transactions on Microwave
Theory and Techniques, vol. 21, no. 2, pp. 76–82, Feb. 1973.
[6] W. Pinello, A. C. Cangellaris and A. E. Ruehli, “Hybrid electromagnetic
modeling of noise interactions in packaged electronics based on the
partial-element equivalent circuit formulation,” IEEE Transactions on
Microwave Theory and Techniques, vol. MTT-45, no. 10, pp. 1889–
1896, Oct. 1997.
[7] G. Wollenberg, A. G¨orisch, “Analysis of 3-D interconnect structures
with PEEC using SPICE,” IEEE Transactions on Electromagnetic Com-
patibility, vol. 41, no. 2, pp. 412–417, Nov. 1999.
[8] G. Antonini, A. Orlandi, “A wavelet based time domain solution for
PEEC circuits,” IEEE Transactions on Circuits and Systems, vol. 47,
no. 11, pp. 1634–1639, Nov. 2000.
[9] A. E. Ruehli, A. C. Cangellaris, “Progress in the methodologies for the
electrical modeling of interconnect and electronic packages,” Proceed-
ings of the IEEE, vol. 89, no. 5, pp. 740–771, May 2001.
[10] A. E. Ruehli, G. Antonini, J. Esch, J. Ekman, A. Mayo and A. Orlandi,
“Non-orthogonal PEEC formulation for time and frequency domain
EM and circuit modeling,” IEEE Transactions on Electromagnetic
Compatibility, vol. 45, no. 2, pp. 167–176, May 2003.
[11] G. Antonini, D. Deschrijver and T. Dhaene, “Broadband macromodels
for retarded Partial Element Equivalent Circuit (rPEEC) method,” IEEE
Transactions on Electromagnetic Compatibility, vol. 49, no. 1, pp. 34–
48, Feb. 2007.
[12] G. Antonini, A. E. Ruehli and C. Yang, “PEEC modeling of dispersive
dielectrics,” IEEE Transactions on Advanced Packaging, vol. 31, no. 4,
pp. 768–782, Sep. 2008.
[13] T. Lindgren, J. Ekman, and S. Backen, “A measurement system for the
complex far-field of physically large antenna arrays under noisy condi-
tions utilizing the equivalent electric current method,” IEEE Transactions
on Antennas and Propagation, vol. 58, no. 10, pp. 3205–3211, 2010.
[14] L. Yeung and K.-L. Wu, “Generalized partial element equivalent cir-
cuit (PEEC) modeling with radiation effect,” IEEE Transactions on
Microwave Theory and Techniques, vol. 59, no. 10, pp. 2377–2384,
2011.
[15] L. Pillegi, R. Rohrer, C. Visweswariah, Electronic Circuits and System
Simulation Methods. McGraw-Hill Book Company, 1995.
[16] F. N. Najm, Circuit Simulation. John Wiley and Sons, New York, 2010.
[17] A. Fettweis, “Digital filter structures related to classical filter networks,”
Archiv f¨ur Elektronik und ¨Ubertragungstechnik, vol. 25, no. 2, pp. 79–
89, 1971.
[18] ——, “Wave digital filters: theory and practice,” Proceedings of the
IEEE, vol. 74, no. 2, pp. 270–327, Feb 1986.
[19] P. Belforte, U. Colonnelli, and G. Guaschino, “Use of equivalent digital
wave networks in the simulation of the interconnects among high-
speed logic devices,” Alta Frequenza, vol. 11, pp. 649–660, 1976,
http://dx.doi.org/10.13140/RG.2.1.4546.2240.
[20] P. Belforte, B. Bostica, and G. Guaschino, “Time-domain simulation
of lossy interconnection using digital wave networks,” in Proc. of
International Symposium on Circuit and Syestems, ISCAS, Rome, 1982,
http://dx.doi.org/10.13140/RG.2.1.3019.2804.
[21] P. Belforte and G. Guaschino, “Electrical simulation using digital wave
networks,” in Proc. of IASTED International Symposium, Paris, Jun
1985, https://www.doi.org/10.13140/RG.2.1.4447.9207.
[22] P. Belforte, “A high-performance environment for mod-
eling and simulation of digital systems,” in HP High
-Speed Digital Systems Design and Test Symposium,
1993, http://www.hparchive.com/semi ˆAnar notes/1993 High-
Performance Environment for Modelling and Sim ˆA-
ulation of Digital Systems.pdf.
[23] A. Arnulfo, P. Belforte, and F. Maggioni, 3Dpeec V1.0 Users’s Manual
HDT, 1998, http://dx.doi.org/10.13140/RG.2.1.3676.9042.
[24] P. Belforte and G. Guaschino, DWS 8.5: Digital Wave Simulator, 2015,
http://dx.doi.org/10.13140/RG.2.1.1892.0160.
[25] P. Belforte, “Digital wave simulation of lossy lines for multi-gigabit
applications,” IEEE EMC Magazine, vol. 5, no. 2, 2016.
[26] B. P. Sto˘si´c and M. Gmitrovi´c, “Wave digital approach - a different
procedure for modeling of microstrip step discontinuities,” International
Journal of Circuits, Systems and Signal Processing, vol. 2, no. 3, pp.
209–218, 2008.
[27] B. P. Sto˘si´c, D. I. Krsti´c, and J. Jokovi´c, “Matlab/Simulink implemen-
tation of wave-based models for microstrips atructures utilizing short-
circuited and opened stubs,” Electronics, vol. 15, no. 2, pp. 31–38, Dec
2011.
[28] P. Belforte, L. Lombardi, D. Romano, and G. Antonini, “Digital wave
formulation of quasi-static partial element equivalent circuit method,” in
2016 IEEE 20th Workshop on Signal and Power Integrity (SPI), May
2016, pp. 1–4.
[29] A. E. Ruehli and G. Antonini and L. Jiang, The Partial Element
Equivalent Circuit Method for Electromagnetic and Circuit Problems.
New York, NY, USA: Wiley, 2016.
[30] A. E. Ruehli, J. Garrett, C. R. Paul, “Circuit models for 3D structures
with incident fields,” in Proc. of the IEEE Int. Symp. on Electromagnetic
Compatibility, Dallas, Tx, Aug. 1993, pp. 28–31.
[31] H. Heeb and A. Ruehli, “Three-dimensional interconnect analysis using
Partial Element Equivalent Circuits,” IEEE Transactions on Circuits and
Systems, vol. 38, no. 11, pp. 974–981, Nov. 1992.
[32] S. Bilbao, Wave and Scattering Methods for Numerical Simulation.
Wiley, 2004.
[33] Fettweis A, Nitsche G., “Numerical integration of partial differential
equations by means of multidimensional wave digital filters.” Proceeding
IEEE International Symposium on Circuits and Systems, pp. 954–957,
1990.
[34] ——, “Numerical integration of partial differential equations using
principles of multidimensional wave digital filters.” Journal of VLSI
Signal Processing, pp. 7–24, 1991.
[35] G. Antonini and D. Romano, “Efficient frequency-domain analysis
of peec circuits through multiscale compressed decomposition,” IEEE
Transactions on Electromagnetic Compatibility, vol. 56, no. 2, pp. 454–
465, April 2014.
[36] C. Christopoulos, The Transmission-Line Modeling Method: TLM.
IEEE PRESS, 1995.
[37] P. B. Johns and R. L. Beurle, “Numerical solution of 2-dimensional
scattering problems using a transmission-line matrix,” Proceedings of
the IEEE, vol. 59, no. 9, pp. 1203–1208, Sep. 1971.

13. [38] K. Ochs and B. Stein, “On the design and use of wave digital struc-
tures,” Dept Mathematics and Computer Science (Paderborn University),
November 2001.
[39] P. Nenzi and H. Vogt, Ngspice User’s Manual, Jan 2014.
[40] Orcad Pspice Designer, Cadence Design Systems, Inc., 2015.
[41] P. Belforte, “Diode clamped coplanar stripline PEEC
model: LTspice with default settings vs DWS,” July 2016,
http://dx.doi.org/10.13140/RG.2.1.1809.8164.
[42] P. Belforte and G. Antonini, “Extendible/rectractable
5-conductor PEEC-DWS structure,” Mar 2016,
http://dx.doi.org/10.13140/RG.2.1.4260.0087.
[43] P. Belforte, Research Gate, 2016,
https://www.researchgate.net/profile/Piero Belforte.
Luigi Lombardi was born in Larino (CB), Italy.
He received the Laurea degree (cum laude) in elec-
tronic engineering in 2015 University of L’Aquila,
L’Aquila, Italy, where he is currently working toward
the Ph.D. degree.
Piero Belforte Born in Turin in 1947, he re-
ceived his Laurea degree in Electronics Engineering
summa cum laude in 1970 from the Politecnico of
Turin. From 1970 to 2000 he worked in CSELT,
the Research Center of Telecom Italia as Head of
Switching Techniques Department and then as Head
of Hardware Qualification Department. In 1975 he
started the development of several generations of
high-speed modeling and simulation tools using in-
novative DSP algorithms for fast computer simula-
tion of high-speed electronic systems. In 1988 he
founded and directed the company HDT (High Design Technology) for the
development of state-of.-the art CAE tools for SI/PI/EMC prediction based
on digital wave simulation. From 2001 to present he continues his research
activity as Independent Researcher He is author of several publications and
international patents in the field of digital electronics with reference to
digital switching systems and techniques for telecom networks, high-speed
electronics, signal and power integrity, circuital modeling and simulation,
electromagnetic compatibility and test equipment for high performance digital
systems
Giulio Antonini (M94 - SM05) received the Laurea
degree (cum laude) in electrical engineering from
University of L’Aquila, L’Aquila, Italy, in 1994
and the Ph.D. degree in electrical engineering from
University of Rome “La Sapienza” in 1998. Since
1998, he has been with the UAq EMC Laboratory,
University of L’Aquila, where he is currently a
Professor. His scientific interests are in the field of
computational electromagnetics.